at91sam9g20.c revision 256281
1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/10/sys/arm/at91/at91sam9g20.c 239190 2012-08-11 05:45:19Z imp $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35#include <sys/module.h> 36 37#define _ARM32_BUS_DMA_PRIVATE 38#include <machine/bus.h> 39 40#include <arm/at91/at91var.h> 41#include <arm/at91/at91reg.h> 42#include <arm/at91/at91soc.h> 43#include <arm/at91/at91_aicreg.h> 44#include <arm/at91/at91sam9g20reg.h> 45#include <arm/at91/at91_pitreg.h> 46#include <arm/at91/at91_pmcreg.h> 47#include <arm/at91/at91_pmcvar.h> 48#include <arm/at91/at91_rstreg.h> 49 50/* 51 * Standard priority levels for the system. 0 is lowest and 7 is highest. 52 * These values are the ones Atmel uses for its Linux port 53 */ 54static const int at91_irq_prio[32] = 55{ 56 7, /* Advanced Interrupt Controller */ 57 7, /* System Peripherals */ 58 1, /* Parallel IO Controller A */ 59 1, /* Parallel IO Controller B */ 60 1, /* Parallel IO Controller C */ 61 0, /* Analog-to-Digital Converter */ 62 5, /* USART 0 */ 63 5, /* USART 1 */ 64 5, /* USART 2 */ 65 0, /* Multimedia Card Interface */ 66 2, /* USB Device Port */ 67 6, /* Two-Wire Interface */ 68 5, /* Serial Peripheral Interface 0 */ 69 5, /* Serial Peripheral Interface 1 */ 70 5, /* Serial Synchronous Controller */ 71 0, /* (reserved) */ 72 0, /* (reserved) */ 73 0, /* Timer Counter 0 */ 74 0, /* Timer Counter 1 */ 75 0, /* Timer Counter 2 */ 76 2, /* USB Host port */ 77 3, /* Ethernet */ 78 0, /* Image Sensor Interface */ 79 5, /* USART 3 */ 80 5, /* USART 4 */ 81 5, /* USART 5 */ 82 0, /* Timer Counter 3 */ 83 0, /* Timer Counter 4 */ 84 0, /* Timer Counter 5 */ 85 0, /* Advanced Interrupt Controller IRQ0 */ 86 0, /* Advanced Interrupt Controller IRQ1 */ 87 0, /* Advanced Interrupt Controller IRQ2 */ 88}; 89 90#define DEVICE(_name, _id, _unit) \ 91 { \ 92 _name, _unit, \ 93 AT91SAM9G20_ ## _id ##_BASE, \ 94 AT91SAM9G20_ ## _id ## _SIZE, \ 95 AT91SAM9G20_IRQ_ ## _id \ 96 } 97 98static const struct cpu_devs at91_devs[] = 99{ 100 DEVICE("at91_pmc", PMC, 0), 101 DEVICE("at91_wdt", WDT, 0), 102 DEVICE("at91_rst", RSTC, 0), 103 DEVICE("at91_pit", PIT, 0), 104 DEVICE("at91_pio", PIOA, 0), 105 DEVICE("at91_pio", PIOB, 1), 106 DEVICE("at91_pio", PIOC, 2), 107 DEVICE("at91_twi", TWI, 0), 108 DEVICE("at91_mci", MCI, 0), 109 DEVICE("uart", DBGU, 0), 110 DEVICE("uart", USART0, 1), 111 DEVICE("uart", USART1, 2), 112 DEVICE("uart", USART2, 3), 113 DEVICE("uart", USART3, 4), 114 DEVICE("uart", USART4, 5), 115 DEVICE("uart", USART5, 6), 116 DEVICE("spi", SPI0, 0), 117 DEVICE("spi", SPI1, 1), 118 DEVICE("ate", EMAC, 0), 119 DEVICE("macb", EMAC, 0), 120 DEVICE("nand", NAND, 0), 121 DEVICE("ohci", OHCI, 0), 122 { 0, 0, 0, 0, 0 } 123}; 124 125static void 126at91_clock_init(void) 127{ 128 struct at91_pmc_clock *clk; 129 130 /* Update USB device port clock info */ 131 clk = at91_pmc_clock_ref("udpck"); 132 clk->pmc_mask = PMC_SCER_UDP_SAM9; 133 at91_pmc_clock_deref(clk); 134 135 /* Update USB host port clock info */ 136 clk = at91_pmc_clock_ref("uhpck"); 137 clk->pmc_mask = PMC_SCER_UHP_SAM9; 138 at91_pmc_clock_deref(clk); 139 140 /* Each SOC has different PLL contraints */ 141 clk = at91_pmc_clock_ref("plla"); 142 clk->pll_min_in = SAM9G20_PLL_A_MIN_IN_FREQ; /* 2 MHz */ 143 clk->pll_max_in = SAM9G20_PLL_A_MAX_IN_FREQ; /* 32 MHz */ 144 clk->pll_min_out = SAM9G20_PLL_A_MIN_OUT_FREQ; /* 400 MHz */ 145 clk->pll_max_out = SAM9G20_PLL_A_MAX_OUT_FREQ; /* 800 MHz */ 146 clk->pll_mul_shift = SAM9G20_PLL_A_MUL_SHIFT; 147 clk->pll_mul_mask = SAM9G20_PLL_A_MUL_MASK; 148 clk->pll_div_shift = SAM9G20_PLL_A_DIV_SHIFT; 149 clk->pll_div_mask = SAM9G20_PLL_A_DIV_MASK; 150 clk->set_outb = at91_pmc_800mhz_plla_outb; 151 at91_pmc_clock_deref(clk); 152 153 clk = at91_pmc_clock_ref("pllb"); 154 clk->pll_min_in = SAM9G20_PLL_B_MIN_IN_FREQ; /* 2 MHz */ 155 clk->pll_max_in = SAM9G20_PLL_B_MAX_IN_FREQ; /* 32 MHz */ 156 clk->pll_min_out = SAM9G20_PLL_B_MIN_OUT_FREQ; /* 30 MHz */ 157 clk->pll_max_out = SAM9G20_PLL_B_MAX_OUT_FREQ; /* 100 MHz */ 158 clk->pll_mul_shift = SAM9G20_PLL_B_MUL_SHIFT; 159 clk->pll_mul_mask = SAM9G20_PLL_B_MUL_MASK; 160 clk->pll_div_shift = SAM9G20_PLL_B_DIV_SHIFT; 161 clk->pll_div_mask = SAM9G20_PLL_B_DIV_MASK; 162 clk->set_outb = at91_pmc_800mhz_pllb_outb; 163 at91_pmc_clock_deref(clk); 164} 165 166static struct at91_soc_data soc_data = { 167 .soc_delay = at91_pit_delay, 168 .soc_reset = at91_rst_cpu_reset, 169 .soc_clock_init = at91_clock_init, 170 .soc_irq_prio = at91_irq_prio, 171 .soc_children = at91_devs, 172}; 173 174AT91_SOC(AT91_T_SAM9G20, &soc_data); 175