at91rm92reg.h revision 159795
1155324Simp/*- 2155324Simp * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3155324Simp * 4155324Simp * Redistribution and use in source and binary forms, with or without 5155324Simp * modification, are permitted provided that the following conditions 6155324Simp * are met: 7155324Simp * 1. Redistributions of source code must retain the above copyright 8155324Simp * notice, this list of conditions and the following disclaimer. 9155324Simp * 2. Redistributions in binary form must reproduce the above copyright 10155324Simp * notice, this list of conditions and the following disclaimer in the 11155324Simp * documentation and/or other materials provided with the distribution. 12155324Simp * 13155324Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14155324Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15155324Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16155324Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17155324Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18155324Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19155324Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20155324Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21155324Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22155324Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23155324Simp */ 24155324Simp 25155324Simp/* $FreeBSD: head/sys/arm/at91/at91rm92reg.h 159795 2006-06-20 20:13:40Z imp $ */ 26155324Simp 27155324Simp#ifndef AT91RM92REG_H_ 28155324Simp#define AT91RM92REG_H_ 29155324Simp/* 30155324Simp * Memory map, from datasheet : 31155324Simp * 0x00000000 - 0x0ffffffff : Internal Memories 32155324Simp * 0x10000000 - 0x1ffffffff : Chip Select 0 33155324Simp * 0x20000000 - 0x2ffffffff : Chip Select 1 34155324Simp * 0x30000000 - 0x3ffffffff : Chip Select 2 35155324Simp * 0x40000000 - 0x4ffffffff : Chip Select 3 36155324Simp * 0x50000000 - 0x5ffffffff : Chip Select 4 37155324Simp * 0x60000000 - 0x6ffffffff : Chip Select 5 38155324Simp * 0x70000000 - 0x7ffffffff : Chip Select 6 39155324Simp * 0x80000000 - 0x8ffffffff : Chip Select 7 40155324Simp * 0x90000000 - 0xeffffffff : Undefined (Abort) 41155324Simp * 0xf0000000 - 0xfffffffff : Peripherals 42155324Simp */ 43155324Simp 44155324Simp#define AT91RM92_BASE 0xf0000000 45155324Simp/* Usart */ 46155324Simp 47155324Simp#define AT91RM92_USART0_BASE 0xffc0000 48155324Simp#define AT91RM92_USART0_PDC 0xffc0100 49155324Simp#define AT91RM92_USART1_BASE 0xffc4000 50155324Simp#define AT91RM92_USART1_PDC 0xffc4100 51155324Simp#define AT91RM92_USART2_BASE 0xffc8000 52155324Simp#define AT91RM92_USART2_PDC 0xffc8100 53155324Simp#define AT91RM92_USART3_BASE 0xffcc000 54155324Simp#define AT91RM92_USART3_PDC 0xffcc100 55155324Simp#define AT91RM92_USART_SIZE 0x4000 56155324Simp 57155324Simp/* System Registers */ 58155324Simp 59155324Simp#define AT91RM92_SYS_BASE 0xffff000 60155324Simp#define AT91RM92_SYS_SIZE 0x1000 61155324Simp/* Interrupt Controller */ 62155324Simp#define IC_SMR (0) /* Source mode register */ 63155324Simp#define IC_SVR (128) /* Source vector register */ 64155324Simp#define IC_IVR (256) /* IRQ vector register */ 65155324Simp#define IC_FVR (260) /* FIQ vector register */ 66155324Simp#define IC_ISR (264) /* Interrupt status register */ 67155324Simp#define IC_IPR (268) /* Interrupt pending register */ 68155324Simp#define IC_IMR (272) /* Interrupt status register */ 69155324Simp#define IC_CISR (276) /* Core interrupt status register */ 70155324Simp#define IC_IECR (288) /* Interrupt enable command register */ 71155324Simp#define IC_IDCR (292) /* Interrupt disable command register */ 72155324Simp#define IC_ICCR (296) /* Interrupt clear command register */ 73155324Simp#define IC_ISCR (300) /* Interrupt set command register */ 74155324Simp#define IC_EOICR (304) /* End of interrupt command register */ 75155324Simp#define IC_SPU (308) /* Spurious vector register */ 76155324Simp#define IC_DCR (312) /* Debug control register */ 77155324Simp#define IC_FFER (320) /* Fast forcing enable register */ 78155324Simp#define IC_FFDR (324) /* Fast forcing disable register */ 79155324Simp#define IC_FFSR (328) /* Fast forcing status register */ 80155324Simp 81155324Simp/* DBGU */ 82155324Simp 83155324Simp#define DBGU 0x200 84155324Simp#define DBGU_SIZE 0x200 85155324Simp#define DBGU_C1R (0x200 + 64) /* Chip ID1 Register */ 86155324Simp#define DBGU_C2R (0x200 + 68) /* Chip ID2 Register */ 87155324Simp#define DBGU_FNTR (0x200 + 72) /* Force NTRST Register */ 88155324Simp 89155324Simp#define PIOA_PER (0x400) /* PIO Enable Register */ 90155324Simp#define PIOA_PDR (0x400 + 4) /* PIO Disable Register */ 91155324Simp#define PIOA_PSR (0x400 + 8) /* PIO status register */ 92155324Simp#define PIOA_OER (0x400 + 16) /* Output enable register */ 93155324Simp#define PIOA_ODR (0x400 + 20) /* Output disable register */ 94155324Simp#define PIOA_OSR (0x400 + 24) /* Output status register */ 95155324Simp#define PIOA_IFER (0x400 + 32) /* Input filter enable register */ 96155324Simp#define PIOA_IFDR (0x400 + 36) /* Input filter disable register */ 97155324Simp#define PIOA_IFSR (0x400 + 40) /* Input filter status register */ 98155324Simp#define PIOA_SODR (0x400 + 48) /* Set output data register */ 99155324Simp#define PIOA_CODR (0x400 + 52) /* Clear output data register */ 100155324Simp#define PIOA_ODSR (0x400 + 56) /* Output data status register */ 101155324Simp#define PIOA_PDSR (0x400 + 60) /* Pin data status register */ 102155324Simp#define PIOA_IER (0x400 + 64) /* Interrupt enable register */ 103155324Simp#define PIOA_IDR (0x400 + 68) /* Interrupt disable register */ 104155324Simp#define PIOA_IMR (0x400 + 72) /* Interrupt mask register */ 105155324Simp#define PIOA_ISR (0x400 + 76) /* Interrupt status register */ 106155324Simp#define PIOA_MDER (0x400 + 80) /* Multi driver enable register */ 107155324Simp#define PIOA_MDDR (0x400 + 84) /* Multi driver disable register */ 108155324Simp#define PIOA_MDSR (0x400 + 88) /* Multi driver status register */ 109155324Simp#define PIOA_PPUDR (0x400 + 96) /* Pull-up disable register */ 110155324Simp#define PIOA_PPUER (0x400 + 100) /* Pull-up enable register */ 111155324Simp#define PIOA_PPUSR (0x400 + 104) /* Pad pull-up status register */ 112155324Simp#define PIOA_ASR (0x400 + 112) /* Select A register */ 113155324Simp#define PIOA_BSR (0x400 + 116) /* Select B register */ 114155324Simp#define PIOA_ABSR (0x400 + 120) /* AB Select status register */ 115155324Simp#define PIOA_OWER (0x400 + 160) /* Output Write enable register */ 116155324Simp#define PIOA_OWDR (0x400 + 164) /* Output write disable register */ 117155324Simp#define PIOA_OWSR (0x400 + 168) /* Output write status register */ 118155324Simp#define PIOB_PER (0x400) /* PIO Enable Register */ 119155324Simp#define PIOB_PDR (0x600 + 4) /* PIO Disable Register */ 120155324Simp#define PIOB_PSR (0x600 + 8) /* PIO status register */ 121155324Simp#define PIOB_OER (0x600 + 16) /* Output enable register */ 122155324Simp#define PIOB_ODR (0x600 + 20) /* Output disable register */ 123155324Simp#define PIOB_OSR (0x600 + 24) /* Output status register */ 124155324Simp#define PIOB_IFER (0x600 + 32) /* Input filter enable register */ 125155324Simp#define PIOB_IFDR (0x600 + 36) /* Input filter disable register */ 126155324Simp#define PIOB_IFSR (0x600 + 40) /* Input filter status register */ 127155324Simp#define PIOB_SODR (0x600 + 48) /* Set output data register */ 128155324Simp#define PIOB_CODR (0x600 + 52) /* Clear output data register */ 129155324Simp#define PIOB_ODSR (0x600 + 56) /* Output data status register */ 130155324Simp#define PIOB_PDSR (0x600 + 60) /* Pin data status register */ 131155324Simp#define PIOB_IER (0x600 + 64) /* Interrupt enable register */ 132155324Simp#define PIOB_IDR (0x600 + 68) /* Interrupt disable register */ 133155324Simp#define PIOB_IMR (0x600 + 72) /* Interrupt mask register */ 134155324Simp#define PIOB_ISR (0x600 + 76) /* Interrupt status register */ 135155324Simp#define PIOB_MDER (0x600 + 80) /* Multi driver enable register */ 136155324Simp#define PIOB_MDDR (0x600 + 84) /* Multi driver disable register */ 137155324Simp#define PIOB_MDSR (0x600 + 88) /* Multi driver status register */ 138155324Simp#define PIOB_PPUDR (0x600 + 96) /* Pull-up disable register */ 139155324Simp#define PIOB_PPUER (0x600 + 100) /* Pull-up enable register */ 140155324Simp#define PIOB_PPUSR (0x600 + 104) /* Pad pull-up status register */ 141155324Simp#define PIOB_ASR (0x600 + 112) /* Select A register */ 142155324Simp#define PIOB_BSR (0x600 + 116) /* Select B register */ 143155324Simp#define PIOB_ABSR (0x600 + 120) /* AB Select status register */ 144155324Simp#define PIOB_OWER (0x600 + 160) /* Output Write enable register */ 145155324Simp#define PIOB_OWDR (0x600 + 164) /* Output write disable register */ 146155324Simp#define PIOB_OWSR (0x600 + 168) /* Output write status register */ 147155324Simp#define PIOC_PER (0x800) /* PIO Enable Register */ 148155324Simp#define PIOC_PDR (0x800 + 4) /* PIO Disable Register */ 149155324Simp#define PIOC_PSR (0x800 + 8) /* PIO status register */ 150155324Simp#define PIOC_OER (0x800 + 16) /* Output enable register */ 151155324Simp#define PIOC_ODR (0x800 + 20) /* Output disable register */ 152155324Simp#define PIOC_OSR (0x800 + 24) /* Output status register */ 153155324Simp#define PIOC_IFER (0x800 + 32) /* Input filter enable register */ 154155324Simp#define PIOC_IFDR (0x800 + 36) /* Input filter disable register */ 155155324Simp#define PIOC_IFSR (0x800 + 40) /* Input filter status register */ 156155324Simp#define PIOC_SODR (0x800 + 48) /* Set output data register */ 157155324Simp#define PIOC_CODR (0x800 + 52) /* Clear output data register */ 158155324Simp#define PIOC_ODSR (0x800 + 56) /* Output data status register */ 159155324Simp#define PIOC_PDSR (0x800 + 60) /* Pin data status register */ 160155324Simp#define PIOC_IER (0x800 + 64) /* Interrupt enable register */ 161155324Simp#define PIOC_IDR (0x800 + 68) /* Interrupt disable register */ 162155324Simp#define PIOC_IMR (0x800 + 72) /* Interrupt mask register */ 163155324Simp#define PIOC_ISR (0x800 + 76) /* Interrupt status register */ 164155324Simp#define PIOC_MDER (0x800 + 80) /* Multi driver enable register */ 165155324Simp#define PIOC_MDDR (0x800 + 84) /* Multi driver disable register */ 166155324Simp#define PIOC_MDSR (0x800 + 88) /* Multi driver status register */ 167155324Simp#define PIOC_PPUDR (0x800 + 96) /* Pull-up disable register */ 168155324Simp#define PIOC_PPUER (0x800 + 100) /* Pull-up enable register */ 169155324Simp#define PIOC_PPUSR (0x800 + 104) /* Pad pull-up status register */ 170155324Simp#define PIOC_ASR (0x800 + 112) /* Select A register */ 171155324Simp#define PIOC_BSR (0x800 + 116) /* Select B register */ 172155324Simp#define PIOC_ABSR (0x800 + 120) /* AB Select status register */ 173155324Simp#define PIOC_OWER (0x800 + 160) /* Output Write enable register */ 174155324Simp#define PIOC_OWDR (0x800 + 164) /* Output write disable register */ 175155324Simp#define PIOC_OWSR (0x800 + 168) /* Output write status register */ 176155324Simp#define PIOD_PER (0xa00) /* PIO Enable Register */ 177155324Simp#define PIOD_PDR (0xa00 + 4) /* PIO Disable Register */ 178155324Simp#define PIOD_PSR (0xa00 + 8) /* PIO status register */ 179155324Simp#define PIOD_OER (0xa00 + 16) /* Output enable register */ 180155324Simp#define PIOD_ODR (0xa00 + 20) /* Output disable register */ 181155324Simp#define PIOD_OSR (0xa00 + 24) /* Output status register */ 182155324Simp#define PIOD_IFER (0xa00 + 32) /* Input filter enable register */ 183155324Simp#define PIOD_IFDR (0xa00 + 36) /* Input filter disable register */ 184155324Simp#define PIOD_IFSR (0xa00 + 40) /* Input filter status register */ 185155324Simp#define PIOD_SODR (0xa00 + 48) /* Set output data register */ 186155324Simp#define PIOD_CODR (0xa00 + 52) /* Clear output data register */ 187155324Simp#define PIOD_ODSR (0xa00 + 56) /* Output data status register */ 188155324Simp#define PIOD_PDSR (0xa00 + 60) /* Pin data status register */ 189155324Simp#define PIOD_IER (0xa00 + 64) /* Interrupt enable register */ 190155324Simp#define PIOD_IDR (0xa00 + 68) /* Interrupt disable register */ 191155324Simp#define PIOD_IMR (0xa00 + 72) /* Interrupt mask register */ 192155324Simp#define PIOD_ISR (0xa00 + 76) /* Interrupt status register */ 193155324Simp#define PIOD_MDER (0xa00 + 80) /* Multi driver enable register */ 194155324Simp#define PIOD_MDDR (0xa00 + 84) /* Multi driver disable register */ 195155324Simp#define PIOD_MDSR (0xa00 + 88) /* Multi driver status register */ 196155324Simp#define PIOD_PPUDR (0xa00 + 96) /* Pull-up disable register */ 197155324Simp#define PIOD_PPUER (0xa00 + 100) /* Pull-up enable register */ 198155324Simp#define PIOD_PPUSR (0xa00 + 104) /* Pad pull-up status register */ 199155324Simp#define PIOD_ASR (0xa00 + 112) /* Select A register */ 200155324Simp#define PIOD_BSR (0xa00 + 116) /* Select B register */ 201155324Simp#define PIOD_ABSR (0xa00 + 120) /* AB Select status register */ 202155324Simp#define PIOD_OWER (0xa00 + 160) /* Output Write enable register */ 203155324Simp#define PIOD_OWDR (0xa00 + 164) /* Output write disable register */ 204155324Simp#define PIOD_OWSR (0xa00 + 168) /* Output write status register */ 205155324Simp 206156829Simp/* 207156829Simp * PIO 208156829Simp */ 209156829Simp#define AT91RM92_PIOA_BASE 0xffff400 210156829Simp#define AT91RM92_PIO_SIZE 0x200 211156829Simp#define AT91RM92_PIOB_BASE 0xffff600 212156829Simp#define AT91RM92_PIOC_BASE 0xffff800 213156829Simp#define AT91RM92_PIOD_BASE 0xffffa00 214156829Simp 215156829Simp/* 216156829Simp * PMC 217156829Simp */ 218156829Simp#define AT91RM92_PMC_BASE 0xffffc00 219156829Simp#define AT91RM92_PMC_SIZE 0x100 220156829Simp 221155324Simp/* IRQs : */ 222155324Simp/* 223155324Simp * 0: AIC 224155324Simp * 1: System peripheral (System timer, RTC, DBGU) 225155324Simp * 2: PIO Controller A 226155324Simp * 3: PIO Controller B 227155324Simp * 4: PIO Controller C 228155324Simp * 5: PIO Controller D 229155324Simp * 6: USART 0 230155324Simp * 7: USART 1 231155324Simp * 8: USART 2 232155324Simp * 9: USART 3 233155324Simp * 10: MMC Interface 234155324Simp * 11: USB device port 235155324Simp * 12: Two-wirte interface 236155324Simp * 13: SPI 237155324Simp * 14: SSC 238155324Simp * 15: SSC 239155324Simp * 16: SSC 240155324Simp * 17: Timer Counter 0 241155324Simp * 18: Timer Counter 1 242155324Simp * 19: Timer Counter 2 243155324Simp * 20: Timer Counter 3 244155324Simp * 21: Timer Counter 4 245155324Simp * 22: Timer Counter 6 246155324Simp * 23: USB Host port 247155324Simp * 24: Ethernet 248155324Simp * 25: AIC 249155324Simp * 26: AIC 250155324Simp * 27: AIC 251155324Simp * 28: AIC 252155324Simp * 29: AIC 253155324Simp * 30: AIC 254155324Simp * 31: AIC 255155324Simp */ 256155324Simp 257155324Simp#define AT91RM92_IRQ_SYSTEM 1 258155324Simp#define AT91RM92_IRQ_PIOA 2 259155324Simp#define AT91RM92_IRQ_PIOB 3 260155324Simp#define AT91RM92_IRQ_PIOC 4 261155324Simp#define AT91RM92_IRQ_PIOD 5 262155324Simp#define AT91RM92_IRQ_USART0 6 263155324Simp#define AT91RM92_IRQ_USART1 7 264155324Simp#define AT91RM92_IRQ_USART2 8 265155324Simp#define AT91RM92_IRQ_USART3 9 266155324Simp#define AT91RM92_IRQ_MCI 10 267155324Simp#define AT91RM92_IRQ_UDP 11 268155324Simp#define AT91RM92_IRQ_TWI 12 269155324Simp#define AT91RM92_IRQ_SPI 13 270155324Simp#define AT91RM92_IRQ_SSC0 14 271155324Simp#define AT91RM92_IRQ_SSC1 15 272155324Simp#define AT91RM92_IRQ_SSC2 16 273155324Simp#define AT91RM92_IRQ_TC0 17 274155324Simp#define AT91RM92_IRQ_TC1 18 275155324Simp#define AT91RM92_IRQ_TC2 19 276155324Simp#define AT91RM92_IRQ_TC3 20 277155324Simp#define AT91RM92_IRQ_TC4 21 278155324Simp#define AT91RM92_IRQ_TC5 22 279155324Simp#define AT91RM92_IRQ_UHP 23 280155324Simp#define AT91RM92_IRQ_EMAC 24 281155324Simp#define AT91RM92_IRQ_AIC_BASE 25 282155324Simp 283155324Simp/* Timer */ 284155324Simp 285156829Simp#define AT91RM92_AIC_BASE 0xffff000 286156829Simp#define AT91RM92_AIC_SIZE 0x200 287156829Simp 288156829Simp#define AT91RM92_DBGU_BASE 0xffff200 289156829Simp#define AT91RM92_DBGU_SIZE 0x200 290156829Simp 291156829Simp#define AT91RM92_RTC_BASE 0xffffe00 292156829Simp#define AT91RM92_RTC_SIZE 0x100 293156829Simp 294156829Simp#define AT91RM92_MC_BASE 0xfffff00 295156829Simp#define AT91RM92_MC_SIZE 0x100 296156829Simp 297155324Simp#define AT91RM92_ST_BASE 0xffffd00 298155324Simp#define AT91RM92_ST_SIZE 0x100 299155324Simp 300155324Simp#define AT91RM92_SPI_BASE 0xffe0000 301155324Simp#define AT91RM92_SPI_SIZE 0x4000 302155324Simp#define AT91RM92_SPI_PDC 0xffe0100 303155324Simp 304155324Simp#define AT91RM92_SSC0_BASE 0xffd0000 305155324Simp#define AT91RM92_SSC0_PDC 0xffd0100 306155324Simp 307155324Simp#define AT91RM92_SSC1_BASE 0xffd4000 308155324Simp#define AT91RM92_SSC1_PDC 0xffd4100 309155324Simp 310155324Simp#define AT91RM92_SSC2_BASE 0xffd8000 311155324Simp#define AT91RM92_SSC2_PDC 0xffd8100 312155324Simp 313155324Simp#define AT91RM92_SSC_SIZE 0x4000 314155324Simp 315155324Simp#define AT91RM92_EMAC_BASE 0xffbc000 316155324Simp#define AT91RM92_EMAC_SIZE 0x4000 317155324Simp 318155324Simp#define AT91RM92_TWI_BASE 0xffb8000 319155324Simp#define AT91RM92_TWI_SIZE 0x4000 320155324Simp 321155324Simp#define AT91RM92_MCI_BASE 0xffb4000 322155324Simp#define AT91RM92_MCI_PDC 0xffb4100 323155324Simp#define AT91RM92_MCI_SIZE 0x4000 324155324Simp 325155324Simp#define AT91RM92_UDP_BASE 0xffb0000 326155324Simp#define AT91RM92_UDP_SIZE 0x4000 327155324Simp 328155324Simp#define AT91RM92_TC0_BASE 0xffa0000 329156829Simp#define AT91RM92_TC_SIZE 0x4000 330155324Simp#define AT91RM92_TC0C0_BASE 0xffa0000 331155324Simp#define AT91RM92_TC0C1_BASE 0xffa0040 332155324Simp#define AT91RM92_TC0C2_BASE 0xffa0080 333155324Simp 334155324Simp#define AT91RM92_TC1_BASE 0xffa4000 335155324Simp#define AT91RM92_TC1C0_BASE 0xffa4000 336155324Simp#define AT91RM92_TC1C1_BASE 0xffa4040 337155324Simp#define AT91RM92_TC1C2_BASE 0xffa4080 338155324Simp 339155324Simp#define AT91RM92_OHCI_BASE 0x00300000 340155324Simp#define AT91RM92_OHCI_SIZE 0x00100000 341155324Simp 342155324Simp#define AT91C_MASTER_CLOCK 60000000 343155324Simp 344159795Simp/* SDRAMC */ 345159795Simp 346159795Simp#define AT91RM92_SDRAMC_BASE 0xfffff90 347159795Simp#define AT91RM92_SDRAMC_MR 0x00 348159795Simp#define AT91RM92_SDRAMC_MR_MODE_NORMAL 0 349159795Simp#define AT91RM92_SDRAMC_MR_MODE_NOP 1 350159795Simp#define AT91RM92_SDRAMC_MR_MODE_PRECHARGE 2 351159795Simp#define AT91RM92_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3 352159795Simp#define AT91RM92_SDRAMC_MR_MODE_REFRESH 4 353159795Simp#define AT91RM92_SDRAMC_MR_DBW_16 0x10 354159795Simp#define AT91RM92_SDRAMC_TR 0x04 355159795Simp#define AT91RM92_SDRAMC_CR 0x08 356159795Simp#define AT91RM92_SDRAMC_CR_NC_8 0x0 357159795Simp#define AT91RM92_SDRAMC_CR_NC_9 0x1 358159795Simp#define AT91RM92_SDRAMC_CR_NC_10 0x2 359159795Simp#define AT91RM92_SDRAMC_CR_NC_11 0x3 360159795Simp#define AT91RM92_SDRAMC_CR_NC_MASK 0x00000003 361159795Simp#define AT91RM92_SDRAMC_CR_NR_11 0x0 362159795Simp#define AT91RM92_SDRAMC_CR_NR_12 0x4 363159795Simp#define AT91RM92_SDRAMC_CR_NR_13 0x8 364159795Simp#define AT91RM92_SDRAMC_CR_NR_RES 0xc 365159795Simp#define AT91RM92_SDRAMC_CR_NR_MASK 0x0000000c 366159795Simp#define AT91RM92_SDRAMC_CR_NB_2 0x00 367159795Simp#define AT91RM92_SDRAMC_CR_NB_4 0x10 368159795Simp#define AT91RM92_SDRAMC_CR_NB_MASK 0x00000010 369159795Simp#define AT91RM92_SDRAMC_CR_NCAS_MASK 0x00000060 370159795Simp#define AT91RM92_SDRAMC_CR_TWR_MASK 0x00000780 371159795Simp#define AT91RM92_SDRAMC_CR_TRC_MASK 0x00007800 372159795Simp#define AT91RM92_SDRAMC_CR_TRP_MASK 0x00078000 373159795Simp#define AT91RM92_SDRAMC_CR_TRCD_MASK 0x00780000 374159795Simp#define AT91RM92_SDRAMC_CR_TRAS_MASK 0x07800000 375159795Simp#define AT91RM92_SDRAMC_CR_TXSR_MASK 0x78000000 376159795Simp#define AT91RM92_SDRAMC_SRR 0x0c 377159795Simp#define AT91RM92_SDRAMC_LPR 0x10 378159795Simp#define AT91RM92_SDRAMC_IER 0x14 379159795Simp#define AT91RM92_SDRAMC_IDR 0x18 380159795Simp#define AT91RM92_SDRAMC_IMR 0x1c 381159795Simp#define AT91RM92_SDRAMC_ISR 0x20 382159795Simp#define AT91RM92_SDRAMC_IER_RES 0x1 383159795Simp 384155324Simp#endif /* AT91RM92REG_H_ */ 385