1155324Simp/*- 2155324Simp * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3155324Simp * 4155324Simp * Redistribution and use in source and binary forms, with or without 5155324Simp * modification, are permitted provided that the following conditions 6155324Simp * are met: 7155324Simp * 1. Redistributions of source code must retain the above copyright 8155324Simp * notice, this list of conditions and the following disclaimer. 9155324Simp * 2. Redistributions in binary form must reproduce the above copyright 10155324Simp * notice, this list of conditions and the following disclaimer in the 11155324Simp * documentation and/or other materials provided with the distribution. 12155324Simp * 13185265Simp * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14185265Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15185265Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16185265Simp * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17185265Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18185265Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19185265Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20185265Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21185265Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22185265Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23185265Simp * SUCH DAMAGE. 24155324Simp */ 25155324Simp 26155324Simp/* $FreeBSD: releng/10.2/sys/arm/at91/at91rm92reg.h 266110 2014-05-15 02:41:23Z ian $ */ 27155324Simp 28155324Simp#ifndef AT91RM92REG_H_ 29155324Simp#define AT91RM92REG_H_ 30213496Scognet 31213496Scognet/* Chip Specific limits */ 32213496Scognet#define RM9200_PLL_A_MIN_IN_FREQ 1000000 /* 1 MHz */ 33213496Scognet#define RM9200_PLL_A_MAX_IN_FREQ 32000000 /* 32 MHz */ 34213496Scognet#define RM9200_PLL_A_MIN_OUT_FREQ 80000000 /* 80 MHz */ 35213496Scognet#define RM9200_PLL_A_MAX_OUT_FREQ 180000000 /* 180 MHz */ 36213496Scognet#define RM9200_PLL_A_MUL_SHIFT 16 37236989Simp#define RM9200_PLL_A_MUL_MASK 0x7FF 38213496Scognet#define RM9200_PLL_A_DIV_SHIFT 0 39236989Simp#define RM9200_PLL_A_DIV_MASK 0xFF 40213496Scognet 41213496Scognet/* 42213496Scognet * PLL B input frequency spec sheet says it must be between 1MHz and 32MHz, 43213496Scognet * but it works down as low as 100kHz, a frequency necessary for some 44213496Scognet * output frequencies to work. 45213496Scognet * 46213496Scognet * PLL Max output frequency is 240MHz. The errata says 180MHz is the max 47213496Scognet * for some revisions of this part. Be more permissive and optimistic. 48213496Scognet */ 49213496Scognet#define RM9200_PLL_B_MIN_IN_FREQ 100000 /* 100 KHz */ 50213496Scognet#define RM9200_PLL_B_MAX_IN_FREQ 32000000 /* 32 MHz */ 51213496Scognet#define RM9200_PLL_B_MIN_OUT_FREQ 30000000 /* 30 MHz */ 52213496Scognet#define RM9200_PLL_B_MAX_OUT_FREQ 240000000 /* 240 MHz */ 53213496Scognet#define RM9200_PLL_B_MUL_SHIFT 16 54236989Simp#define RM9200_PLL_B_MUL_MASK 0x7FF 55213496Scognet#define RM9200_PLL_B_DIV_SHIFT 0 56236989Simp#define RM9200_PLL_B_DIV_MASK 0xFF 57236989Simp 58236989Simp/* 59155324Simp * Memory map, from datasheet : 60155324Simp * 0x00000000 - 0x0ffffffff : Internal Memories 61155324Simp * 0x10000000 - 0x1ffffffff : Chip Select 0 62155324Simp * 0x20000000 - 0x2ffffffff : Chip Select 1 63155324Simp * 0x30000000 - 0x3ffffffff : Chip Select 2 64155324Simp * 0x40000000 - 0x4ffffffff : Chip Select 3 65155324Simp * 0x50000000 - 0x5ffffffff : Chip Select 4 66155324Simp * 0x60000000 - 0x6ffffffff : Chip Select 5 67155324Simp * 0x70000000 - 0x7ffffffff : Chip Select 6 68155324Simp * 0x80000000 - 0x8ffffffff : Chip Select 7 69155324Simp * 0x90000000 - 0xeffffffff : Undefined (Abort) 70155324Simp * 0xf0000000 - 0xfffffffff : Peripherals 71155324Simp */ 72155324Simp 73155324Simp/* Usart */ 74155324Simp 75213496Scognet#define AT91RM92_USART_SIZE 0x4000 76155324Simp#define AT91RM92_USART0_BASE 0xffc0000 77155324Simp#define AT91RM92_USART0_PDC 0xffc0100 78213496Scognet#define AT91RM92_USART0_SIZE AT91RM92_USART_SIZE 79155324Simp#define AT91RM92_USART1_BASE 0xffc4000 80155324Simp#define AT91RM92_USART1_PDC 0xffc4100 81213496Scognet#define AT91RM92_USART1_SIZE AT91RM92_USART_SIZE 82155324Simp#define AT91RM92_USART2_BASE 0xffc8000 83155324Simp#define AT91RM92_USART2_PDC 0xffc8100 84213496Scognet#define AT91RM92_USART2_SIZE AT91RM92_USART_SIZE 85155324Simp#define AT91RM92_USART3_BASE 0xffcc000 86155324Simp#define AT91RM92_USART3_PDC 0xffcc100 87213496Scognet#define AT91RM92_USART3_SIZE AT91RM92_USART_SIZE 88155324Simp 89155324Simp/* System Registers */ 90155324Simp 91155324Simp#define AT91RM92_SYS_BASE 0xffff000 92155324Simp#define AT91RM92_SYS_SIZE 0x1000 93213496Scognet 94156829Simp/* 95156829Simp * PIO 96156829Simp */ 97213496Scognet#define AT91RM92_PIO_SIZE 0x200 98156829Simp#define AT91RM92_PIOA_BASE 0xffff400 99213496Scognet#define AT91RM92_PIOA_SIZE AT91RM92_PIO_SIZE 100156829Simp#define AT91RM92_PIOB_BASE 0xffff600 101213496Scognet#define AT91RM92_PIOB_SIZE AT91RM92_PIO_SIZE 102156829Simp#define AT91RM92_PIOC_BASE 0xffff800 103213496Scognet#define AT91RM92_PIOC_SIZE AT91RM92_PIO_SIZE 104156829Simp#define AT91RM92_PIOD_BASE 0xffffa00 105213496Scognet#define AT91RM92_PIOD_SIZE AT91RM92_PIO_SIZE 106156829Simp 107156829Simp/* 108156829Simp * PMC 109156829Simp */ 110156829Simp#define AT91RM92_PMC_BASE 0xffffc00 111156829Simp#define AT91RM92_PMC_SIZE 0x100 112156829Simp 113155324Simp/* IRQs : */ 114155324Simp/* 115236989Simp * 0: AIC 116155324Simp * 1: System peripheral (System timer, RTC, DBGU) 117155324Simp * 2: PIO Controller A 118155324Simp * 3: PIO Controller B 119155324Simp * 4: PIO Controller C 120155324Simp * 5: PIO Controller D 121155324Simp * 6: USART 0 122155324Simp * 7: USART 1 123155324Simp * 8: USART 2 124155324Simp * 9: USART 3 125155324Simp * 10: MMC Interface 126155324Simp * 11: USB device port 127155324Simp * 12: Two-wirte interface 128155324Simp * 13: SPI 129155324Simp * 14: SSC 130155324Simp * 15: SSC 131155324Simp * 16: SSC 132155324Simp * 17: Timer Counter 0 133155324Simp * 18: Timer Counter 1 134155324Simp * 19: Timer Counter 2 135155324Simp * 20: Timer Counter 3 136155324Simp * 21: Timer Counter 4 137155324Simp * 22: Timer Counter 6 138155324Simp * 23: USB Host port 139155324Simp * 24: Ethernet 140155324Simp * 25: AIC 141155324Simp * 26: AIC 142155324Simp * 27: AIC 143155324Simp * 28: AIC 144155324Simp * 29: AIC 145155324Simp * 30: AIC 146155324Simp * 31: AIC 147155324Simp */ 148155324Simp 149155324Simp#define AT91RM92_IRQ_SYSTEM 1 150155324Simp#define AT91RM92_IRQ_PIOA 2 151155324Simp#define AT91RM92_IRQ_PIOB 3 152155324Simp#define AT91RM92_IRQ_PIOC 4 153155324Simp#define AT91RM92_IRQ_PIOD 5 154155324Simp#define AT91RM92_IRQ_USART0 6 155155324Simp#define AT91RM92_IRQ_USART1 7 156155324Simp#define AT91RM92_IRQ_USART2 8 157155324Simp#define AT91RM92_IRQ_USART3 9 158155324Simp#define AT91RM92_IRQ_MCI 10 159155324Simp#define AT91RM92_IRQ_UDP 11 160155324Simp#define AT91RM92_IRQ_TWI 12 161155324Simp#define AT91RM92_IRQ_SPI 13 162155324Simp#define AT91RM92_IRQ_SSC0 14 163155324Simp#define AT91RM92_IRQ_SSC1 15 164155324Simp#define AT91RM92_IRQ_SSC2 16 165213496Scognet#define AT91RM92_IRQ_TC0 17,18,19 166213496Scognet#define AT91RM92_IRQ_TC0C0 17 167213496Scognet#define AT91RM92_IRQ_TC0C1 18 168213496Scognet#define AT91RM92_IRQ_TC0C2 19 169213496Scognet#define AT91RM92_IRQ_TC1 20,21,22 170213496Scognet#define AT91RM92_IRQ_TC1C1 20 171213496Scognet#define AT91RM92_IRQ_TC1C2 21 172213496Scognet#define AT91RM92_IRQ_TC1C3 22 173155324Simp#define AT91RM92_IRQ_UHP 23 174155324Simp#define AT91RM92_IRQ_EMAC 24 175213496Scognet#define AT91RM92_IRQ_AIC_IRQ0 25 176213496Scognet#define AT91RM92_IRQ_AIC_IRQ1 26 177213496Scognet#define AT91RM92_IRQ_AIC_IRQ2 27 178213496Scognet#define AT91RM92_IRQ_AIC_IRQ3 28 179213496Scognet#define AT91RM92_IRQ_AIC_IRQ4 29 180213496Scognet#define AT91RM92_IRQ_AIC_IRQ5 30 181213496Scognet#define AT91RM92_IRQ_AIC_IRQ6 31 182155324Simp 183213496Scognet/* Alias */ 184213496Scognet#define AT91RM92_IRQ_DBGU AT91RM92_IRQ_SYSTEM 185213496Scognet#define AT91RM92_IRQ_PMC AT91RM92_IRQ_SYSTEM 186213496Scognet#define AT91RM92_IRQ_ST AT91RM92_IRQ_SYSTEM 187213496Scognet#define AT91RM92_IRQ_RTC AT91RM92_IRQ_SYSTEM 188213496Scognet#define AT91RM92_IRQ_MC AT91RM92_IRQ_SYSTEM 189213496Scognet#define AT91RM92_IRQ_OHCI AT91RM92_IRQ_UHP 190213496Scognet#define AT91RM92_IRQ_AIC -1 191213496Scognet#define AT91RM92_IRQ_CF -1 192213496Scognet 193155324Simp/* Timer */ 194155324Simp 195156829Simp#define AT91RM92_AIC_BASE 0xffff000 196156829Simp#define AT91RM92_AIC_SIZE 0x200 197156829Simp 198213496Scognet/* DBGU */ 199156829Simp#define AT91RM92_DBGU_BASE 0xffff200 200156829Simp#define AT91RM92_DBGU_SIZE 0x200 201156829Simp 202156829Simp#define AT91RM92_RTC_BASE 0xffffe00 203156829Simp#define AT91RM92_RTC_SIZE 0x100 204156829Simp 205156829Simp#define AT91RM92_MC_BASE 0xfffff00 206156829Simp#define AT91RM92_MC_SIZE 0x100 207156829Simp 208155324Simp#define AT91RM92_ST_BASE 0xffffd00 209155324Simp#define AT91RM92_ST_SIZE 0x100 210155324Simp 211155324Simp#define AT91RM92_SPI_BASE 0xffe0000 212155324Simp#define AT91RM92_SPI_SIZE 0x4000 213155324Simp#define AT91RM92_SPI_PDC 0xffe0100 214155324Simp 215213496Scognet#define AT91RM92_SSC_SIZE 0x4000 216155324Simp#define AT91RM92_SSC0_BASE 0xffd0000 217155324Simp#define AT91RM92_SSC0_PDC 0xffd0100 218213496Scognet#define AT91RM92_SSC0_SIZE AT91RM92_SSC_SIZE 219155324Simp 220155324Simp#define AT91RM92_SSC1_BASE 0xffd4000 221155324Simp#define AT91RM92_SSC1_PDC 0xffd4100 222213496Scognet#define AT91RM92_SSC1_SIZE AT91RM92_SSC_SIZE 223155324Simp 224155324Simp#define AT91RM92_SSC2_BASE 0xffd8000 225155324Simp#define AT91RM92_SSC2_PDC 0xffd8100 226213496Scognet#define AT91RM92_SSC2_SIZE AT91RM92_SSC_SIZE 227155324Simp 228155324Simp#define AT91RM92_EMAC_BASE 0xffbc000 229155324Simp#define AT91RM92_EMAC_SIZE 0x4000 230155324Simp 231155324Simp#define AT91RM92_TWI_BASE 0xffb8000 232155324Simp#define AT91RM92_TWI_SIZE 0x4000 233155324Simp 234155324Simp#define AT91RM92_MCI_BASE 0xffb4000 235155324Simp#define AT91RM92_MCI_PDC 0xffb4100 236155324Simp#define AT91RM92_MCI_SIZE 0x4000 237155324Simp 238155324Simp#define AT91RM92_UDP_BASE 0xffb0000 239155324Simp#define AT91RM92_UDP_SIZE 0x4000 240155324Simp 241213496Scognet#define AT91RM92_TC_SIZE 0x4000 242155324Simp#define AT91RM92_TC0_BASE 0xffa0000 243213496Scognet#define AT91RM92_TC0_SIZE AT91RM92_TC_SIZE 244155324Simp#define AT91RM92_TC0C0_BASE 0xffa0000 245155324Simp#define AT91RM92_TC0C1_BASE 0xffa0040 246155324Simp#define AT91RM92_TC0C2_BASE 0xffa0080 247155324Simp 248155324Simp#define AT91RM92_TC1_BASE 0xffa4000 249213496Scognet#define AT91RM92_TC1_SIZE AT91RM92_TC_SIZE 250155324Simp#define AT91RM92_TC1C0_BASE 0xffa4000 251155324Simp#define AT91RM92_TC1C1_BASE 0xffa4040 252155324Simp#define AT91RM92_TC1C2_BASE 0xffa4080 253155324Simp 254213496Scognet/* XXX Needs to be carfully coordinated with 255213496Scognet * other * soc's so phyical and vm address 256213496Scognet * mapping are unique. XXX 257213496Scognet */ 258266110Sian#define AT91RM92_OHCI_VA_BASE 0xdfe00000 259266110Sian#define AT91RM92_OHCI_BASE 0x00300000 260155324Simp#define AT91RM92_OHCI_SIZE 0x00100000 261155324Simp 262266110Sian#define AT91RM92_CF_VA_BASE 0xdfd00000 263266110Sian#define AT91RM92_CF_BASE 0x51400000 264191408Sstas#define AT91RM92_CF_SIZE 0x00100000 265191408Sstas 266159795Simp/* SDRAMC */ 267159795Simp 268159795Simp#define AT91RM92_SDRAMC_BASE 0xfffff90 269159795Simp#define AT91RM92_SDRAMC_MR 0x00 270159795Simp#define AT91RM92_SDRAMC_MR_MODE_NORMAL 0 271159795Simp#define AT91RM92_SDRAMC_MR_MODE_NOP 1 272159795Simp#define AT91RM92_SDRAMC_MR_MODE_PRECHARGE 2 273159795Simp#define AT91RM92_SDRAMC_MR_MODE_LOAD_MODE_REGISTER 3 274159795Simp#define AT91RM92_SDRAMC_MR_MODE_REFRESH 4 275159795Simp#define AT91RM92_SDRAMC_MR_DBW_16 0x10 276159795Simp#define AT91RM92_SDRAMC_TR 0x04 277159795Simp#define AT91RM92_SDRAMC_CR 0x08 278159795Simp#define AT91RM92_SDRAMC_CR_NC_8 0x0 279159795Simp#define AT91RM92_SDRAMC_CR_NC_9 0x1 280159795Simp#define AT91RM92_SDRAMC_CR_NC_10 0x2 281159795Simp#define AT91RM92_SDRAMC_CR_NC_11 0x3 282159795Simp#define AT91RM92_SDRAMC_CR_NC_MASK 0x00000003 283159795Simp#define AT91RM92_SDRAMC_CR_NR_11 0x0 284159795Simp#define AT91RM92_SDRAMC_CR_NR_12 0x4 285159795Simp#define AT91RM92_SDRAMC_CR_NR_13 0x8 286159795Simp#define AT91RM92_SDRAMC_CR_NR_RES 0xc 287159795Simp#define AT91RM92_SDRAMC_CR_NR_MASK 0x0000000c 288159795Simp#define AT91RM92_SDRAMC_CR_NB_2 0x00 289159795Simp#define AT91RM92_SDRAMC_CR_NB_4 0x10 290159795Simp#define AT91RM92_SDRAMC_CR_NB_MASK 0x00000010 291159795Simp#define AT91RM92_SDRAMC_CR_NCAS_MASK 0x00000060 292159795Simp#define AT91RM92_SDRAMC_CR_TWR_MASK 0x00000780 293159795Simp#define AT91RM92_SDRAMC_CR_TRC_MASK 0x00007800 294159795Simp#define AT91RM92_SDRAMC_CR_TRP_MASK 0x00078000 295159795Simp#define AT91RM92_SDRAMC_CR_TRCD_MASK 0x00780000 296159795Simp#define AT91RM92_SDRAMC_CR_TRAS_MASK 0x07800000 297159795Simp#define AT91RM92_SDRAMC_CR_TXSR_MASK 0x78000000 298159795Simp#define AT91RM92_SDRAMC_SRR 0x0c 299159795Simp#define AT91RM92_SDRAMC_LPR 0x10 300159795Simp#define AT91RM92_SDRAMC_IER 0x14 301159795Simp#define AT91RM92_SDRAMC_IDR 0x18 302159795Simp#define AT91RM92_SDRAMC_IMR 0x1c 303159795Simp#define AT91RM92_SDRAMC_ISR 0x20 304159795Simp#define AT91RM92_SDRAMC_IER_RES 0x1 305159795Simp 306155324Simp#endif /* AT91RM92REG_H_ */ 307