at91rm9200.c revision 238348
1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * Copyright (c) 2010 Greg Ansley. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: head/sys/arm/at91/at91rm9200.c 238348 2012-07-10 15:02:29Z imp $"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/malloc.h> 35#include <sys/module.h> 36 37#define _ARM32_BUS_DMA_PRIVATE 38#include <machine/bus.h> 39 40#include <arm/at91/at91var.h> 41#include <arm/at91/at91reg.h> 42#include <arm/at91/at91rm92reg.h> 43#include <arm/at91/at91_aicreg.h> 44#include <arm/at91/at91_pmcreg.h> 45#include <arm/at91/at91_pmcvar.h> 46 47struct at91rm92_softc { 48 device_t dev; 49 bus_space_tag_t sc_st; 50 bus_space_handle_t sc_sh; 51 bus_space_handle_t sc_sys_sh; 52 bus_space_handle_t sc_aic_sh; 53 bus_space_handle_t sc_dbg_sh; 54 bus_space_handle_t sc_matrix_sh; 55}; 56/* 57 * Standard priority levels for the system. 0 is lowest and 7 is highest. 58 * These values are the ones Atmel uses for its Linux port, which differ 59 * a little form the ones that are in the standard distribution. Also, 60 * the ones marked with 'TWEEK' are different based on experience. 61 */ 62static const int at91_irq_prio[32] = 63{ 64 7, /* Advanced Interrupt Controller (FIQ) */ 65 7, /* System Peripherals */ 66 1, /* Parallel IO Controller A */ 67 1, /* Parallel IO Controller B */ 68 1, /* Parallel IO Controller C */ 69 1, /* Parallel IO Controller D */ 70 5, /* USART 0 */ 71 5, /* USART 1 */ 72 5, /* USART 2 */ 73 5, /* USART 3 */ 74 0, /* Multimedia Card Interface */ 75 2, /* USB Device Port */ 76 4, /* Two-Wire Interface */ /* TWEEK */ 77 5, /* Serial Peripheral Interface */ 78 4, /* Serial Synchronous Controller 0 */ 79 6, /* Serial Synchronous Controller 1 */ /* TWEEK */ 80 4, /* Serial Synchronous Controller 2 */ 81 0, /* Timer Counter 0 */ 82 6, /* Timer Counter 1 */ /* TWEEK */ 83 0, /* Timer Counter 2 */ 84 0, /* Timer Counter 3 */ 85 0, /* Timer Counter 4 */ 86 0, /* Timer Counter 5 */ 87 2, /* USB Host port */ 88 3, /* Ethernet MAC */ 89 0, /* Advanced Interrupt Controller (IRQ0) */ 90 0, /* Advanced Interrupt Controller (IRQ1) */ 91 0, /* Advanced Interrupt Controller (IRQ2) */ 92 0, /* Advanced Interrupt Controller (IRQ3) */ 93 0, /* Advanced Interrupt Controller (IRQ4) */ 94 0, /* Advanced Interrupt Controller (IRQ5) */ 95 0 /* Advanced Interrupt Controller (IRQ6) */ 96}; 97 98#define DEVICE(_name, _id, _unit) \ 99 { \ 100 _name, _unit, \ 101 AT91RM92_ ## _id ##_BASE, \ 102 AT91RM92_ ## _id ## _SIZE, \ 103 AT91RM92_IRQ_ ## _id \ 104 } 105 106static const struct cpu_devs at91_devs[] = 107{ 108 DEVICE("at91_pmc", PMC, 0), 109 DEVICE("at91_st", ST, 0), 110 DEVICE("at91_pio", PIOA, 0), 111 DEVICE("at91_pio", PIOB, 1), 112 DEVICE("at91_pio", PIOC, 2), 113 DEVICE("at91_pio", PIOD, 3), 114 DEVICE("at91_rtc", RTC, 0), 115 116 DEVICE("at91_mci", MCI, 0), 117 DEVICE("at91_twi", TWI, 0), 118 DEVICE("at91_udp", UDP, 0), 119 DEVICE("ate", EMAC, 0), 120 DEVICE("at91_ssc", SSC0, 0), 121 DEVICE("at91_ssc", SSC1, 1), 122 DEVICE("at91_ssc", SSC2, 2), 123 DEVICE("spi", SPI, 0), 124 125 DEVICE("uart", DBGU, 0), 126 DEVICE("uart", USART0, 1), 127 DEVICE("uart", USART1, 2), 128 DEVICE("uart", USART2, 3), 129 DEVICE("uart", USART3, 4), 130 DEVICE("at91_aic", AIC, 0), 131 DEVICE("at91_mc", MC, 0), 132 DEVICE("at91_tc", TC0, 0), 133 DEVICE("at91_tc", TC1, 1), 134 DEVICE("ohci", OHCI, 0), 135 DEVICE("af91_cfata", CF, 0), 136 { 0, 0, 0, 0, 0 } 137}; 138 139static void 140at91_cpu_add_builtin_children(device_t dev) 141{ 142 int i; 143 const struct cpu_devs *walker; 144 145 for (i = 1, walker = at91_devs; walker->name; i++, walker++) { 146 at91_add_child(dev, i, walker->name, walker->unit, 147 walker->mem_base, walker->mem_len, walker->irq0, 148 walker->irq1, walker->irq2); 149 } 150} 151 152static uint32_t 153at91_pll_outb(int freq) 154{ 155 156 if (freq > 155000000) 157 return (0x0000); 158 else 159 return (0x8000); 160} 161 162static void 163at91_identify(driver_t *drv, device_t parent) 164{ 165 166 if (at91_cpu_is(AT91_T_RM9200)) { 167 at91_add_child(parent, 0, "at91rm920", 0, 0, 0, -1, 0, 0); 168 at91_cpu_add_builtin_children(parent); 169 } 170} 171 172static int 173at91_probe(device_t dev) 174{ 175 176 device_set_desc(dev, soc_data.name); 177 return (0); 178} 179 180static int 181at91_attach(device_t dev) 182{ 183 struct at91_pmc_clock *clk; 184 struct at91rm92_softc *sc = device_get_softc(dev); 185 int i; 186 187 struct at91_softc *at91sc = device_get_softc(device_get_parent(dev)); 188 189 sc->sc_st = at91sc->sc_st; 190 sc->sc_sh = at91sc->sc_sh; 191 sc->dev = dev; 192 193 if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_SYS_BASE, 194 AT91RM92_SYS_SIZE, &sc->sc_sys_sh) != 0) 195 panic("Enable to map system registers"); 196 197 if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_DBGU_BASE, 198 AT91RM92_DBGU_SIZE, &sc->sc_dbg_sh) != 0) 199 panic("Enable to map DBGU registers"); 200 201 if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_AIC_BASE, 202 AT91RM92_AIC_SIZE, &sc->sc_aic_sh) != 0) 203 panic("Enable to map system registers"); 204 205 /* XXX Hack to tell atmelarm about the AIC */ 206 at91sc->sc_aic_sh = sc->sc_aic_sh; 207 208 for (i = 0; i < 32; i++) { 209 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SVR + 210 i * 4, i); 211 /* Priority. */ 212 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SMR + i * 4, 213 at91_irq_prio[i]); 214 if (i < 8) 215 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_EOICR, 216 1); 217 } 218 219 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_SPU, 32); 220 /* No debug. */ 221 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_DCR, 0); 222 /* Disable and clear all interrupts. */ 223 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_IDCR, 0xffffffff); 224 bus_space_write_4(sc->sc_st, sc->sc_aic_sh, IC_ICCR, 0xffffffff); 225 226 /* Disable all interrupts for RTC (0xe24 == RTC_IDR) */ 227 bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xe24, 0xffffffff); 228 229 /* Disable all interrupts for the SDRAM controller */ 230 bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xfa8, 0xffffffff); 231 232 /* Disable all interrupts for DBGU */ 233 bus_space_write_4(sc->sc_st, sc->sc_dbg_sh, 0x0c, 0xffffffff); 234 235 /* Update USB device port clock info */ 236 clk = at91_pmc_clock_ref("udpck"); 237 clk->pmc_mask = PMC_SCER_UDP; 238 at91_pmc_clock_deref(clk); 239 240 /* Update USB host port clock info */ 241 clk = at91_pmc_clock_ref("uhpck"); 242 clk->pmc_mask = PMC_SCER_UHP; 243 at91_pmc_clock_deref(clk); 244 245 /* Each SOC has different PLL contraints */ 246 clk = at91_pmc_clock_ref("plla"); 247 clk->pll_min_in = RM9200_PLL_A_MIN_IN_FREQ; /* 1 MHz */ 248 clk->pll_max_in = RM9200_PLL_A_MAX_IN_FREQ; /* 32 MHz */ 249 clk->pll_min_out = RM9200_PLL_A_MIN_OUT_FREQ; /* 80 MHz */ 250 clk->pll_max_out = RM9200_PLL_A_MAX_OUT_FREQ; /* 180 MHz */ 251 clk->pll_mul_shift = RM9200_PLL_A_MUL_SHIFT; 252 clk->pll_mul_mask = RM9200_PLL_A_MUL_MASK; 253 clk->pll_div_shift = RM9200_PLL_A_DIV_SHIFT; 254 clk->pll_div_mask = RM9200_PLL_A_DIV_MASK; 255 clk->set_outb = at91_pll_outb; 256 at91_pmc_clock_deref(clk); 257 258 clk = at91_pmc_clock_ref("pllb"); 259 clk->pll_min_in = RM9200_PLL_B_MIN_IN_FREQ; /* 100 KHz */ 260 clk->pll_max_in = RM9200_PLL_B_MAX_IN_FREQ; /* 32 MHz */ 261 clk->pll_min_out = RM9200_PLL_B_MIN_OUT_FREQ; /* 30 MHz */ 262 clk->pll_max_out = RM9200_PLL_B_MAX_OUT_FREQ; /* 240 MHz */ 263 clk->pll_mul_shift = RM9200_PLL_B_MUL_SHIFT; 264 clk->pll_mul_mask = RM9200_PLL_B_MUL_MASK; 265 clk->pll_div_shift = RM9200_PLL_B_DIV_SHIFT; 266 clk->pll_div_mask = RM9200_PLL_B_DIV_MASK; 267 clk->set_outb = at91_pll_outb; 268 at91_pmc_clock_deref(clk); 269 270 return (0); 271} 272 273static device_method_t at91_methods[] = { 274 DEVMETHOD(device_probe, at91_probe), 275 DEVMETHOD(device_attach, at91_attach), 276 DEVMETHOD(device_identify, at91_identify), 277 {0, 0}, 278}; 279 280static driver_t at91rm92_driver = { 281 "at91rm920", 282 at91_methods, 283 sizeof(struct at91rm92_softc), 284}; 285 286static devclass_t at91rm92_devclass; 287 288DRIVER_MODULE(at91rm920, atmelarm, at91rm92_driver, at91rm92_devclass, 0, 0); 289