at91rm9200.c revision 238390
1213496Scognet/*- 2213496Scognet * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3213496Scognet * Copyright (c) 2010 Greg Ansley. All rights reserved. 4213496Scognet * 5213496Scognet * Redistribution and use in source and binary forms, with or without 6213496Scognet * modification, are permitted provided that the following conditions 7213496Scognet * are met: 8213496Scognet * 1. Redistributions of source code must retain the above copyright 9213496Scognet * notice, this list of conditions and the following disclaimer. 10213496Scognet * 2. Redistributions in binary form must reproduce the above copyright 11213496Scognet * notice, this list of conditions and the following disclaimer in the 12213496Scognet * documentation and/or other materials provided with the distribution. 13213496Scognet * 14213496Scognet * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15213496Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16213496Scognet * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17213496Scognet * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18213496Scognet * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19213496Scognet * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20213496Scognet * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21213496Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22213496Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23213496Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24213496Scognet * SUCH DAMAGE. 25213496Scognet */ 26213496Scognet 27213496Scognet#include <sys/cdefs.h> 28213496Scognet__FBSDID("$FreeBSD: head/sys/arm/at91/at91rm9200.c 238390 2012-07-12 04:23:11Z imp $"); 29213496Scognet 30213496Scognet#include <sys/param.h> 31213496Scognet#include <sys/systm.h> 32213496Scognet#include <sys/bus.h> 33213496Scognet#include <sys/kernel.h> 34213496Scognet#include <sys/malloc.h> 35213496Scognet#include <sys/module.h> 36213496Scognet 37213496Scognet#define _ARM32_BUS_DMA_PRIVATE 38213496Scognet#include <machine/bus.h> 39213496Scognet 40213496Scognet#include <arm/at91/at91var.h> 41238331Simp#include <arm/at91/at91reg.h> 42213496Scognet#include <arm/at91/at91rm92reg.h> 43213496Scognet#include <arm/at91/at91_aicreg.h> 44213496Scognet#include <arm/at91/at91_pmcreg.h> 45238376Simp#include <arm/at91/at91_streg.h> 46213496Scognet#include <arm/at91/at91_pmcvar.h> 47238376Simp#include <arm/at91/at91soc.h> 48213496Scognet 49238376Simp 50213496Scognetstruct at91rm92_softc { 51213496Scognet device_t dev; 52213496Scognet bus_space_tag_t sc_st; 53213496Scognet bus_space_handle_t sc_sh; 54213496Scognet bus_space_handle_t sc_sys_sh; 55213496Scognet bus_space_handle_t sc_aic_sh; 56213496Scognet}; 57213496Scognet/* 58213496Scognet * Standard priority levels for the system. 0 is lowest and 7 is highest. 59213496Scognet * These values are the ones Atmel uses for its Linux port, which differ 60213496Scognet * a little form the ones that are in the standard distribution. Also, 61213496Scognet * the ones marked with 'TWEEK' are different based on experience. 62213496Scognet */ 63213496Scognetstatic const int at91_irq_prio[32] = 64213496Scognet{ 65213496Scognet 7, /* Advanced Interrupt Controller (FIQ) */ 66213496Scognet 7, /* System Peripherals */ 67213496Scognet 1, /* Parallel IO Controller A */ 68213496Scognet 1, /* Parallel IO Controller B */ 69213496Scognet 1, /* Parallel IO Controller C */ 70213496Scognet 1, /* Parallel IO Controller D */ 71213496Scognet 5, /* USART 0 */ 72213496Scognet 5, /* USART 1 */ 73213496Scognet 5, /* USART 2 */ 74213496Scognet 5, /* USART 3 */ 75213496Scognet 0, /* Multimedia Card Interface */ 76213496Scognet 2, /* USB Device Port */ 77213496Scognet 4, /* Two-Wire Interface */ /* TWEEK */ 78213496Scognet 5, /* Serial Peripheral Interface */ 79213496Scognet 4, /* Serial Synchronous Controller 0 */ 80213496Scognet 6, /* Serial Synchronous Controller 1 */ /* TWEEK */ 81213496Scognet 4, /* Serial Synchronous Controller 2 */ 82213496Scognet 0, /* Timer Counter 0 */ 83213496Scognet 6, /* Timer Counter 1 */ /* TWEEK */ 84213496Scognet 0, /* Timer Counter 2 */ 85213496Scognet 0, /* Timer Counter 3 */ 86213496Scognet 0, /* Timer Counter 4 */ 87213496Scognet 0, /* Timer Counter 5 */ 88213496Scognet 2, /* USB Host port */ 89213496Scognet 3, /* Ethernet MAC */ 90213496Scognet 0, /* Advanced Interrupt Controller (IRQ0) */ 91213496Scognet 0, /* Advanced Interrupt Controller (IRQ1) */ 92213496Scognet 0, /* Advanced Interrupt Controller (IRQ2) */ 93213496Scognet 0, /* Advanced Interrupt Controller (IRQ3) */ 94213496Scognet 0, /* Advanced Interrupt Controller (IRQ4) */ 95213496Scognet 0, /* Advanced Interrupt Controller (IRQ5) */ 96213496Scognet 0 /* Advanced Interrupt Controller (IRQ6) */ 97213496Scognet}; 98213496Scognet 99213496Scognet#define DEVICE(_name, _id, _unit) \ 100213496Scognet { \ 101213496Scognet _name, _unit, \ 102213496Scognet AT91RM92_ ## _id ##_BASE, \ 103213496Scognet AT91RM92_ ## _id ## _SIZE, \ 104213496Scognet AT91RM92_IRQ_ ## _id \ 105213496Scognet } 106213496Scognet 107213496Scognetstatic const struct cpu_devs at91_devs[] = 108213496Scognet{ 109213496Scognet DEVICE("at91_pmc", PMC, 0), 110213496Scognet DEVICE("at91_st", ST, 0), 111213496Scognet DEVICE("at91_pio", PIOA, 0), 112213496Scognet DEVICE("at91_pio", PIOB, 1), 113213496Scognet DEVICE("at91_pio", PIOC, 2), 114213496Scognet DEVICE("at91_pio", PIOD, 3), 115213496Scognet DEVICE("at91_rtc", RTC, 0), 116213496Scognet 117213496Scognet DEVICE("at91_mci", MCI, 0), 118213496Scognet DEVICE("at91_twi", TWI, 0), 119213496Scognet DEVICE("at91_udp", UDP, 0), 120213496Scognet DEVICE("ate", EMAC, 0), 121213496Scognet DEVICE("at91_ssc", SSC0, 0), 122213496Scognet DEVICE("at91_ssc", SSC1, 1), 123213496Scognet DEVICE("at91_ssc", SSC2, 2), 124213496Scognet DEVICE("spi", SPI, 0), 125213496Scognet 126213496Scognet DEVICE("uart", DBGU, 0), 127213496Scognet DEVICE("uart", USART0, 1), 128213496Scognet DEVICE("uart", USART1, 2), 129213496Scognet DEVICE("uart", USART2, 3), 130213496Scognet DEVICE("uart", USART3, 4), 131213496Scognet DEVICE("at91_aic", AIC, 0), 132213496Scognet DEVICE("at91_mc", MC, 0), 133213496Scognet DEVICE("at91_tc", TC0, 0), 134213496Scognet DEVICE("at91_tc", TC1, 1), 135213496Scognet DEVICE("ohci", OHCI, 0), 136213496Scognet DEVICE("af91_cfata", CF, 0), 137213496Scognet { 0, 0, 0, 0, 0 } 138213496Scognet}; 139213496Scognet 140213496Scognetstatic uint32_t 141213496Scognetat91_pll_outb(int freq) 142213496Scognet{ 143213496Scognet 144213496Scognet if (freq > 155000000) 145213496Scognet return (0x0000); 146236989Simp else 147213496Scognet return (0x8000); 148213496Scognet} 149213496Scognet 150213496Scognetstatic void 151213496Scognetat91_identify(driver_t *drv, device_t parent) 152213496Scognet{ 153213496Scognet 154238390Simp if (at91_cpu_is(AT91_T_RM9200)) 155213496Scognet at91_add_child(parent, 0, "at91rm920", 0, 0, 0, -1, 0, 0); 156213496Scognet} 157213496Scognet 158213496Scognetstatic int 159213496Scognetat91_probe(device_t dev) 160213496Scognet{ 161213496Scognet 162238376Simp device_set_desc(dev, soc_info.name); 163236658Simp return (0); 164213496Scognet} 165213496Scognet 166213496Scognetstatic int 167213496Scognetat91_attach(device_t dev) 168213496Scognet{ 169213496Scognet struct at91_pmc_clock *clk; 170213496Scognet struct at91rm92_softc *sc = device_get_softc(dev); 171213496Scognet struct at91_softc *at91sc = device_get_softc(device_get_parent(dev)); 172213496Scognet 173213496Scognet sc->sc_st = at91sc->sc_st; 174213496Scognet sc->sc_sh = at91sc->sc_sh; 175213496Scognet sc->dev = dev; 176213496Scognet 177213496Scognet if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_SYS_BASE, 178213496Scognet AT91RM92_SYS_SIZE, &sc->sc_sys_sh) != 0) 179213496Scognet panic("Enable to map system registers"); 180213496Scognet 181213496Scognet /* Disable all interrupts for RTC (0xe24 == RTC_IDR) */ 182213496Scognet bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xe24, 0xffffffff); 183213496Scognet 184213496Scognet /* Disable all interrupts for the SDRAM controller */ 185213496Scognet bus_space_write_4(sc->sc_st, sc->sc_sys_sh, 0xfa8, 0xffffffff); 186213496Scognet 187213496Scognet /* Update USB device port clock info */ 188213496Scognet clk = at91_pmc_clock_ref("udpck"); 189213496Scognet clk->pmc_mask = PMC_SCER_UDP; 190213496Scognet at91_pmc_clock_deref(clk); 191213496Scognet 192213496Scognet /* Update USB host port clock info */ 193213496Scognet clk = at91_pmc_clock_ref("uhpck"); 194213496Scognet clk->pmc_mask = PMC_SCER_UHP; 195213496Scognet at91_pmc_clock_deref(clk); 196213496Scognet 197213496Scognet /* Each SOC has different PLL contraints */ 198213496Scognet clk = at91_pmc_clock_ref("plla"); 199213496Scognet clk->pll_min_in = RM9200_PLL_A_MIN_IN_FREQ; /* 1 MHz */ 200213496Scognet clk->pll_max_in = RM9200_PLL_A_MAX_IN_FREQ; /* 32 MHz */ 201213496Scognet clk->pll_min_out = RM9200_PLL_A_MIN_OUT_FREQ; /* 80 MHz */ 202213496Scognet clk->pll_max_out = RM9200_PLL_A_MAX_OUT_FREQ; /* 180 MHz */ 203213496Scognet clk->pll_mul_shift = RM9200_PLL_A_MUL_SHIFT; 204213496Scognet clk->pll_mul_mask = RM9200_PLL_A_MUL_MASK; 205213496Scognet clk->pll_div_shift = RM9200_PLL_A_DIV_SHIFT; 206213496Scognet clk->pll_div_mask = RM9200_PLL_A_DIV_MASK; 207213496Scognet clk->set_outb = at91_pll_outb; 208213496Scognet at91_pmc_clock_deref(clk); 209213496Scognet 210213496Scognet clk = at91_pmc_clock_ref("pllb"); 211213496Scognet clk->pll_min_in = RM9200_PLL_B_MIN_IN_FREQ; /* 100 KHz */ 212213496Scognet clk->pll_max_in = RM9200_PLL_B_MAX_IN_FREQ; /* 32 MHz */ 213213496Scognet clk->pll_min_out = RM9200_PLL_B_MIN_OUT_FREQ; /* 30 MHz */ 214213496Scognet clk->pll_max_out = RM9200_PLL_B_MAX_OUT_FREQ; /* 240 MHz */ 215213496Scognet clk->pll_mul_shift = RM9200_PLL_B_MUL_SHIFT; 216213496Scognet clk->pll_mul_mask = RM9200_PLL_B_MUL_MASK; 217213496Scognet clk->pll_div_shift = RM9200_PLL_B_DIV_SHIFT; 218213496Scognet clk->pll_div_mask = RM9200_PLL_B_DIV_MASK; 219213496Scognet clk->set_outb = at91_pll_outb; 220213496Scognet at91_pmc_clock_deref(clk); 221213496Scognet 222213496Scognet return (0); 223213496Scognet} 224213496Scognet 225213496Scognetstatic device_method_t at91_methods[] = { 226213496Scognet DEVMETHOD(device_probe, at91_probe), 227213496Scognet DEVMETHOD(device_attach, at91_attach), 228213496Scognet DEVMETHOD(device_identify, at91_identify), 229213496Scognet {0, 0}, 230213496Scognet}; 231213496Scognet 232213496Scognetstatic driver_t at91rm92_driver = { 233213496Scognet "at91rm920", 234213496Scognet at91_methods, 235213496Scognet sizeof(struct at91rm92_softc), 236213496Scognet}; 237213496Scognet 238213496Scognetstatic devclass_t at91rm92_devclass; 239213496Scognet 240213496ScognetDRIVER_MODULE(at91rm920, atmelarm, at91rm92_driver, at91rm92_devclass, 0, 0); 241238376Simp 242238376Simpstatic struct at91_soc_data soc_data = { 243238376Simp .soc_delay = at91_st_delay, 244238389Simp .soc_reset = at91_st_cpu_reset, 245238389Simp .soc_irq_prio = at91_irq_prio, 246238390Simp .soc_children = at91_devs, 247238376Simp}; 248238376Simp 249238376SimpAT91_SOC(AT91_T_RM9200, &soc_data); 250