at91_rstreg.h revision 213496
1192991Srmacklem/*- 2192991Srmacklem * Copyright (c) 2009 Greg Ansley. All rights reserved. 3221032Srmacklem * 4192991Srmacklem * Redistribution and use in source and binary forms, with or without 5192991Srmacklem * modification, are permitted provided that the following conditions 6192991Srmacklem * are met: 7192991Srmacklem * 1. Redistributions of source code must retain the above copyright 8192991Srmacklem * notice, this list of conditions and the following disclaimer. 9192991Srmacklem * 2. Redistributions in binary form must reproduce the above copyright 10192991Srmacklem * notice, this list of conditions and the following disclaimer in the 11192991Srmacklem * documentation and/or other materials provided with the distribution. 12192991Srmacklem * 13192991Srmacklem * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14192991Srmacklem * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15192991Srmacklem * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16192991Srmacklem * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17223483Suqs * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18192991Srmacklem * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19192991Srmacklem * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20223483Suqs * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21223483Suqs * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22223483Suqs * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23192991Srmacklem * SUCH DAMAGE. 24223483Suqs */ 25192991Srmacklem 26221032Srmacklem/* $FreeBSD: head/sys/arm/at91/at91_rstreg.h 213496 2010-10-06 22:25:21Z cognet $ */ 27221032Srmacklem 28221032Srmacklem#ifndef ARM_AT91_AT91RSTREG_H 29221032Srmacklem#define ARM_AT91_AT91RSTREG_H 30221032Srmacklem 31221032Srmacklem#define RST_CR 0x0 /* Control Register */ 32221032Srmacklem#define RST_SR 0x4 /* Status Register */ 33221032Srmacklem#define RST_MR 0x8 /* Mode Register */ 34221032Srmacklem 35221032Srmacklem/* RST_CR */ 36221032Srmacklem#define RST_CR_PROCRST (1<<0) 37221032Srmacklem#define RST_CR_PERRST (1<<2) 38221032Srmacklem#define RST_CR_EXTRST (1<<3) 39221032Srmacklem#define RST_CR_KEY (0xa5<<24) 40221032Srmacklem 41221032Srmacklem/* RST_SR */ 42221032Srmacklem#define RST_SR_SRCMP (1<<17) /* Software Reset in progress */ 43221032Srmacklem#define RST_SR_NRSTL (1<<16) /* NRST pin level at MCK */ 44221032Srmacklem#define RST_SR_URSTS (1<<0) /* NRST pin has been active */ 45221032Srmacklem 46221032Srmacklem#define RST_SR_RST_POW (0<<8) /* General (Power On) reset */ 47221032Srmacklem#define RST_SR_RST_WAKE (1<<8) /* Wake-up reset */ 48221032Srmacklem#define RST_SR_RST_WDT (2<<8) /* Watchdog reset */ 49221032Srmacklem#define RST_SR_RST_SOFT (3<<8) /* Software reset */ 50221032Srmacklem#define RST_SR_RST_USR (4<<8) /* User (External) reset */ 51221032Srmacklem#define RST_SR_RST_MASK (7<<8) /* User (External) reset */ 52221032Srmacklem 53221032Srmacklem/* RST_MR */ 54221032Srmacklem#define RST_MR_URSTEN (1<<0) /* User reset enable */ 55221032Srmacklem#define RST_MR_URSIEN (1<<4) /* User interrupt enable */ 56221032Srmacklem#define RST_MR_ERSTL(x) ((x)<<8) /* External reset length */ 57221032Srmacklem#define RST_MR_KEY (0xa5<<24) 58192991Srmacklem 59#endif /* ARM_AT91_AT91RSTREG_H */ 60