1213496Scognet/*- 2213496Scognet * Copyright (c) 2009 Greg Ansley. All rights reserved. 3213496Scognet * 4213496Scognet * Redistribution and use in source and binary forms, with or without 5213496Scognet * modification, are permitted provided that the following conditions 6213496Scognet * are met: 7213496Scognet * 1. Redistributions of source code must retain the above copyright 8213496Scognet * notice, this list of conditions and the following disclaimer. 9213496Scognet * 2. Redistributions in binary form must reproduce the above copyright 10213496Scognet * notice, this list of conditions and the following disclaimer in the 11213496Scognet * documentation and/or other materials provided with the distribution. 12213496Scognet * 13213496Scognet * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14213496Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15213496Scognet * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16213496Scognet * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17213496Scognet * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18213496Scognet * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19213496Scognet * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20213496Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21213496Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22213496Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23213496Scognet * SUCH DAMAGE. 24213496Scognet */ 25213496Scognet 26213496Scognet/* $FreeBSD: releng/10.2/sys/arm/at91/at91_rstreg.h 238369 2012-07-11 17:11:07Z imp $ */ 27213496Scognet 28238369Simp#ifndef ARM_AT91_AT91_RSTREG_H 29238369Simp#define ARM_AT91_AT91_RSTREG_H 30213496Scognet 31213496Scognet#define RST_CR 0x0 /* Control Register */ 32213496Scognet#define RST_SR 0x4 /* Status Register */ 33213496Scognet#define RST_MR 0x8 /* Mode Register */ 34213496Scognet 35213496Scognet/* RST_CR */ 36213496Scognet#define RST_CR_PROCRST (1<<0) 37213496Scognet#define RST_CR_PERRST (1<<2) 38213496Scognet#define RST_CR_EXTRST (1<<3) 39213496Scognet#define RST_CR_KEY (0xa5<<24) 40213496Scognet 41213496Scognet/* RST_SR */ 42213496Scognet#define RST_SR_SRCMP (1<<17) /* Software Reset in progress */ 43213496Scognet#define RST_SR_NRSTL (1<<16) /* NRST pin level at MCK */ 44213496Scognet#define RST_SR_URSTS (1<<0) /* NRST pin has been active */ 45213496Scognet 46213496Scognet#define RST_SR_RST_POW (0<<8) /* General (Power On) reset */ 47213496Scognet#define RST_SR_RST_WAKE (1<<8) /* Wake-up reset */ 48213496Scognet#define RST_SR_RST_WDT (2<<8) /* Watchdog reset */ 49213496Scognet#define RST_SR_RST_SOFT (3<<8) /* Software reset */ 50213496Scognet#define RST_SR_RST_USR (4<<8) /* User (External) reset */ 51213496Scognet#define RST_SR_RST_MASK (7<<8) /* User (External) reset */ 52213496Scognet 53213496Scognet/* RST_MR */ 54213496Scognet#define RST_MR_URSTEN (1<<0) /* User reset enable */ 55213496Scognet#define RST_MR_URSIEN (1<<4) /* User interrupt enable */ 56213496Scognet#define RST_MR_ERSTL(x) ((x)<<8) /* External reset length */ 57213496Scognet#define RST_MR_KEY (0xa5<<24) 58213496Scognet 59238369Simp#ifndef __ASSEMBLER__ 60238369Simpvoid at91_rst_cpu_reset(void); 61238369Simp#endif 62238369Simp 63238369Simp#endif /* ARM_AT91_AT91_RSTREG_H */ 64