1#include <machine/asm.h> 2#include <arm/at91/at91_rstreg.h> 3#include <arm/at91/at91reg.h> 4#include <arm/at91/at91sam9g20reg.h> 5__FBSDID("$FreeBSD: releng/10.2/sys/arm/at91/at91_reset.S 238330 2012-07-10 02:14:50Z imp $"); 6 7#define SDRAM_TR (AT91_BASE + \ 8 AT91SAM9G20_SDRAMC_BASE + AT91SAM9G20_SDRAMC_TR) 9#define SDRAM_LPR (AT91_BASE + \ 10 AT91SAM9G20_SDRAMC_BASE + AT91SAM9G20_SDRAMC_LPR) 11#define RSTC_RCR (AT91_BASE + \ 12 AT91SAM9G20_RSTC_BASE + RST_CR) 13 14/* 15 * From AT91SAM9G20 Datasheet errata 44:3.5: 16 * 17 * When User Reset occurs durring SDRAM read acces, eh SDRAM clock is turned 18 * off while data are ready to be read on the data bus. The SDRAM maintains 19 * the data until the clock restarts. 20 * 21 * If the User reset is programed to assert a general reset, the data 22 * maintained by the SDRAM leads to a data bus conflict and adversly affects 23 * the boot memories connected to the EBI: 24 * + NAND Flash boot functionality, if the system boots out of internal ROM. 25 * + NOR Flash boot, if the system boots on an external memory connected to 26 * the EBI CS0. 27 * 28 * Assembly code is mandatory for the following sequnce as ARM 29 * instructions need to be piplined. 30 * 31 */ 32 33ENTRY(cpu_reset_sam9g20) 34 35 /* Disable IRQs */ 36 mrs r0, cpsr 37 orr r0, r0, #0x80 38 msr cpsr_c, r0 39 40 /* Change Refresh to block all data access */ 41 ldr r0, =SDRAM_TR 42 ldr r1, =1 43 str r1, [r0] 44 45 /* Prepare power down command */ 46 ldr r0, =SDRAM_LPR 47 ldr r1, =2 48 49 /* Prepare proc_reset and periph reset */ 50 ldr r2, =RSTC_RCR 51 ldr r3, =0xA5000005 52 53 /* perform power down command */ 54 str r1, [r0] 55 56 /* Perfom proc_reset and periph reset (in the ARM pipeline) */ 57 str r3, [r2] 58