vmcb.h revision 271939
1/*- 2 * Copyright (c) 2013 Anish Gupta (akgupt3@gmail.com) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: projects/bhyve_svm/sys/amd64/vmm/amd/vmcb.h 271939 2014-09-21 23:42:54Z neel $ 27 */ 28 29#ifndef _VMCB_H_ 30#define _VMCB_H_ 31 32struct svm_softc; 33 34/* 35 * Secure Virtual Machine: AMD64 Programmer's Manual Vol2, Chapter 15 36 * Layout of VMCB: AMD64 Programmer's Manual Vol2, Appendix B 37 */ 38 39/* vmcb_ctrl->intercept[] array indices */ 40#define VMCB_CR_INTCPT 0 41#define VMCB_DR_INTCPT 1 42#define VMCB_EXC_INTCPT 2 43#define VMCB_CTRL1_INTCPT 3 44#define VMCB_CTRL2_INTCPT 4 45 46/* intercept[VMCB_CTRL1_INTCPT] fields */ 47#define VMCB_INTCPT_INTR BIT(0) 48#define VMCB_INTCPT_NMI BIT(1) 49#define VMCB_INTCPT_SMI BIT(2) 50#define VMCB_INTCPT_INIT BIT(3) 51#define VMCB_INTCPT_VINTR BIT(4) 52#define VMCB_INTCPT_CR0_WRITE BIT(5) 53#define VMCB_INTCPT_IDTR_READ BIT(6) 54#define VMCB_INTCPT_GDTR_READ BIT(7) 55#define VMCB_INTCPT_LDTR_READ BIT(8) 56#define VMCB_INTCPT_TR_READ BIT(9) 57#define VMCB_INTCPT_IDTR_WRITE BIT(10) 58#define VMCB_INTCPT_GDTR_WRITE BIT(11) 59#define VMCB_INTCPT_LDTR_WRITE BIT(12) 60#define VMCB_INTCPT_TR_WRITE BIT(13) 61#define VMCB_INTCPT_RDTSC BIT(14) 62#define VMCB_INTCPT_RDPMC BIT(15) 63#define VMCB_INTCPT_PUSHF BIT(16) 64#define VMCB_INTCPT_POPF BIT(17) 65#define VMCB_INTCPT_CPUID BIT(18) 66#define VMCB_INTCPT_RSM BIT(19) 67#define VMCB_INTCPT_IRET BIT(20) 68#define VMCB_INTCPT_INTn BIT(21) 69#define VMCB_INTCPT_INVD BIT(22) 70#define VMCB_INTCPT_PAUSE BIT(23) 71#define VMCB_INTCPT_HLT BIT(24) 72#define VMCB_INTCPT_INVPG BIT(25) 73#define VMCB_INTCPT_INVPGA BIT(26) 74#define VMCB_INTCPT_IO BIT(27) 75#define VMCB_INTCPT_MSR BIT(28) 76#define VMCB_INTCPT_TASK_SWITCH BIT(29) 77#define VMCB_INTCPT_FERR_FREEZE BIT(30) 78#define VMCB_INTCPT_SHUTDOWN BIT(31) 79 80/* intercept[VMCB_CTRL2_INTCPT] fields */ 81#define VMCB_INTCPT_VMRUN BIT(0) 82#define VMCB_INTCPT_VMMCALL BIT(1) 83#define VMCB_INTCPT_VMLOAD BIT(2) 84#define VMCB_INTCPT_VMSAVE BIT(3) 85#define VMCB_INTCPT_STGI BIT(4) 86#define VMCB_INTCPT_CLGI BIT(5) 87#define VMCB_INTCPT_SKINIT BIT(6) 88#define VMCB_INTCPT_RDTSCP BIT(7) 89#define VMCB_INTCPT_ICEBP BIT(8) 90#define VMCB_INTCPT_WBINVD BIT(9) 91#define VMCB_INTCPT_MONITOR BIT(10) 92#define VMCB_INTCPT_MWAIT BIT(11) 93#define VMCB_INTCPT_MWAIT_ARMED BIT(12) 94#define VMCB_INTCPT_XSETBV BIT(13) 95 96/* VMCB TLB control */ 97#define VMCB_TLB_FLUSH_NOTHING 0 /* Flush nothing */ 98#define VMCB_TLB_FLUSH_ALL 1 /* Flush entire TLB */ 99#define VMCB_TLB_FLUSH_GUEST 3 /* Flush all guest entries */ 100#define VMCB_TLB_FLUSH_GUEST_NONGLOBAL 7 /* Flush guest non-PG entries */ 101 102/* VMCB state caching */ 103#define VMCB_CACHE_NONE 0 /* No caching */ 104#define VMCB_CACHE_I BIT(0) /* Intercept, TSC off, Pause filter */ 105#define VMCB_CACHE_IOPM BIT(1) /* I/O and MSR permission */ 106#define VMCB_CACHE_ASID BIT(2) /* ASID */ 107#define VMCB_CACHE_TPR BIT(3) /* V_TPR to V_INTR_VECTOR */ 108#define VMCB_CACHE_NP BIT(4) /* Nested Paging */ 109#define VMCB_CACHE_CR BIT(5) /* CR0, CR3, CR4 & EFER */ 110#define VMCB_CACHE_DR BIT(6) /* Debug registers */ 111#define VMCB_CACHE_DT BIT(7) /* GDT/IDT */ 112#define VMCB_CACHE_SEG BIT(8) /* User segments, CPL */ 113#define VMCB_CACHE_CR2 BIT(9) /* page fault address */ 114#define VMCB_CACHE_LBR BIT(10) /* Last branch */ 115 116/* VMCB control event injection */ 117#define VMCB_EVENTINJ_EC_VALID BIT(11) /* Error Code valid */ 118#define VMCB_EVENTINJ_VALID BIT(31) /* Event valid */ 119 120/* Event types that can be injected */ 121#define VMCB_EVENTINJ_TYPE_INTR 0 122#define VMCB_EVENTINJ_TYPE_NMI 2 123#define VMCB_EVENTINJ_TYPE_EXCEPTION 3 124#define VMCB_EVENTINJ_TYPE_INTn 4 125 126/* VMCB exit code, APM vol2 Appendix C */ 127#define VMCB_EXIT_MC 0x52 128#define VMCB_EXIT_INTR 0x60 129#define VMCB_EXIT_NMI 0x61 130#define VMCB_EXIT_VINTR 0x64 131#define VMCB_EXIT_PUSHF 0x70 132#define VMCB_EXIT_POPF 0x71 133#define VMCB_EXIT_CPUID 0x72 134#define VMCB_EXIT_IRET 0x74 135#define VMCB_EXIT_PAUSE 0x77 136#define VMCB_EXIT_HLT 0x78 137#define VMCB_EXIT_IO 0x7B 138#define VMCB_EXIT_MSR 0x7C 139#define VMCB_EXIT_SHUTDOWN 0x7F 140#define VMCB_EXIT_VMSAVE 0x83 141#define VMCB_EXIT_NPF 0x400 142#define VMCB_EXIT_INVALID -1 143 144/* 145 * Nested page fault. 146 * Bit definitions to decode EXITINFO1. 147 */ 148#define VMCB_NPF_INFO1_P BIT(0) /* Nested page present. */ 149#define VMCB_NPF_INFO1_W BIT(1) /* Access was write. */ 150#define VMCB_NPF_INFO1_U BIT(2) /* Access was user access. */ 151#define VMCB_NPF_INFO1_RSV BIT(3) /* Reserved bits present. */ 152#define VMCB_NPF_INFO1_ID BIT(4) /* Code read. */ 153 154#define VMCB_NPF_INFO1_GPA BIT(32) /* Guest physical address. */ 155#define VMCB_NPF_INFO1_GPT BIT(33) /* Guest page table. */ 156 157/* 158 * EXITINTINFO, Interrupt exit info for all intrecepts. 159 * Section 15.7.2, Intercepts during IDT Interrupt Delivery. 160 */ 161#define VMCB_EXITINTINFO_VECTOR(x) ((x) & 0xFF) 162#define VMCB_EXITINTINFO_TYPE(x) (((x) >> 8) & 0x7) 163#define VMCB_EXITINTINFO_EC_VALID(x) (((x) & BIT(11)) ? 1 : 0) 164#define VMCB_EXITINTINFO_VALID(x) (((x) & BIT(31)) ? 1 : 0) 165#define VMCB_EXITINTINFO_EC(x) (((x) >> 32) & 0xFFFFFFFF) 166 167/* VMCB save state area segment format */ 168struct vmcb_segment { 169 uint16_t selector; 170 uint16_t attrib; 171 uint32_t limit; 172 uint64_t base; 173} __attribute__ ((__packed__)); 174CTASSERT(sizeof(struct vmcb_segment) == 16); 175 176/* Code segment descriptor attribute in 12 bit format as saved by VMCB. */ 177#define VMCB_CS_ATTRIB_L BIT(9) /* Long mode. */ 178#define VMCB_CS_ATTRIB_D BIT(10) /* OPerand size bit. */ 179 180/* 181 * The VMCB is divided into two areas - the first one contains various 182 * control bits including the intercept vector and the second one contains 183 * the guest state. 184 */ 185 186/* VMCB control area - padded up to 1024 bytes */ 187struct vmcb_ctrl { 188 uint32_t intercept[5]; /* all intercepts */ 189 uint8_t pad1[0x28]; /* Offsets 0x14-0x3B are reserved. */ 190 uint16_t pause_filthresh; /* Offset 0x3C, PAUSE filter threshold */ 191 uint16_t pause_filcnt; /* Offset 0x3E, PAUSE filter count */ 192 uint64_t iopm_base_pa; /* 0x40: IOPM_BASE_PA */ 193 uint64_t msrpm_base_pa; /* 0x48: MSRPM_BASE_PA */ 194 uint64_t tsc_offset; /* 0x50: TSC_OFFSET */ 195 uint32_t asid; /* 0x58: Guest ASID */ 196 uint8_t tlb_ctrl; /* 0x5C: TLB_CONTROL */ 197 uint8_t pad2[3]; /* 0x5D-0x5F: Reserved. */ 198 uint8_t v_tpr; /* 0x60: V_TPR, guest CR8 */ 199 uint8_t v_irq:1; /* Is virtual interrupt pending? */ 200 uint8_t :7; /* Padding */ 201 uint8_t v_intr_prio:4; /* 0x62: Priority for virtual interrupt. */ 202 uint8_t v_ign_tpr:1; 203 uint8_t :3; 204 uint8_t v_intr_masking:1; /* Guest and host sharing of RFLAGS. */ 205 uint8_t :7; 206 uint8_t v_intr_vector; /* 0x65: Vector for virtual interrupt. */ 207 uint8_t pad3[3]; /* Bit64-40 Reserved. */ 208 uint64_t intr_shadow:1; /* 0x68: Interrupt shadow, section15.2.1 APM2 */ 209 uint64_t :63; 210 uint64_t exitcode; /* 0x70, Exitcode */ 211 uint64_t exitinfo1; /* 0x78, EXITINFO1 */ 212 uint64_t exitinfo2; /* 0x80, EXITINFO2 */ 213 uint64_t exitintinfo; /* 0x88, Interrupt exit value. */ 214 uint64_t np_enable:1; /* 0x90, Nested paging enable. */ 215 uint64_t :63; 216 uint8_t pad4[0x10]; /* 0x98-0xA7 reserved. */ 217 uint64_t eventinj; /* 0xA8, Event injection. */ 218 uint64_t n_cr3; /* B0, Nested page table. */ 219 uint64_t lbr_virt_en:1; /* Enable LBR virtualization. */ 220 uint64_t :63; 221 uint32_t vmcb_clean; /* 0xC0: VMCB clean bits for caching */ 222 uint32_t :32; /* 0xC4: Reserved */ 223 uint64_t nrip; /* 0xC8: Guest next nRIP. */ 224 uint8_t inst_len; /* 0xD0: #NPF decode assist */ 225 uint8_t inst_bytes[15]; 226 uint8_t padd6[0x320]; 227} __attribute__ ((__packed__)); 228CTASSERT(sizeof(struct vmcb_ctrl) == 1024); 229 230struct vmcb_state { 231 struct vmcb_segment es; 232 struct vmcb_segment cs; 233 struct vmcb_segment ss; 234 struct vmcb_segment ds; 235 struct vmcb_segment fs; 236 struct vmcb_segment gs; 237 struct vmcb_segment gdt; 238 struct vmcb_segment ldt; 239 struct vmcb_segment idt; 240 struct vmcb_segment tr; 241 uint8_t pad1[0x2b]; /* Reserved: 0xA0-0xCA */ 242 uint8_t cpl; 243 uint8_t pad2[4]; 244 uint64_t efer; 245 uint8_t pad3[0x70]; /* Reserved: 0xd8-0x147 */ 246 uint64_t cr4; 247 uint64_t cr3; /* Guest CR3 */ 248 uint64_t cr0; 249 uint64_t dr7; 250 uint64_t dr6; 251 uint64_t rflags; 252 uint64_t rip; 253 uint8_t pad4[0x58]; /* Reserved: 0x180-0x1D7 */ 254 uint64_t rsp; 255 uint8_t pad5[0x18]; /* Reserved 0x1E0-0x1F7 */ 256 uint64_t rax; 257 uint64_t star; 258 uint64_t lstar; 259 uint64_t cstar; 260 uint64_t sfmask; 261 uint64_t kernelgsbase; 262 uint64_t sysenter_cs; 263 uint64_t sysenter_esp; 264 uint64_t sysenter_eip; 265 uint64_t cr2; 266 uint8_t pad6[0x20]; 267 uint64_t g_pat; 268 uint64_t dbgctl; 269 uint64_t br_from; 270 uint64_t br_to; 271 uint64_t int_from; 272 uint64_t int_to; 273 uint8_t pad7[0x968]; /* Reserved upto end of VMCB */ 274} __attribute__ ((__packed__)); 275CTASSERT(sizeof(struct vmcb_state) == 0xC00); 276 277struct vmcb { 278 struct vmcb_ctrl ctrl; 279 struct vmcb_state state; 280} __attribute__ ((__packed__)); 281CTASSERT(sizeof(struct vmcb) == PAGE_SIZE); 282CTASSERT(offsetof(struct vmcb, state) == 0x400); 283 284int vmcb_read(struct svm_softc *sc, int vcpu, int ident, uint64_t *retval); 285int vmcb_write(struct svm_softc *sc, int vcpu, int ident, uint64_t val); 286int vmcb_setdesc(void *arg, int vcpu, int ident, struct seg_desc *desc); 287int vmcb_getdesc(void *arg, int vcpu, int ident, struct seg_desc *desc); 288int vmcb_seg(struct vmcb *vmcb, int ident, struct vmcb_segment *seg); 289 290#endif /* _VMCB_H_ */ 291