intr_machdep.h revision 153241
1238730Sdelphij/*-
2238730Sdelphij * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3238730Sdelphij * All rights reserved.
4238730Sdelphij *
5238730Sdelphij * Redistribution and use in source and binary forms, with or without
6238730Sdelphij * modification, are permitted provided that the following conditions
7238730Sdelphij * are met:
8238730Sdelphij * 1. Redistributions of source code must retain the above copyright
960786Sps *    notice, this list of conditions and the following disclaimer.
1060786Sps * 2. Redistributions in binary form must reproduce the above copyright
1160786Sps *    notice, this list of conditions and the following disclaimer in the
1260786Sps *    documentation and/or other materials provided with the distribution.
1360786Sps *
1460786Sps * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
1560786Sps * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1660786Sps * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1760786Sps * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
1860786Sps * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
1960786Sps * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
2060786Sps * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
2160786Sps * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
2260786Sps * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
2360786Sps * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
2460786Sps * SUCH DAMAGE.
2560786Sps *
2660786Sps * $FreeBSD: head/sys/amd64/include/intr_machdep.h 153241 2005-12-08 18:33:30Z jhb $
2760786Sps */
2860786Sps
2960786Sps#ifndef __MACHINE_INTR_MACHDEP_H__
3060786Sps#define	__MACHINE_INTR_MACHDEP_H__
3160786Sps
3260786Sps#ifdef _KERNEL
3360786Sps
3460786Sps/*
3560786Sps * The maximum number of I/O interrupts we allow.  This number is rather
3660786Sps * arbitrary as it is just the maximum IRQ resource value.  The interrupt
37128345Stjr * source for a given IRQ maps that I/O interrupt to device interrupt
3860786Sps * source whether it be a pin on an interrupt controller or an MSI interrupt.
3960786Sps * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device
4060786Sps * interrupts allocate IDT vectors on demand.  Currently we have 191 IDT
4160786Sps * vectors available for device interrupts.  On many systems with I/O APICs,
42170256Sdelphij * a lot of the IRQs are not used, so this number can be much larger than
43195941Sdelphij * 191 and still be safe since only interrupt sources in actual use will
4460786Sps * allocate IDT vectors.
4560786Sps *
4689019Sps * For now we stick with 255 as ISA IRQs and PCI intline IRQs only allow
4760786Sps * for IRQs in the range 0 - 254.  When MSI support is added this number
4860786Sps * will likely increase.
4963128Sps */
5063128Sps#define	NUM_IO_INTS	255
51128345Stjr
52161475Sdelphij/*
53173682Sdelphij * - 1 ??? dummy counter.
54173682Sdelphij * - 2 counters for each I/O interrupt.
55250592Sdelphij * - 1 counter for each CPU for lapic timer.
5660786Sps * - 7 counters for each CPU for IPI counters for SMP.
5760786Sps */
5860786Sps#ifdef SMP
5960786Sps#define	INTRCNT_COUNT	(1 + NUM_IO_INTS * 2 + 1)
60161475Sdelphij#else
61161475Sdelphij#define	INTRCNT_COUNT	(1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU)
6260786Sps#endif
6360786Sps
6460786Sps#ifndef LOCORE
6560786Sps
6660786Spstypedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
6760786Sps
6860786Sps#define	IDTVEC(name)	__CONCAT(X,name)
6960786Sps
7060786Spsstruct intsrc;
7160786Sps
7260786Sps/*
7360786Sps * Methods that a PIC provides to mask/unmask a given interrupt source,
7460786Sps * "turn on" the interrupt on the CPU side by setting up an IDT entry, and
7560786Sps * return the vector associated with this source.
7660786Sps */
7760786Spsstruct pic {
7860786Sps	void (*pic_enable_source)(struct intsrc *);
7960786Sps	void (*pic_disable_source)(struct intsrc *, int);
8060786Sps	void (*pic_eoi_source)(struct intsrc *);
8160786Sps	void (*pic_enable_intr)(struct intsrc *);
8263128Sps	int (*pic_vector)(struct intsrc *);
8360786Sps	int (*pic_source_pending)(struct intsrc *);
8460786Sps	void (*pic_suspend)(struct intsrc *);
8560786Sps	void (*pic_resume)(struct intsrc *);
86161475Sdelphij	int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
87128345Stjr	    enum intr_polarity);
8860786Sps};
8960786Sps
9060786Sps/* Flags for pic_disable_source() */
9160786Spsenum {
9260786Sps	PIC_EOI,
9360786Sps	PIC_NO_EOI,
9460786Sps};
9560786Sps
9660786Sps/*
9760786Sps * An interrupt source.  The upper-layer code uses the PIC methods to
9860786Sps * control a given source.  The lower-layer PIC drivers can store additional
9960786Sps * private data in a given interrupt source such as an interrupt pin number
10060786Sps * or an I/O APIC pointer.
10160786Sps */
10260786Spsstruct intsrc {
10360786Sps	struct pic *is_pic;
10460786Sps	struct intr_event *is_event;
10560786Sps	u_long *is_count;
10660786Sps	u_long *is_straycount;
10760786Sps	u_int is_index;
10860786Sps};
10960786Sps
11060786Spsstruct trapframe;
11160786Sps
11260786Spsextern struct mtx icu_lock;
11360786Spsextern int elcr_found;
11460786Sps
11563128Sps/* XXX: The elcr_* prototypes probably belong somewhere else. */
11689019Spsint	elcr_probe(void);
117170256Sdelphijenum intr_trigger elcr_read_trigger(u_int irq);
118173682Sdelphijvoid	elcr_resume(void);
119250592Sdelphijvoid	elcr_write_trigger(u_int irq, enum intr_trigger trigger);
12060786Spsint	intr_add_handler(const char *name, int vector, driver_intr_t handler,
12160786Sps    void *arg, enum intr_type flags, void **cookiep);
12260786Spsint	intr_config_intr(int vector, enum intr_trigger trig,
12360786Sps    enum intr_polarity pol);
12489019Spsvoid	intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
12589019Spsstruct intsrc *intr_lookup_source(int vector);
12689019Spsint	intr_register_source(struct intsrc *isrc);
12789019Spsint	intr_remove_handler(void *cookie);
12889019Spsvoid	intr_resume(void);
12989019Spsvoid	intr_suspend(void);
13089019Spsvoid	intrcnt_add(const char *name, u_long **countp);
13189019Sps
13289019Sps#endif	/* !LOCORE */
13360786Sps#endif	/* _KERNEL */
134128345Stjr#endif	/* !__MACHINE_INTR_MACHDEP_H__ */
13560786Sps