fenv.h revision 176530
1/*- 2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: head/lib/msun/powerpc/fenv.h 176530 2008-02-24 19:22:53Z raj $ 27 */ 28 29#ifndef _FENV_H_ 30#define _FENV_H_ 31 32#include <sys/_types.h> 33 34typedef __uint32_t fenv_t; 35typedef __uint32_t fexcept_t; 36 37/* Exception flags */ 38#define FE_INEXACT 0x02000000 39#define FE_DIVBYZERO 0x04000000 40#define FE_UNDERFLOW 0x08000000 41#define FE_OVERFLOW 0x10000000 42#define FE_INVALID 0x20000000 /* all types of invalid FP ops */ 43 44/* 45 * The PowerPC architecture has extra invalid flags that indicate the 46 * specific type of invalid operation occurred. These flags may be 47 * tested, set, and cleared---but not masked---separately. All of 48 * these bits are cleared when FE_INVALID is cleared, but only 49 * FE_VXSOFT is set when FE_INVALID is explicitly set in software. 50 */ 51#define FE_VXCVI 0x00000100 /* invalid integer convert */ 52#define FE_VXSQRT 0x00000200 /* square root of a negative */ 53#define FE_VXSOFT 0x00000400 /* software-requested exception */ 54#define FE_VXVC 0x00080000 /* ordered comparison involving NaN */ 55#define FE_VXIMZ 0x00100000 /* inf * 0 */ 56#define FE_VXZDZ 0x00200000 /* 0 / 0 */ 57#define FE_VXIDI 0x00400000 /* inf / inf */ 58#define FE_VXISI 0x00800000 /* inf - inf */ 59#define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ 60#define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ 61 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ 62 FE_VXSNAN | FE_INVALID) 63#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 64 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 65 66/* Rounding modes */ 67#define FE_TONEAREST 0x0000 68#define FE_TOWARDZERO 0x0001 69#define FE_UPWARD 0x0002 70#define FE_DOWNWARD 0x0003 71#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 72 FE_UPWARD | FE_TOWARDZERO) 73 74__BEGIN_DECLS 75 76/* Default floating-point environment */ 77extern const fenv_t __fe_dfl_env; 78#define FE_DFL_ENV (&__fe_dfl_env) 79 80/* We need to be able to map status flag positions to mask flag positions */ 81#define _FPUSW_SHIFT 22 82#define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ 83 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) 84 85#ifndef _SOFT_FLOAT 86#define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env))) 87#define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env)) 88#else 89#define __mffs(__env) 90#define __mtfsf(__env) 91#endif 92 93union __fpscr { 94 double __d; 95 struct { 96 __uint32_t __junk; 97 fenv_t __reg; 98 } __bits; 99}; 100 101static __inline int 102feclearexcept(int __excepts) 103{ 104 union __fpscr __r; 105 106 if (__excepts & FE_INVALID) 107 __excepts |= FE_ALL_INVALID; 108 __mffs(&__r.__d); 109 __r.__bits.__reg &= ~__excepts; 110 __mtfsf(__r.__d); 111 return (0); 112} 113 114static __inline int 115fegetexceptflag(fexcept_t *__flagp, int __excepts) 116{ 117 union __fpscr __r; 118 119 __mffs(&__r.__d); 120 *__flagp = __r.__bits.__reg & __excepts; 121 return (0); 122} 123 124static __inline int 125fesetexceptflag(const fexcept_t *__flagp, int __excepts) 126{ 127 union __fpscr __r; 128 129 if (__excepts & FE_INVALID) 130 __excepts |= FE_ALL_EXCEPT; 131 __mffs(&__r.__d); 132 __r.__bits.__reg &= ~__excepts; 133 __r.__bits.__reg |= *__flagp & __excepts; 134 __mtfsf(__r.__d); 135 return (0); 136} 137 138static __inline int 139feraiseexcept(int __excepts) 140{ 141 union __fpscr __r; 142 143 if (__excepts & FE_INVALID) 144 __excepts |= FE_VXSOFT; 145 __mffs(&__r.__d); 146 __r.__bits.__reg |= __excepts; 147 __mtfsf(__r.__d); 148 return (0); 149} 150 151static __inline int 152fetestexcept(int __excepts) 153{ 154 union __fpscr __r; 155 156 __mffs(&__r.__d); 157 return (__r.__bits.__reg & __excepts); 158} 159 160static __inline int 161fegetround(void) 162{ 163 union __fpscr __r; 164 165 __mffs(&__r.__d); 166 return (__r.__bits.__reg & _ROUND_MASK); 167} 168 169static __inline int 170fesetround(int __round) 171{ 172 union __fpscr __r; 173 174 if (__round & ~_ROUND_MASK) 175 return (-1); 176 __mffs(&__r.__d); 177 __r.__bits.__reg &= ~_ROUND_MASK; 178 __r.__bits.__reg |= __round; 179 __mtfsf(__r.__d); 180 return (0); 181} 182 183static __inline int 184fegetenv(fenv_t *__envp) 185{ 186 union __fpscr __r; 187 188 __mffs(&__r.__d); 189 *__envp = __r.__bits.__reg; 190 return (0); 191} 192 193static __inline int 194feholdexcept(fenv_t *__envp) 195{ 196 union __fpscr __r; 197 198 __mffs(&__r.__d); 199 *__envp = __r.__d; 200 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); 201 __mtfsf(__r.__d); 202 return (0); 203} 204 205static __inline int 206fesetenv(const fenv_t *__envp) 207{ 208 union __fpscr __r; 209 210 __r.__bits.__reg = *__envp; 211 __mtfsf(__r.__d); 212 return (0); 213} 214 215static __inline int 216feupdateenv(const fenv_t *__envp) 217{ 218 union __fpscr __r; 219 220 __mffs(&__r.__d); 221 __r.__bits.__reg &= FE_ALL_EXCEPT; 222 __r.__bits.__reg |= *__envp; 223 __mtfsf(__r.__d); 224 return (0); 225} 226 227#if __BSD_VISIBLE 228 229static __inline int 230feenableexcept(int __mask) 231{ 232 union __fpscr __r; 233 fenv_t __oldmask; 234 235 __mffs(&__r.__d); 236 __oldmask = __r.__bits.__reg; 237 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; 238 __mtfsf(__r.__d); 239 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 240} 241 242static __inline int 243fedisableexcept(int __mask) 244{ 245 union __fpscr __r; 246 fenv_t __oldmask; 247 248 __mffs(&__r.__d); 249 __oldmask = __r.__bits.__reg; 250 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); 251 __mtfsf(__r.__d); 252 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 253} 254 255static __inline int 256fegetexcept(void) 257{ 258 union __fpscr __r; 259 260 __mffs(&__r.__d); 261 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); 262} 263 264#endif /* __BSD_VISIBLE */ 265 266__END_DECLS 267 268#endif /* !_FENV_H_ */ 269