fenv.h revision 130146
1130146Sdas/*- 2130146Sdas * Copyright (c) 2004 David Schultz <das@FreeBSD.ORG> 3130146Sdas * All rights reserved. 4130146Sdas * 5130146Sdas * Redistribution and use in source and binary forms, with or without 6130146Sdas * modification, are permitted provided that the following conditions 7130146Sdas * are met: 8130146Sdas * 1. Redistributions of source code must retain the above copyright 9130146Sdas * notice, this list of conditions and the following disclaimer. 10130146Sdas * 2. Redistributions in binary form must reproduce the above copyright 11130146Sdas * notice, this list of conditions and the following disclaimer in the 12130146Sdas * documentation and/or other materials provided with the distribution. 13130146Sdas * 14130146Sdas * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15130146Sdas * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16130146Sdas * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17130146Sdas * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18130146Sdas * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19130146Sdas * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20130146Sdas * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21130146Sdas * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22130146Sdas * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23130146Sdas * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24130146Sdas * SUCH DAMAGE. 25130146Sdas * 26130146Sdas * $FreeBSD: head/lib/msun/powerpc/fenv.h 130146 2004-06-06 10:05:10Z das $ 27130146Sdas */ 28130146Sdas 29130146Sdas#ifndef _FENV_H_ 30130146Sdas#define _FENV_H_ 31130146Sdas 32130146Sdas#include <sys/_types.h> 33130146Sdas 34130146Sdastypedef __uint32_t fenv_t; 35130146Sdastypedef __uint32_t fexcept_t; 36130146Sdas 37130146Sdas/* Exception flags */ 38130146Sdas#define FE_INEXACT 0x02000000 39130146Sdas#define FE_DIVBYZERO 0x04000000 40130146Sdas#define FE_UNDERFLOW 0x08000000 41130146Sdas#define FE_OVERFLOW 0x10000000 42130146Sdas#define FE_INVALID 0x20000000 /* all types of invalid FP ops */ 43130146Sdas 44130146Sdas/* 45130146Sdas * The PowerPC architecture has extra invalid flags that indicate the 46130146Sdas * specific type of invalid operation occurred. These flags may be 47130146Sdas * tested, set, and cleared---but not masked---separately. All of 48130146Sdas * these bits are cleared when FE_INVALID is cleared, but only 49130146Sdas * FE_VXSOFT is set when FE_INVALID is explicitly set in software. 50130146Sdas */ 51130146Sdas#define FE_VXCVI 0x00000100 /* invalid integer convert */ 52130146Sdas#define FE_VXSQRT 0x00000200 /* square root of a negative */ 53130146Sdas#define FE_VXSOFT 0x00000400 /* software-requested exception */ 54130146Sdas#define FE_VXVC 0x00080000 /* ordered comparison involving NaN */ 55130146Sdas#define FE_VXIMZ 0x00100000 /* inf * 0 */ 56130146Sdas#define FE_VXZDZ 0x00200000 /* 0 / 0 */ 57130146Sdas#define FE_VXIDI 0x00400000 /* inf / inf */ 58130146Sdas#define FE_VXISI 0x00800000 /* inf - inf */ 59130146Sdas#define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ 60130146Sdas#define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ 61130146Sdas FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ 62130146Sdas FE_VXSNAN | FE_INVALID) 63130146Sdas#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 64130146Sdas FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 65130146Sdas 66130146Sdas/* Rounding modes */ 67130146Sdas#define FE_TONEAREST 0x0000 68130146Sdas#define FE_TOWARDZERO 0x0001 69130146Sdas#define FE_UPWARD 0x0002 70130146Sdas#define FE_DOWNWARD 0x0003 71130146Sdas#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 72130146Sdas FE_UPWARD | FE_TOWARDZERO) 73130146Sdas 74130146Sdas__BEGIN_DECLS 75130146Sdas 76130146Sdas/* Default floating-point environment */ 77130146Sdasextern const fenv_t __fe_dfl_env; 78130146Sdas#define FE_DFL_ENV (&__fe_dfl_env) 79130146Sdas 80130146Sdas/* We need to be able to map status flag positions to mask flag positions */ 81130146Sdas#define _FPUSW_SHIFT 22 82130146Sdas#define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ 83130146Sdas FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) 84130146Sdas 85130146Sdas#define __mffs(__env) __asm("mffs %0" : "=f" (*(__env))) 86130146Sdas#define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env)) 87130146Sdas 88130146Sdasunion __fpscr { 89130146Sdas double __d; 90130146Sdas struct { 91130146Sdas __uint32_t __junk; 92130146Sdas fenv_t __reg; 93130146Sdas } __bits; 94130146Sdas}; 95130146Sdas 96130146Sdasstatic __inline int 97130146Sdasfeclearexcept(int __excepts) 98130146Sdas{ 99130146Sdas union __fpscr __r; 100130146Sdas 101130146Sdas if (__excepts & FE_INVALID) 102130146Sdas __excepts |= FE_ALL_INVALID; 103130146Sdas __mffs(&__r.__d); 104130146Sdas __r.__bits.__reg &= ~__excepts; 105130146Sdas __mtfsf(__r.__d); 106130146Sdas return (0); 107130146Sdas} 108130146Sdas 109130146Sdasstatic __inline int 110130146Sdasfegetexceptflag(fexcept_t *__flagp, int __excepts) 111130146Sdas{ 112130146Sdas union __fpscr __r; 113130146Sdas 114130146Sdas __mffs(&__r.__d); 115130146Sdas *__flagp = __r.__bits.__reg & __excepts; 116130146Sdas return (0); 117130146Sdas} 118130146Sdas 119130146Sdasstatic __inline int 120130146Sdasfesetexceptflag(const fexcept_t *__flagp, int __excepts) 121130146Sdas{ 122130146Sdas union __fpscr __r; 123130146Sdas 124130146Sdas if (__excepts & FE_INVALID) 125130146Sdas __excepts |= FE_ALL_EXCEPT; 126130146Sdas __mffs(&__r.__d); 127130146Sdas __r.__bits.__reg &= ~__excepts; 128130146Sdas __r.__bits.__reg |= *__flagp & __excepts; 129130146Sdas __mtfsf(__r.__d); 130130146Sdas return (0); 131130146Sdas} 132130146Sdas 133130146Sdasstatic __inline int 134130146Sdasferaiseexcept(int __excepts) 135130146Sdas{ 136130146Sdas union __fpscr __r; 137130146Sdas 138130146Sdas if (__excepts & FE_INVALID) 139130146Sdas __excepts |= FE_VXSOFT; 140130146Sdas __mffs(&__r.__d); 141130146Sdas __r.__bits.__reg |= __excepts; 142130146Sdas __mtfsf(__r.__d); 143130146Sdas return (0); 144130146Sdas} 145130146Sdas 146130146Sdasstatic __inline int 147130146Sdasfetestexcept(int __excepts) 148130146Sdas{ 149130146Sdas union __fpscr __r; 150130146Sdas 151130146Sdas __mffs(&__r.__d); 152130146Sdas return (__r.__bits.__reg & __excepts); 153130146Sdas} 154130146Sdas 155130146Sdasstatic __inline int 156130146Sdasfegetround(void) 157130146Sdas{ 158130146Sdas union __fpscr __r; 159130146Sdas 160130146Sdas __mffs(&__r.__d); 161130146Sdas return (__r.__bits.__reg & _ROUND_MASK); 162130146Sdas} 163130146Sdas 164130146Sdasstatic __inline int 165130146Sdasfesetround(int __round) 166130146Sdas{ 167130146Sdas union __fpscr __r; 168130146Sdas 169130146Sdas if (__round & ~_ROUND_MASK) 170130146Sdas return (-1); 171130146Sdas __mffs(&__r.__d); 172130146Sdas __r.__bits.__reg &= ~_ROUND_MASK; 173130146Sdas __r.__bits.__reg |= __round; 174130146Sdas __mtfsf(__r.__d); 175130146Sdas return (0); 176130146Sdas} 177130146Sdas 178130146Sdasstatic __inline int 179130146Sdasfegetenv(fenv_t *__envp) 180130146Sdas{ 181130146Sdas union __fpscr __r; 182130146Sdas 183130146Sdas __mffs(&__r.__d); 184130146Sdas *__envp = __r.__bits.__reg; 185130146Sdas return (0); 186130146Sdas} 187130146Sdas 188130146Sdasstatic __inline int 189130146Sdasfeholdexcept(fenv_t *__envp) 190130146Sdas{ 191130146Sdas union __fpscr __r; 192130146Sdas 193130146Sdas __mffs(&__r.__d); 194130146Sdas *__envp = __r.__d; 195130146Sdas __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); 196130146Sdas __mtfsf(__r.__d); 197130146Sdas return (0); 198130146Sdas} 199130146Sdas 200130146Sdasstatic __inline int 201130146Sdasfesetenv(const fenv_t *__envp) 202130146Sdas{ 203130146Sdas union __fpscr __r; 204130146Sdas 205130146Sdas __r.__bits.__reg = *__envp; 206130146Sdas __mtfsf(__r.__d); 207130146Sdas return (0); 208130146Sdas} 209130146Sdas 210130146Sdasstatic __inline int 211130146Sdasfeupdateenv(const fenv_t *__envp) 212130146Sdas{ 213130146Sdas union __fpscr __r; 214130146Sdas 215130146Sdas __mffs(&__r.__d); 216130146Sdas __r.__bits.__reg &= FE_ALL_EXCEPT; 217130146Sdas __r.__bits.__reg |= *__envp; 218130146Sdas __mtfsf(__r.__d); 219130146Sdas return (0); 220130146Sdas} 221130146Sdas 222130146Sdas#if __BSD_VISIBLE 223130146Sdas 224130146Sdasstatic __inline int 225130146Sdasfesetmask(int __mask) 226130146Sdas{ 227130146Sdas union __fpscr __r; 228130146Sdas fenv_t __oldmask; 229130146Sdas 230130146Sdas __mffs(&__r.__d); 231130146Sdas __oldmask = __r.__bits.__reg; 232130146Sdas __r.__bits.__reg &= ~_ENABLE_MASK; 233130146Sdas __r.__bits.__reg |= __mask >> _FPUSW_SHIFT; 234130146Sdas __mtfsf(__r.__d); 235130146Sdas return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 236130146Sdas} 237130146Sdas 238130146Sdasstatic __inline int 239130146Sdasfegetmask(void) 240130146Sdas{ 241130146Sdas union __fpscr __r; 242130146Sdas 243130146Sdas __mffs(&__r.__d); 244130146Sdas return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); 245130146Sdas} 246130146Sdas 247130146Sdas#endif /* __BSD_VISIBLE */ 248130146Sdas 249130146Sdas__END_DECLS 250130146Sdas 251130146Sdas#endif /* !_FENV_H_ */ 252