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$FreeBSD: releng/10.2/lib/libpmc/pmc.xscale.3 233648 2012-03-29 05:02:12Z eadler $
.Dd December 23, 2009 .Dt PMC.XSCALE 3 .Os .Sh NAME .Nm pmc.xscale .Nd measurement events for .Tn Intel .Tn XScale family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS n pmc.h .Sh DESCRIPTION .Tn Intel XScale CPUs are ARM CPUs based on the ARMv5e core.
p Second generation cores have 2 counters, while third generation cores have 4 counters. Third generation cores also have an increased number of PMC events.
p .Tn Intel XScale PMCs are documented in .Rs .%B "3rd Generation Intel XScale Microarchitecture Developer's Manual" .%D May 2007 .Re .Ss Event Specifiers (Programmable PMCs) .Tn Intel XScale programmable PMCs support the following events: l -tag -width indent t Li IC_FETCH External memory fetch due to L1 instruction cache miss. t Li IC_MISS Instruction cache or TLB miss. t Li DATA_DEPENDENCY_STALLED A data dependency stalled t Li ITLB_MISS Instruction TLB miss. t Li DTLB_MISS Data TLB miss. t Li BRANCH_RETIRED Branch instruction retired (executed). t Li BRANCH_MISPRED Branch mispredicted. t Li INSTR_RETIRED Instructions retired (executed). t Li DC_FULL_CYCLE L1 data cache buffer full stall. Event occurs on every cycle the condition is present. t Li DC_FULL_CONTIG L1 data cache buffer full stall. Event occurs once for each contiguous sequence of this type of stall. t Li DC_ACCESS L1 data cache access, not including cache operations. t Li DC_MISS L1 data cache miss, not including cache operations. t Li DC_WRITEBACK L1 data cache write-back. Occurs for each cache line that's written back from the cache. t Li PC_CHANGE Software changed the program counter. t Li BRANCH_RETIRED_ALL Branch instruction retired (executed). This event counts all branch instructions, indirect or direct. t Li INSTR_CYCLE Count the number of microarchitecture cycles each instruction requires to issue. t Li CP_STALL Coprocessor stalled the instruction pipeline. t Li PC_CHANGE_ALL Software changed the program counter (includes exceptions). t Li PIPELINE_FLUSH Pipeline flushes due to mispredictions or exceptions. t Li BACKEND_STALL Backend stalled the instruction pipeline. t Li MULTIPLIER_USE Multiplier used. t Li MULTIPLIER_STALLED Multiplier stalled the instruction pipeline. t Li DATA_CACHE_STALLED Data cache stalled the instruction pipeline. t Li L2_CACHE_REQ L2 cache request, not including cache operations. t Li L2_CACHE_MISS L2 cache miss, not including cache operations. t Li ADDRESS_BUS_TRANS Address bus transaction. t Li SELF_ADDRESS_BUS_TRANS Self initiated address bus transaction. t Li DATA_BUS_TRANS Data bus transaction. .El .Ss Event Name Aliases The following table shows the mapping between the PMC-independent aliases supported by .Lb libpmc and the underlying hardware events used. l -column "branch-mispredicts" "BRANCH_MISPRED" t Em Alias Ta Em Event t Li branches Ta Li BRANCH_RETIRED t Li branch-mispredicts Ta Li BRANCH_MISPRED t Li dc-misses Ta Li DC_MISS t Li ic-misses Ta Li IC_MISS t Li instructions Ta Li INSTR_RETIRED .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr pmc.soft 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . Intel XScale support first appeared in .Fx 9.0 . .Sh AUTHORS The .Lb libpmc library was written by .An "Joseph Koshy" .Aq jkoshy@FreeBSD.org .
p Intel XScale support was added by .An "Rui Paulo" .Aq rpaulo@FreeBSD.org . .Sh CAVEATS The Intel XScale code does not yet support sampling.