RegisterInfoEmitter.cpp revision 193323
1193323Sed//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This tablegen backend is responsible for emitting a description of a target 11193323Sed// register file for a code generator. It uses instances of the Register, 12193323Sed// RegisterAliases, and RegisterClass classes to gather this information. 13193323Sed// 14193323Sed//===----------------------------------------------------------------------===// 15193323Sed 16193323Sed#include "RegisterInfoEmitter.h" 17193323Sed#include "CodeGenTarget.h" 18193323Sed#include "CodeGenRegisters.h" 19193323Sed#include "Record.h" 20193323Sed#include "llvm/ADT/StringExtras.h" 21193323Sed#include "llvm/ADT/STLExtras.h" 22193323Sed#include "llvm/Support/Streams.h" 23193323Sed#include <set> 24193323Sed#include <algorithm> 25193323Sedusing namespace llvm; 26193323Sed 27193323Sed// runEnums - Print out enum values for all of the registers. 28193323Sedvoid RegisterInfoEmitter::runEnums(std::ostream &OS) { 29193323Sed CodeGenTarget Target; 30193323Sed const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); 31193323Sed 32193323Sed std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace"); 33193323Sed 34193323Sed EmitSourceFileHeader("Target Register Enum Values", OS); 35193323Sed OS << "namespace llvm {\n\n"; 36193323Sed 37193323Sed if (!Namespace.empty()) 38193323Sed OS << "namespace " << Namespace << " {\n"; 39193323Sed OS << " enum {\n NoRegister,\n"; 40193323Sed 41193323Sed for (unsigned i = 0, e = Registers.size(); i != e; ++i) 42193323Sed OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n"; 43193323Sed OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 44193323Sed OS << " };\n"; 45193323Sed if (!Namespace.empty()) 46193323Sed OS << "}\n"; 47193323Sed OS << "} // End llvm namespace \n"; 48193323Sed} 49193323Sed 50193323Sedvoid RegisterInfoEmitter::runHeader(std::ostream &OS) { 51193323Sed EmitSourceFileHeader("Register Information Header Fragment", OS); 52193323Sed CodeGenTarget Target; 53193323Sed const std::string &TargetName = Target.getName(); 54193323Sed std::string ClassName = TargetName + "GenRegisterInfo"; 55193323Sed 56193323Sed OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; 57193323Sed OS << "#include <string>\n\n"; 58193323Sed 59193323Sed OS << "namespace llvm {\n\n"; 60193323Sed 61193323Sed OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 62193323Sed << " explicit " << ClassName 63193323Sed << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" 64193323Sed << " virtual int getDwarfRegNumFull(unsigned RegNum, " 65193323Sed << "unsigned Flavour) const;\n" 66193323Sed << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" 67193323Sed << " virtual bool needsStackRealignment(const MachineFunction &) const\n" 68193323Sed << " { return false; }\n" 69193323Sed << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" 70193323Sed << "};\n\n"; 71193323Sed 72193323Sed const std::vector<CodeGenRegisterClass> &RegisterClasses = 73193323Sed Target.getRegisterClasses(); 74193323Sed 75193323Sed if (!RegisterClasses.empty()) { 76193323Sed OS << "namespace " << RegisterClasses[0].Namespace 77193323Sed << " { // Register classes\n"; 78193323Sed 79193323Sed OS << " enum {\n"; 80193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 81193323Sed if (i) OS << ",\n"; 82193323Sed OS << " " << RegisterClasses[i].getName() << "RegClassID"; 83193323Sed OS << " = " << (i+1); 84193323Sed } 85193323Sed OS << "\n };\n\n"; 86193323Sed 87193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 88193323Sed const std::string &Name = RegisterClasses[i].getName(); 89193323Sed 90193323Sed // Output the register class definition. 91193323Sed OS << " struct " << Name << "Class : public TargetRegisterClass {\n" 92193323Sed << " " << Name << "Class();\n" 93193323Sed << RegisterClasses[i].MethodProtos << " };\n"; 94193323Sed 95193323Sed // Output the extern for the instance. 96193323Sed OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; 97193323Sed // Output the extern for the pointer to the instance (should remove). 98193323Sed OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" 99193323Sed << Name << "RegClass;\n"; 100193323Sed } 101193323Sed OS << "} // end of namespace " << TargetName << "\n\n"; 102193323Sed } 103193323Sed OS << "} // End llvm namespace \n"; 104193323Sed} 105193323Sed 106193323Sedbool isSubRegisterClass(const CodeGenRegisterClass &RC, 107193323Sed std::set<Record*> &RegSet) { 108193323Sed for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 109193323Sed Record *Reg = RC.Elements[i]; 110193323Sed if (!RegSet.count(Reg)) 111193323Sed return false; 112193323Sed } 113193323Sed return true; 114193323Sed} 115193323Sed 116193323Sedstatic void addSuperReg(Record *R, Record *S, 117193323Sed std::map<Record*, std::set<Record*>, LessRecord> &SubRegs, 118193323Sed std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs, 119193323Sed std::map<Record*, std::set<Record*>, LessRecord> &Aliases) { 120193323Sed if (R == S) { 121193323Sed cerr << "Error: recursive sub-register relationship between" 122193323Sed << " register " << getQualifiedName(R) 123193323Sed << " and its sub-registers?\n"; 124193323Sed abort(); 125193323Sed } 126193323Sed if (!SuperRegs[R].insert(S).second) 127193323Sed return; 128193323Sed SubRegs[S].insert(R); 129193323Sed Aliases[R].insert(S); 130193323Sed Aliases[S].insert(R); 131193323Sed if (SuperRegs.count(S)) 132193323Sed for (std::set<Record*>::iterator I = SuperRegs[S].begin(), 133193323Sed E = SuperRegs[S].end(); I != E; ++I) 134193323Sed addSuperReg(R, *I, SubRegs, SuperRegs, Aliases); 135193323Sed} 136193323Sed 137193323Sedstatic void addSubSuperReg(Record *R, Record *S, 138193323Sed std::map<Record*, std::set<Record*>, LessRecord> &SubRegs, 139193323Sed std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs, 140193323Sed std::map<Record*, std::set<Record*>, LessRecord> &Aliases) { 141193323Sed if (R == S) { 142193323Sed cerr << "Error: recursive sub-register relationship between" 143193323Sed << " register " << getQualifiedName(R) 144193323Sed << " and its sub-registers?\n"; 145193323Sed abort(); 146193323Sed } 147193323Sed 148193323Sed if (!SubRegs[R].insert(S).second) 149193323Sed return; 150193323Sed addSuperReg(S, R, SubRegs, SuperRegs, Aliases); 151193323Sed Aliases[R].insert(S); 152193323Sed Aliases[S].insert(R); 153193323Sed if (SubRegs.count(S)) 154193323Sed for (std::set<Record*>::iterator I = SubRegs[S].begin(), 155193323Sed E = SubRegs[S].end(); I != E; ++I) 156193323Sed addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases); 157193323Sed} 158193323Sed 159193323Sedclass RegisterSorter { 160193323Sedprivate: 161193323Sed std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs; 162193323Sed 163193323Sedpublic: 164193323Sed RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS) 165193323Sed : RegisterSubRegs(RS) {}; 166193323Sed 167193323Sed bool operator()(Record *RegA, Record *RegB) { 168193323Sed // B is sub-register of A. 169193323Sed return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB); 170193323Sed } 171193323Sed}; 172193323Sed 173193323Sed// RegisterInfoEmitter::run - Main register file description emitter. 174193323Sed// 175193323Sedvoid RegisterInfoEmitter::run(std::ostream &OS) { 176193323Sed CodeGenTarget Target; 177193323Sed EmitSourceFileHeader("Register Information Source Fragment", OS); 178193323Sed 179193323Sed OS << "namespace llvm {\n\n"; 180193323Sed 181193323Sed // Start out by emitting each of the register classes... to do this, we build 182193323Sed // a set of registers which belong to a register class, this is to ensure that 183193323Sed // each register is only in a single register class. 184193323Sed // 185193323Sed const std::vector<CodeGenRegisterClass> &RegisterClasses = 186193323Sed Target.getRegisterClasses(); 187193323Sed 188193323Sed // Loop over all of the register classes... emitting each one. 189193323Sed OS << "namespace { // Register classes...\n"; 190193323Sed 191193323Sed // RegClassesBelongedTo - Keep track of which register classes each reg 192193323Sed // belongs to. 193193323Sed std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo; 194193323Sed 195193323Sed // Emit the register enum value arrays for each RegisterClass 196193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 197193323Sed const CodeGenRegisterClass &RC = RegisterClasses[rc]; 198193323Sed 199193323Sed // Give the register class a legal C name if it's anonymous. 200193323Sed std::string Name = RC.TheDef->getName(); 201193323Sed 202193323Sed // Emit the register list now. 203193323Sed OS << " // " << Name << " Register Class...\n" 204193323Sed << " static const unsigned " << Name 205193323Sed << "[] = {\n "; 206193323Sed for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 207193323Sed Record *Reg = RC.Elements[i]; 208193323Sed OS << getQualifiedName(Reg) << ", "; 209193323Sed 210193323Sed // Keep track of which regclasses this register is in. 211193323Sed RegClassesBelongedTo.insert(std::make_pair(Reg, &RC)); 212193323Sed } 213193323Sed OS << "\n };\n\n"; 214193323Sed } 215193323Sed 216193323Sed // Emit the ValueType arrays for each RegisterClass 217193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 218193323Sed const CodeGenRegisterClass &RC = RegisterClasses[rc]; 219193323Sed 220193323Sed // Give the register class a legal C name if it's anonymous. 221193323Sed std::string Name = RC.TheDef->getName() + "VTs"; 222193323Sed 223193323Sed // Emit the register list now. 224193323Sed OS << " // " << Name 225193323Sed << " Register Class Value Types...\n" 226193323Sed << " static const MVT " << Name 227193323Sed << "[] = {\n "; 228193323Sed for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) 229193323Sed OS << getEnumName(RC.VTs[i]) << ", "; 230193323Sed OS << "MVT::Other\n };\n\n"; 231193323Sed } 232193323Sed OS << "} // end anonymous namespace\n\n"; 233193323Sed 234193323Sed // Now that all of the structs have been emitted, emit the instances. 235193323Sed if (!RegisterClasses.empty()) { 236193323Sed OS << "namespace " << RegisterClasses[0].Namespace 237193323Sed << " { // Register class instances\n"; 238193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 239193323Sed OS << " " << RegisterClasses[i].getName() << "Class\t" 240193323Sed << RegisterClasses[i].getName() << "RegClass;\n"; 241193323Sed 242193323Sed std::map<unsigned, std::set<unsigned> > SuperClassMap; 243193323Sed std::map<unsigned, std::set<unsigned> > SuperRegClassMap; 244193323Sed OS << "\n"; 245193323Sed 246193323Sed // Emit the sub-register classes for each RegisterClass 247193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 248193323Sed const CodeGenRegisterClass &RC = RegisterClasses[rc]; 249193323Sed 250193323Sed // Give the register class a legal C name if it's anonymous. 251193323Sed std::string Name = RC.TheDef->getName(); 252193323Sed 253193323Sed OS << " // " << Name 254193323Sed << " Sub-register Classes...\n" 255193323Sed << " static const TargetRegisterClass* const " 256193323Sed << Name << "SubRegClasses [] = {\n "; 257193323Sed 258193323Sed bool Empty = true; 259193323Sed 260193323Sed for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size(); 261193323Sed subrc != subrcMax; ++subrc) { 262193323Sed unsigned rc2 = 0, e2 = RegisterClasses.size(); 263193323Sed for (; rc2 != e2; ++rc2) { 264193323Sed const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 265193323Sed if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) { 266193323Sed if (!Empty) 267193323Sed OS << ", "; 268193323Sed OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 269193323Sed Empty = false; 270193323Sed 271193323Sed std::map<unsigned, std::set<unsigned> >::iterator SCMI = 272193323Sed SuperRegClassMap.find(rc2); 273193323Sed if (SCMI == SuperRegClassMap.end()) { 274193323Sed SuperRegClassMap.insert(std::make_pair(rc2, 275193323Sed std::set<unsigned>())); 276193323Sed SCMI = SuperRegClassMap.find(rc2); 277193323Sed } 278193323Sed SCMI->second.insert(rc); 279193323Sed break; 280193323Sed } 281193323Sed } 282193323Sed if (rc2 == e2) 283193323Sed throw "Register Class member '" + 284193323Sed RC.SubRegClasses[subrc]->getName() + 285193323Sed "' is not a valid RegisterClass!"; 286193323Sed } 287193323Sed 288193323Sed OS << (!Empty ? ", " : "") << "NULL"; 289193323Sed OS << "\n };\n\n"; 290193323Sed } 291193323Sed 292193323Sed // Emit the super-register classes for each RegisterClass 293193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 294193323Sed const CodeGenRegisterClass &RC = RegisterClasses[rc]; 295193323Sed 296193323Sed // Give the register class a legal C name if it's anonymous. 297193323Sed std::string Name = RC.TheDef->getName(); 298193323Sed 299193323Sed OS << " // " << Name 300193323Sed << " Super-register Classes...\n" 301193323Sed << " static const TargetRegisterClass* const " 302193323Sed << Name << "SuperRegClasses [] = {\n "; 303193323Sed 304193323Sed bool Empty = true; 305193323Sed std::map<unsigned, std::set<unsigned> >::iterator I = 306193323Sed SuperRegClassMap.find(rc); 307193323Sed if (I != SuperRegClassMap.end()) { 308193323Sed for (std::set<unsigned>::iterator II = I->second.begin(), 309193323Sed EE = I->second.end(); II != EE; ++II) { 310193323Sed const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 311193323Sed if (!Empty) 312193323Sed OS << ", "; 313193323Sed OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 314193323Sed Empty = false; 315193323Sed } 316193323Sed } 317193323Sed 318193323Sed OS << (!Empty ? ", " : "") << "NULL"; 319193323Sed OS << "\n };\n\n"; 320193323Sed } 321193323Sed 322193323Sed // Emit the sub-classes array for each RegisterClass 323193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 324193323Sed const CodeGenRegisterClass &RC = RegisterClasses[rc]; 325193323Sed 326193323Sed // Give the register class a legal C name if it's anonymous. 327193323Sed std::string Name = RC.TheDef->getName(); 328193323Sed 329193323Sed std::set<Record*> RegSet; 330193323Sed for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 331193323Sed Record *Reg = RC.Elements[i]; 332193323Sed RegSet.insert(Reg); 333193323Sed } 334193323Sed 335193323Sed OS << " // " << Name 336193323Sed << " Register Class sub-classes...\n" 337193323Sed << " static const TargetRegisterClass* const " 338193323Sed << Name << "Subclasses [] = {\n "; 339193323Sed 340193323Sed bool Empty = true; 341193323Sed for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { 342193323Sed const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 343193323Sed 344193323Sed // RC2 is a sub-class of RC if it is a valid replacement for any 345193323Sed // instruction operand where an RC register is required. It must satisfy 346193323Sed // these conditions: 347193323Sed // 348193323Sed // 1. All RC2 registers are also in RC. 349193323Sed // 2. The RC2 spill size must not be smaller that the RC spill size. 350193323Sed // 3. RC2 spill alignment must be compatible with RC. 351193323Sed // 352193323Sed // Sub-classes are used to determine if a virtual register can be used 353193323Sed // as an instruction operand, or if it must be copied first. 354193323Sed 355193323Sed if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() || 356193323Sed (RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) || 357193323Sed RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet)) 358193323Sed continue; 359193323Sed 360193323Sed if (!Empty) OS << ", "; 361193323Sed OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 362193323Sed Empty = false; 363193323Sed 364193323Sed std::map<unsigned, std::set<unsigned> >::iterator SCMI = 365193323Sed SuperClassMap.find(rc2); 366193323Sed if (SCMI == SuperClassMap.end()) { 367193323Sed SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>())); 368193323Sed SCMI = SuperClassMap.find(rc2); 369193323Sed } 370193323Sed SCMI->second.insert(rc); 371193323Sed } 372193323Sed 373193323Sed OS << (!Empty ? ", " : "") << "NULL"; 374193323Sed OS << "\n };\n\n"; 375193323Sed } 376193323Sed 377193323Sed for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 378193323Sed const CodeGenRegisterClass &RC = RegisterClasses[rc]; 379193323Sed 380193323Sed // Give the register class a legal C name if it's anonymous. 381193323Sed std::string Name = RC.TheDef->getName(); 382193323Sed 383193323Sed OS << " // " << Name 384193323Sed << " Register Class super-classes...\n" 385193323Sed << " static const TargetRegisterClass* const " 386193323Sed << Name << "Superclasses [] = {\n "; 387193323Sed 388193323Sed bool Empty = true; 389193323Sed std::map<unsigned, std::set<unsigned> >::iterator I = 390193323Sed SuperClassMap.find(rc); 391193323Sed if (I != SuperClassMap.end()) { 392193323Sed for (std::set<unsigned>::iterator II = I->second.begin(), 393193323Sed EE = I->second.end(); II != EE; ++II) { 394193323Sed const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 395193323Sed if (!Empty) OS << ", "; 396193323Sed OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 397193323Sed Empty = false; 398193323Sed } 399193323Sed } 400193323Sed 401193323Sed OS << (!Empty ? ", " : "") << "NULL"; 402193323Sed OS << "\n };\n\n"; 403193323Sed } 404193323Sed 405193323Sed 406193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 407193323Sed const CodeGenRegisterClass &RC = RegisterClasses[i]; 408193323Sed OS << RC.MethodBodies << "\n"; 409193323Sed OS << RC.getName() << "Class::" << RC.getName() 410193323Sed << "Class() : TargetRegisterClass(" 411193323Sed << RC.getName() + "RegClassID" << ", " 412193323Sed << '\"' << RC.getName() << "\", " 413193323Sed << RC.getName() + "VTs" << ", " 414193323Sed << RC.getName() + "Subclasses" << ", " 415193323Sed << RC.getName() + "Superclasses" << ", " 416193323Sed << RC.getName() + "SubRegClasses" << ", " 417193323Sed << RC.getName() + "SuperRegClasses" << ", " 418193323Sed << RC.SpillSize/8 << ", " 419193323Sed << RC.SpillAlignment/8 << ", " 420193323Sed << RC.CopyCost << ", " 421193323Sed << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size() 422193323Sed << ") {}\n"; 423193323Sed } 424193323Sed 425193323Sed OS << "}\n"; 426193323Sed } 427193323Sed 428193323Sed OS << "\nnamespace {\n"; 429193323Sed OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 430193323Sed for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 431193323Sed OS << " &" << getQualifiedName(RegisterClasses[i].TheDef) 432193323Sed << "RegClass,\n"; 433193323Sed OS << " };\n"; 434193323Sed 435193323Sed // Emit register sub-registers / super-registers, aliases... 436193323Sed std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs; 437193323Sed std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs; 438193323Sed std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases; 439193323Sed std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors; 440193323Sed typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy; 441193323Sed DwarfRegNumsMapTy DwarfRegNums; 442193323Sed 443193323Sed const std::vector<CodeGenRegister> &Regs = Target.getRegisters(); 444193323Sed 445193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 446193323Sed Record *R = Regs[i].TheDef; 447193323Sed std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases"); 448193323Sed // Add information that R aliases all of the elements in the list... and 449193323Sed // that everything in the list aliases R. 450193323Sed for (unsigned j = 0, e = LI.size(); j != e; ++j) { 451193323Sed Record *Reg = LI[j]; 452193323Sed if (RegisterAliases[R].count(Reg)) 453193323Sed cerr << "Warning: register alias between " << getQualifiedName(R) 454193323Sed << " and " << getQualifiedName(Reg) 455193323Sed << " specified multiple times!\n"; 456193323Sed RegisterAliases[R].insert(Reg); 457193323Sed 458193323Sed if (RegisterAliases[Reg].count(R)) 459193323Sed cerr << "Warning: register alias between " << getQualifiedName(R) 460193323Sed << " and " << getQualifiedName(Reg) 461193323Sed << " specified multiple times!\n"; 462193323Sed RegisterAliases[Reg].insert(R); 463193323Sed } 464193323Sed } 465193323Sed 466193323Sed // Process sub-register sets. 467193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 468193323Sed Record *R = Regs[i].TheDef; 469193323Sed std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs"); 470193323Sed // Process sub-register set and add aliases information. 471193323Sed for (unsigned j = 0, e = LI.size(); j != e; ++j) { 472193323Sed Record *SubReg = LI[j]; 473193323Sed if (RegisterSubRegs[R].count(SubReg)) 474193323Sed cerr << "Warning: register " << getQualifiedName(SubReg) 475193323Sed << " specified as a sub-register of " << getQualifiedName(R) 476193323Sed << " multiple times!\n"; 477193323Sed addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs, 478193323Sed RegisterAliases); 479193323Sed } 480193323Sed } 481193323Sed 482193323Sed // Print the SubregHashTable, a simple quadratically probed 483193323Sed // hash table for determining if a register is a subregister 484193323Sed // of another register. 485193323Sed unsigned NumSubRegs = 0; 486193323Sed std::map<Record*, unsigned> RegNo; 487193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 488193323Sed RegNo[Regs[i].TheDef] = i; 489193323Sed NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size(); 490193323Sed } 491193323Sed 492193323Sed unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs); 493193323Sed unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize]; 494193323Sed std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U); 495193323Sed 496193323Sed unsigned hashMisses = 0; 497193323Sed 498193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 499193323Sed Record* R = Regs[i].TheDef; 500193323Sed for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(), 501193323Sed E = RegisterSubRegs[R].end(); I != E; ++I) { 502193323Sed Record* RJ = *I; 503193323Sed // We have to increase the indices of both registers by one when 504193323Sed // computing the hash because, in the generated code, there 505193323Sed // will be an extra empty slot at register 0. 506193323Sed size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1); 507193323Sed unsigned ProbeAmt = 2; 508193323Sed while (SubregHashTable[index*2] != ~0U && 509193323Sed SubregHashTable[index*2+1] != ~0U) { 510193323Sed index = (index + ProbeAmt) & (SubregHashTableSize-1); 511193323Sed ProbeAmt += 2; 512193323Sed 513193323Sed hashMisses++; 514193323Sed } 515193323Sed 516193323Sed SubregHashTable[index*2] = i; 517193323Sed SubregHashTable[index*2+1] = RegNo[RJ]; 518193323Sed } 519193323Sed } 520193323Sed 521193323Sed OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; 522193323Sed 523193323Sed if (SubregHashTableSize) { 524193323Sed std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); 525193323Sed 526193323Sed OS << " const unsigned SubregHashTable[] = { "; 527193323Sed for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) { 528193323Sed if (i != 0) 529193323Sed // Insert spaces for nice formatting. 530193323Sed OS << " "; 531193323Sed 532193323Sed if (SubregHashTable[2*i] != ~0U) { 533193323Sed OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", " 534193323Sed << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n"; 535193323Sed } else { 536193323Sed OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; 537193323Sed } 538193323Sed } 539193323Sed 540193323Sed unsigned Idx = SubregHashTableSize*2-2; 541193323Sed if (SubregHashTable[Idx] != ~0U) { 542193323Sed OS << " " 543193323Sed << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", " 544193323Sed << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n"; 545193323Sed } else { 546193323Sed OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; 547193323Sed } 548193323Sed 549193323Sed OS << " const unsigned SubregHashTableSize = " 550193323Sed << SubregHashTableSize << ";\n"; 551193323Sed } else { 552193323Sed OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n" 553193323Sed << " const unsigned SubregHashTableSize = 1;\n"; 554193323Sed } 555193323Sed 556193323Sed delete [] SubregHashTable; 557193323Sed 558193323Sed 559193323Sed // Print the SuperregHashTable, a simple quadratically probed 560193323Sed // hash table for determining if a register is a super-register 561193323Sed // of another register. 562193323Sed unsigned NumSupRegs = 0; 563193323Sed RegNo.clear(); 564193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 565193323Sed RegNo[Regs[i].TheDef] = i; 566193323Sed NumSupRegs += RegisterSuperRegs[Regs[i].TheDef].size(); 567193323Sed } 568193323Sed 569193323Sed unsigned SuperregHashTableSize = 2 * NextPowerOf2(2 * NumSupRegs); 570193323Sed unsigned* SuperregHashTable = new unsigned[2 * SuperregHashTableSize]; 571193323Sed std::fill(SuperregHashTable, SuperregHashTable + 2 * SuperregHashTableSize, ~0U); 572193323Sed 573193323Sed hashMisses = 0; 574193323Sed 575193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 576193323Sed Record* R = Regs[i].TheDef; 577193323Sed for (std::set<Record*>::iterator I = RegisterSuperRegs[R].begin(), 578193323Sed E = RegisterSuperRegs[R].end(); I != E; ++I) { 579193323Sed Record* RJ = *I; 580193323Sed // We have to increase the indices of both registers by one when 581193323Sed // computing the hash because, in the generated code, there 582193323Sed // will be an extra empty slot at register 0. 583193323Sed size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SuperregHashTableSize-1); 584193323Sed unsigned ProbeAmt = 2; 585193323Sed while (SuperregHashTable[index*2] != ~0U && 586193323Sed SuperregHashTable[index*2+1] != ~0U) { 587193323Sed index = (index + ProbeAmt) & (SuperregHashTableSize-1); 588193323Sed ProbeAmt += 2; 589193323Sed 590193323Sed hashMisses++; 591193323Sed } 592193323Sed 593193323Sed SuperregHashTable[index*2] = i; 594193323Sed SuperregHashTable[index*2+1] = RegNo[RJ]; 595193323Sed } 596193323Sed } 597193323Sed 598193323Sed OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; 599193323Sed 600193323Sed if (SuperregHashTableSize) { 601193323Sed std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); 602193323Sed 603193323Sed OS << " const unsigned SuperregHashTable[] = { "; 604193323Sed for (unsigned i = 0; i < SuperregHashTableSize - 1; ++i) { 605193323Sed if (i != 0) 606193323Sed // Insert spaces for nice formatting. 607193323Sed OS << " "; 608193323Sed 609193323Sed if (SuperregHashTable[2*i] != ~0U) { 610193323Sed OS << getQualifiedName(Regs[SuperregHashTable[2*i]].TheDef) << ", " 611193323Sed << getQualifiedName(Regs[SuperregHashTable[2*i+1]].TheDef) << ", \n"; 612193323Sed } else { 613193323Sed OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; 614193323Sed } 615193323Sed } 616193323Sed 617193323Sed unsigned Idx = SuperregHashTableSize*2-2; 618193323Sed if (SuperregHashTable[Idx] != ~0U) { 619193323Sed OS << " " 620193323Sed << getQualifiedName(Regs[SuperregHashTable[Idx]].TheDef) << ", " 621193323Sed << getQualifiedName(Regs[SuperregHashTable[Idx+1]].TheDef) << " };\n"; 622193323Sed } else { 623193323Sed OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; 624193323Sed } 625193323Sed 626193323Sed OS << " const unsigned SuperregHashTableSize = " 627193323Sed << SuperregHashTableSize << ";\n"; 628193323Sed } else { 629193323Sed OS << " const unsigned SuperregHashTable[] = { ~0U, ~0U };\n" 630193323Sed << " const unsigned SuperregHashTableSize = 1;\n"; 631193323Sed } 632193323Sed 633193323Sed delete [] SuperregHashTable; 634193323Sed 635193323Sed 636193323Sed // Print the AliasHashTable, a simple quadratically probed 637193323Sed // hash table for determining if a register aliases another register. 638193323Sed unsigned NumAliases = 0; 639193323Sed RegNo.clear(); 640193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 641193323Sed RegNo[Regs[i].TheDef] = i; 642193323Sed NumAliases += RegisterAliases[Regs[i].TheDef].size(); 643193323Sed } 644193323Sed 645193323Sed unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases); 646193323Sed unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize]; 647193323Sed std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U); 648193323Sed 649193323Sed hashMisses = 0; 650193323Sed 651193323Sed for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 652193323Sed Record* R = Regs[i].TheDef; 653193323Sed for (std::set<Record*>::iterator I = RegisterAliases[R].begin(), 654193323Sed E = RegisterAliases[R].end(); I != E; ++I) { 655193323Sed Record* RJ = *I; 656193323Sed // We have to increase the indices of both registers by one when 657193323Sed // computing the hash because, in the generated code, there 658193323Sed // will be an extra empty slot at register 0. 659193323Sed size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1); 660193323Sed unsigned ProbeAmt = 2; 661193323Sed while (AliasesHashTable[index*2] != ~0U && 662193323Sed AliasesHashTable[index*2+1] != ~0U) { 663193323Sed index = (index + ProbeAmt) & (AliasesHashTableSize-1); 664193323Sed ProbeAmt += 2; 665193323Sed 666193323Sed hashMisses++; 667193323Sed } 668193323Sed 669193323Sed AliasesHashTable[index*2] = i; 670193323Sed AliasesHashTable[index*2+1] = RegNo[RJ]; 671193323Sed } 672193323Sed } 673193323Sed 674193323Sed OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; 675193323Sed 676193323Sed if (AliasesHashTableSize) { 677193323Sed std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); 678193323Sed 679193323Sed OS << " const unsigned AliasesHashTable[] = { "; 680193323Sed for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) { 681193323Sed if (i != 0) 682193323Sed // Insert spaces for nice formatting. 683193323Sed OS << " "; 684193323Sed 685193323Sed if (AliasesHashTable[2*i] != ~0U) { 686193323Sed OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", " 687193323Sed << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n"; 688193323Sed } else { 689193323Sed OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; 690193323Sed } 691193323Sed } 692193323Sed 693193323Sed unsigned Idx = AliasesHashTableSize*2-2; 694193323Sed if (AliasesHashTable[Idx] != ~0U) { 695193323Sed OS << " " 696193323Sed << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", " 697193323Sed << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n"; 698193323Sed } else { 699193323Sed OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; 700193323Sed } 701193323Sed 702193323Sed OS << " const unsigned AliasesHashTableSize = " 703193323Sed << AliasesHashTableSize << ";\n"; 704193323Sed } else { 705193323Sed OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n" 706193323Sed << " const unsigned AliasesHashTableSize = 1;\n"; 707193323Sed } 708193323Sed 709193323Sed delete [] AliasesHashTable; 710193323Sed 711193323Sed if (!RegisterAliases.empty()) 712193323Sed OS << "\n\n // Register Alias Sets...\n"; 713193323Sed 714193323Sed // Emit the empty alias list 715193323Sed OS << " const unsigned Empty_AliasSet[] = { 0 };\n"; 716193323Sed // Loop over all of the registers which have aliases, emitting the alias list 717193323Sed // to memory. 718193323Sed for (std::map<Record*, std::set<Record*>, LessRecord >::iterator 719193323Sed I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) { 720193323Sed OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { "; 721193323Sed for (std::set<Record*>::iterator ASI = I->second.begin(), 722193323Sed E = I->second.end(); ASI != E; ++ASI) 723193323Sed OS << getQualifiedName(*ASI) << ", "; 724193323Sed OS << "0 };\n"; 725193323Sed } 726193323Sed 727193323Sed if (!RegisterSubRegs.empty()) 728193323Sed OS << "\n\n // Register Sub-registers Sets...\n"; 729193323Sed 730193323Sed // Emit the empty sub-registers list 731193323Sed OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; 732193323Sed // Loop over all of the registers which have sub-registers, emitting the 733193323Sed // sub-registers list to memory. 734193323Sed for (std::map<Record*, std::set<Record*>, LessRecord>::iterator 735193323Sed I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) { 736193323Sed OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { "; 737193323Sed std::vector<Record*> SubRegsVector; 738193323Sed for (std::set<Record*>::iterator ASI = I->second.begin(), 739193323Sed E = I->second.end(); ASI != E; ++ASI) 740193323Sed SubRegsVector.push_back(*ASI); 741193323Sed RegisterSorter RS(RegisterSubRegs); 742193323Sed std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS); 743193323Sed for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i) 744193323Sed OS << getQualifiedName(SubRegsVector[i]) << ", "; 745193323Sed OS << "0 };\n"; 746193323Sed } 747193323Sed 748193323Sed if (!RegisterSuperRegs.empty()) 749193323Sed OS << "\n\n // Register Super-registers Sets...\n"; 750193323Sed 751193323Sed // Emit the empty super-registers list 752193323Sed OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; 753193323Sed // Loop over all of the registers which have super-registers, emitting the 754193323Sed // super-registers list to memory. 755193323Sed for (std::map<Record*, std::set<Record*>, LessRecord >::iterator 756193323Sed I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) { 757193323Sed OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { "; 758193323Sed 759193323Sed std::vector<Record*> SuperRegsVector; 760193323Sed for (std::set<Record*>::iterator ASI = I->second.begin(), 761193323Sed E = I->second.end(); ASI != E; ++ASI) 762193323Sed SuperRegsVector.push_back(*ASI); 763193323Sed RegisterSorter RS(RegisterSubRegs); 764193323Sed std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS); 765193323Sed for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i) 766193323Sed OS << getQualifiedName(SuperRegsVector[i]) << ", "; 767193323Sed OS << "0 };\n"; 768193323Sed } 769193323Sed 770193323Sed OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; 771193323Sed OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n"; 772193323Sed 773193323Sed // Now that register alias and sub-registers sets have been emitted, emit the 774193323Sed // register descriptors now. 775193323Sed const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); 776193323Sed for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 777193323Sed const CodeGenRegister &Reg = Registers[i]; 778193323Sed OS << " { \""; 779193323Sed if (!Reg.TheDef->getValueAsString("AsmName").empty()) 780193323Sed OS << Reg.TheDef->getValueAsString("AsmName"); 781193323Sed else 782193323Sed OS << Reg.getName(); 783193323Sed OS << "\",\t\""; 784193323Sed OS << Reg.getName() << "\",\t"; 785193323Sed if (RegisterAliases.count(Reg.TheDef)) 786193323Sed OS << Reg.getName() << "_AliasSet,\t"; 787193323Sed else 788193323Sed OS << "Empty_AliasSet,\t"; 789193323Sed if (RegisterSubRegs.count(Reg.TheDef)) 790193323Sed OS << Reg.getName() << "_SubRegsSet,\t"; 791193323Sed else 792193323Sed OS << "Empty_SubRegsSet,\t"; 793193323Sed if (RegisterSuperRegs.count(Reg.TheDef)) 794193323Sed OS << Reg.getName() << "_SuperRegsSet },\n"; 795193323Sed else 796193323Sed OS << "Empty_SuperRegsSet },\n"; 797193323Sed } 798193323Sed OS << " };\n"; // End of register descriptors... 799193323Sed OS << "}\n\n"; // End of anonymous namespace... 800193323Sed 801193323Sed std::string ClassName = Target.getName() + "GenRegisterInfo"; 802193323Sed 803193323Sed // Calculate the mapping of subregister+index pairs to physical registers. 804193323Sed std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet"); 805193323Sed for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) { 806193323Sed int subRegIndex = SubRegs[i]->getValueAsInt("index"); 807193323Sed std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From"); 808193323Sed std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To"); 809193323Sed 810193323Sed if (From.size() != To.size()) { 811193323Sed cerr << "Error: register list and sub-register list not of equal length" 812193323Sed << " in SubRegSet\n"; 813193323Sed exit(1); 814193323Sed } 815193323Sed 816193323Sed // For each entry in from/to vectors, insert the to register at index 817193323Sed for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii) 818193323Sed SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii])); 819193323Sed } 820193323Sed 821193323Sed // Emit the subregister + index mapping function based on the information 822193323Sed // calculated above. 823193323Sed OS << "unsigned " << ClassName 824193323Sed << "::getSubReg(unsigned RegNo, unsigned Index) const {\n" 825193323Sed << " switch (RegNo) {\n" 826193323Sed << " default:\n return 0;\n"; 827193323Sed for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator 828193323Sed I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) { 829193323Sed OS << " case " << getQualifiedName(I->first) << ":\n"; 830193323Sed OS << " switch (Index) {\n"; 831193323Sed OS << " default: return 0;\n"; 832193323Sed for (unsigned i = 0, e = I->second.size(); i != e; ++i) 833193323Sed OS << " case " << (I->second)[i].first << ": return " 834193323Sed << getQualifiedName((I->second)[i].second) << ";\n"; 835193323Sed OS << " };\n" << " break;\n"; 836193323Sed } 837193323Sed OS << " };\n"; 838193323Sed OS << " return 0;\n"; 839193323Sed OS << "}\n\n"; 840193323Sed 841193323Sed // Emit the constructor of the class... 842193323Sed OS << ClassName << "::" << ClassName 843193323Sed << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" 844193323Sed << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1 845193323Sed << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n " 846193323Sed << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n" 847193323Sed << " SubregHashTable, SubregHashTableSize,\n" 848193323Sed << " SuperregHashTable, SuperregHashTableSize,\n" 849193323Sed << " AliasesHashTable, AliasesHashTableSize) {\n" 850193323Sed << "}\n\n"; 851193323Sed 852193323Sed // Collect all information about dwarf register numbers 853193323Sed 854193323Sed // First, just pull all provided information to the map 855193323Sed unsigned maxLength = 0; 856193323Sed for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 857193323Sed Record *Reg = Registers[i].TheDef; 858193323Sed std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 859193323Sed maxLength = std::max((size_t)maxLength, RegNums.size()); 860193323Sed if (DwarfRegNums.count(Reg)) 861193323Sed cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg) 862193323Sed << "specified multiple times\n"; 863193323Sed DwarfRegNums[Reg] = RegNums; 864193323Sed } 865193323Sed 866193323Sed // Now we know maximal length of number list. Append -1's, where needed 867193323Sed for (DwarfRegNumsMapTy::iterator 868193323Sed I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 869193323Sed for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 870193323Sed I->second.push_back(-1); 871193323Sed 872193323Sed // Emit information about the dwarf register numbers. 873193323Sed OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, " 874193323Sed << "unsigned Flavour) const {\n" 875193323Sed << " switch (Flavour) {\n" 876193323Sed << " default:\n" 877193323Sed << " assert(0 && \"Unknown DWARF flavour\");\n" 878193323Sed << " return -1;\n"; 879193323Sed 880193323Sed for (unsigned i = 0, e = maxLength; i != e; ++i) { 881193323Sed OS << " case " << i << ":\n" 882193323Sed << " switch (RegNum) {\n" 883193323Sed << " default:\n" 884193323Sed << " assert(0 && \"Invalid RegNum\");\n" 885193323Sed << " return -1;\n"; 886193323Sed 887193323Sed // Sort by name to get a stable order. 888193323Sed 889193323Sed 890193323Sed for (DwarfRegNumsMapTy::iterator 891193323Sed I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 892193323Sed int RegNo = I->second[i]; 893193323Sed if (RegNo != -2) 894193323Sed OS << " case " << getQualifiedName(I->first) << ":\n" 895193323Sed << " return " << RegNo << ";\n"; 896193323Sed else 897193323Sed OS << " case " << getQualifiedName(I->first) << ":\n" 898193323Sed << " assert(0 && \"Invalid register for this mode\");\n" 899193323Sed << " return -1;\n"; 900193323Sed } 901193323Sed OS << " };\n"; 902193323Sed } 903193323Sed 904193323Sed OS << " };\n}\n\n"; 905193323Sed 906193323Sed OS << "} // End llvm namespace \n"; 907193323Sed} 908