1263320SdimPull in r199786 from upstream llvm trunk (by Venkatraman Govindaraju): 2263320Sdim 3263320Sdim [Sparc] Add support for inline assembly constraints which specify registers by their aliases. 4263320Sdim 5269012SemasteIntroduced here: http://svnweb.freebsd.org/changeset/base/262261 6263320Sdim 7263320SdimIndex: lib/Target/Sparc/SparcISelLowering.cpp 8263320Sdim=================================================================== 9263320Sdim--- lib/Target/Sparc/SparcISelLowering.cpp 10263320Sdim+++ lib/Target/Sparc/SparcISelLowering.cpp 11263320Sdim@@ -2992,6 +2992,26 @@ SparcTargetLowering::getRegForInlineAsmConstraint( 12263320Sdim case 'r': 13263320Sdim return std::make_pair(0U, &SP::IntRegsRegClass); 14263320Sdim } 15263320Sdim+ } else if (!Constraint.empty() && Constraint.size() <= 5 16263320Sdim+ && Constraint[0] == '{' && *(Constraint.end()-1) == '}') { 17263320Sdim+ // constraint = '{r<d>}' 18263320Sdim+ // Remove the braces from around the name. 19263320Sdim+ StringRef name(Constraint.data()+1, Constraint.size()-2); 20263320Sdim+ // Handle register aliases: 21263320Sdim+ // r0-r7 -> g0-g7 22263320Sdim+ // r8-r15 -> o0-o7 23263320Sdim+ // r16-r23 -> l0-l7 24263320Sdim+ // r24-r31 -> i0-i7 25263320Sdim+ uint64_t intVal = 0; 26263320Sdim+ if (name.substr(0, 1).equals("r") 27263320Sdim+ && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) { 28263320Sdim+ const char regTypes[] = { 'g', 'o', 'l', 'i' }; 29263320Sdim+ char regType = regTypes[intVal/8]; 30263320Sdim+ char regIdx = '0' + (intVal % 8); 31263320Sdim+ char tmp[] = { '{', regType, regIdx, '}', 0 }; 32263320Sdim+ std::string newConstraint = std::string(tmp); 33263320Sdim+ return TargetLowering::getRegForInlineAsmConstraint(newConstraint, VT); 34263320Sdim+ } 35263320Sdim } 36263320Sdim 37263320Sdim return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 38263320SdimIndex: test/CodeGen/SPARC/inlineasm.ll 39263320Sdim=================================================================== 40263320Sdim--- test/CodeGen/SPARC/inlineasm.ll 41263320Sdim+++ test/CodeGen/SPARC/inlineasm.ll 42263320Sdim@@ -33,3 +33,13 @@ entry: 43263320Sdim %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000) 44263320Sdim ret i32 %0 45263320Sdim } 46263320Sdim+ 47263320Sdim+; CHECK-LABEL: test_constraint_reg 48263320Sdim+; CHECK: ldda [%o1] 43, %g2 49263320Sdim+; CHECK: ldda [%o1] 43, %g3 50263320Sdim+define void @test_constraint_reg(i32 %s, i32* %ptr) { 51263320Sdim+entry: 52263320Sdim+ %0 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={r2},r,n"(i32* %ptr, i32 43) 53263320Sdim+ %1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g3},r,n"(i32* %ptr, i32 43) 54263320Sdim+ ret void 55263320Sdim+} 56