1263320SdimPull in r199187 from upstream llvm trunk (by Jakob Stoklund Olesen): 2263320Sdim 3263320Sdim Always let value types influence register classes. 4263320Sdim 5263320Sdim When creating a virtual register for a def, the value type should be 6263320Sdim used to pick the register class. If we only use the register class 7263320Sdim constraint on the instruction, we might pick a too large register class. 8263320Sdim 9263320Sdim Some registers can store values of different sizes. For example, the x86 10263320Sdim xmm registers can hold f32, f64, and 128-bit vectors. The three 11263320Sdim different value sizes are represented by register classes with identical 12263320Sdim register sets: FR32, FR64, and VR128. These register classes have 13263320Sdim different spill slot sizes, so it is important to use the right one. 14263320Sdim 15263320Sdim The register class constraint on an instruction doesn't necessarily care 16263320Sdim about the size of the value its defining. The value type determines 17263320Sdim that. 18263320Sdim 19263320Sdim This fixes a problem where InstrEmitter was picking 32-bit register 20263320Sdim classes for 64-bit values on SPARC. 21263320Sdim 22269012SemasteIntroduced here: http://svnweb.freebsd.org/changeset/base/262261 23263320Sdim 24263320SdimIndex: test/CodeGen/SPARC/spillsize.ll 25263320Sdim=================================================================== 26263320Sdim--- test/CodeGen/SPARC/spillsize.ll 27263320Sdim+++ test/CodeGen/SPARC/spillsize.ll 28263320Sdim@@ -0,0 +1,25 @@ 29263320Sdim+; RUN: llc < %s -verify-machineinstrs | FileCheck %s 30263320Sdim+target datalayout = "E-m:e-i64:64-n32:64-S128" 31263320Sdim+target triple = "sparcv9" 32263320Sdim+ 33263320Sdim+; CHECK-LABEL: spill4 34263320Sdim+; This function spills two values: %p and the materialized large constant. 35263320Sdim+; Both must use 8-byte spill and fill instructions. 36263320Sdim+; CHECK: stx %{{..}}, [%fp+ 37263320Sdim+; CHECK: stx %{{..}}, [%fp+ 38263320Sdim+; CHECK: ldx [%fp+ 39263320Sdim+; CHECK: ldx [%fp+ 40263320Sdim+define void @spill4(i64* nocapture %p) { 41263320Sdim+entry: 42263320Sdim+ %val0 = load i64* %p 43263320Sdim+ %cmp0 = icmp ult i64 %val0, 385672958347594845 44263320Sdim+ %cm80 = zext i1 %cmp0 to i64 45263320Sdim+ store i64 %cm80, i64* %p, align 8 46263320Sdim+ tail call void asm sideeffect "", "~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{g2},~{g3},~{g4},~{g5},~{l0},~{l1},~{l2},~{l3},~{l4},~{l5},~{l6},~{l7},~{o0},~{o1},~{o2},~{o3},~{o4},~{o5},~{o7}"() 47263320Sdim+ %arrayidx1 = getelementptr inbounds i64* %p, i64 1 48263320Sdim+ %val = load i64* %arrayidx1 49263320Sdim+ %cmp = icmp ult i64 %val, 385672958347594845 50263320Sdim+ %cm8 = select i1 %cmp, i64 10, i64 20 51263320Sdim+ store i64 %cm8, i64* %arrayidx1, align 8 52263320Sdim+ ret void 53263320Sdim+} 54263320SdimIndex: lib/CodeGen/SelectionDAG/InstrEmitter.cpp 55263320Sdim=================================================================== 56263320Sdim--- lib/CodeGen/SelectionDAG/InstrEmitter.cpp 57263320Sdim+++ lib/CodeGen/SelectionDAG/InstrEmitter.cpp 58263320Sdim@@ -220,10 +220,19 @@ void InstrEmitter::CreateVirtualRegisters(SDNode * 59263320Sdim unsigned VRBase = 0; 60263320Sdim const TargetRegisterClass *RC = 61263320Sdim TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 62263320Sdim- // If the register class is unknown for the given definition, then try to 63263320Sdim- // infer one from the value type. 64263320Sdim- if (!RC && i < NumResults) 65263320Sdim- RC = TLI->getRegClassFor(Node->getSimpleValueType(i)); 66263320Sdim+ // Always let the value type influence the used register class. The 67263320Sdim+ // constraints on the instruction may be too lax to represent the value 68263320Sdim+ // type correctly. For example, a 64-bit float (X86::FR64) can't live in 69263320Sdim+ // the 32-bit float super-class (X86::FR32). 70263320Sdim+ if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { 71263320Sdim+ const TargetRegisterClass *VTRC = 72263320Sdim+ TLI->getRegClassFor(Node->getSimpleValueType(i)); 73263320Sdim+ if (RC) 74263320Sdim+ VTRC = TRI->getCommonSubClass(RC, VTRC); 75263320Sdim+ if (VTRC) 76263320Sdim+ RC = VTRC; 77263320Sdim+ } 78263320Sdim+ 79263320Sdim if (II.OpInfo[i].isOptionalDef()) { 80263320Sdim // Optional def must be a physical register. 81263320Sdim unsigned NumResults = CountResults(Node); 82