1263320SdimPull in r199028 from upstream llvm trunk (by Jakob Stoklund Olesen): 2263320Sdim 3263320Sdim The SPARCv9 ABI returns a float in %f0. 4263320Sdim 5263320Sdim This is different from the argument passing convention which puts the 6263320Sdim first float argument in %f1. 7263320Sdim 8263320Sdim With this patch, all returned floats are treated as if the 'inreg' flag 9263320Sdim were set. This means multiple float return values get packed in %f0, 10263320Sdim %f1, %f2, ... 11263320Sdim 12263320Sdim Note that when returning a struct in registers, clang will set the 13263320Sdim 'inreg' flag on the return value, so that behavior is unchanged. This 14263320Sdim also happens when returning a float _Complex. 15263320Sdim 16269012SemasteIntroduced here: http://svnweb.freebsd.org/changeset/base/262261 17263320Sdim 18263320SdimIndex: test/CodeGen/SPARC/64abi.ll 19263320Sdim=================================================================== 20263320Sdim--- test/CodeGen/SPARC/64abi.ll 21263320Sdim+++ test/CodeGen/SPARC/64abi.ll 22263320Sdim@@ -180,7 +180,7 @@ define void @call_inreg_fi(i32* %p, i32 %i1, float 23263320Sdim } 24263320Sdim 25263320Sdim ; CHECK: inreg_ff 26263320Sdim-; CHECK: fsubs %f0, %f1, %f1 27263320Sdim+; CHECK: fsubs %f0, %f1, %f0 28263320Sdim define float @inreg_ff(float inreg %a0, ; %f0 29263320Sdim float inreg %a1) { ; %f1 30263320Sdim %rv = fsub float %a0, %a1 31263320Sdim@@ -262,10 +262,10 @@ define void @call_ret_i64_pair(i64* %i0) { 32263320Sdim ret void 33263320Sdim } 34263320Sdim 35263320Sdim-; This is not a C struct, each member uses 8 bytes. 36263320Sdim+; This is not a C struct, the i32 member uses 8 bytes, but the float only 4. 37263320Sdim ; CHECK: ret_i32_float_pair 38263320Sdim ; CHECK: ld [%i2], %i0 39263320Sdim-; CHECK: ld [%i3], %f3 40263320Sdim+; CHECK: ld [%i3], %f2 41263320Sdim define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1, 42263320Sdim i32* %p, float* %q) { 43263320Sdim %r1 = load i32* %p 44263320Sdim@@ -279,7 +279,7 @@ define { i32, float } @ret_i32_float_pair(i32 %a0, 45263320Sdim ; CHECK: call_ret_i32_float_pair 46263320Sdim ; CHECK: call ret_i32_float_pair 47263320Sdim ; CHECK: st %o0, [%i0] 48263320Sdim-; CHECK: st %f3, [%i1] 49263320Sdim+; CHECK: st %f2, [%i1] 50263320Sdim define void @call_ret_i32_float_pair(i32* %i0, float* %i1) { 51263320Sdim %rv = call { i32, float } @ret_i32_float_pair(i32 undef, i32 undef, 52263320Sdim i32* undef, float* undef) 53263320SdimIndex: test/CodeGen/SPARC/constpool.ll 54263320Sdim=================================================================== 55263320Sdim--- test/CodeGen/SPARC/constpool.ll 56263320Sdim+++ test/CodeGen/SPARC/constpool.ll 57263320Sdim@@ -21,7 +21,7 @@ entry: 58263320Sdim ; abs44: add %[[R1]], %m44(.LCPI0_0), %[[R2:[gilo][0-7]]] 59263320Sdim ; abs44: sllx %[[R2]], 12, %[[R3:[gilo][0-7]]] 60263320Sdim ; abs44: retl 61263320Sdim-; abs44: ld [%[[R3]]+%l44(.LCPI0_0)], %f1 62263320Sdim+; abs44: ld [%[[R3]]+%l44(.LCPI0_0)], %f0 63263320Sdim 64263320Sdim 65263320Sdim ; abs64: floatCP 66263320Sdim@@ -31,7 +31,7 @@ entry: 67263320Sdim ; abs64: add %[[R3]], %hm(.LCPI0_0), %[[R4:[gilo][0-7]]] 68263320Sdim ; abs64: sllx %[[R4]], 32, %[[R5:[gilo][0-7]]] 69263320Sdim ; abs64: retl 70263320Sdim-; abs64: ld [%[[R5]]+%[[R2]]], %f1 71263320Sdim+; abs64: ld [%[[R5]]+%[[R2]]], %f0 72263320Sdim 73263320Sdim 74263320Sdim ; v8pic32: floatCP 75263320Sdim@@ -50,7 +50,7 @@ entry: 76263320Sdim ; v9pic32: sethi %hi(.LCPI0_0), %[[R1:[gilo][0-7]]] 77263320Sdim ; v9pic32: add %[[R1]], %lo(.LCPI0_0), %[[Goffs:[gilo][0-7]]] 78263320Sdim ; v9pic32: ldx [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]] 79263320Sdim-; v9pic32: ld [%[[Gaddr]]], %f1 80263320Sdim+; v9pic32: ld [%[[Gaddr]]], %f0 81263320Sdim ; v9pic32: ret 82263320Sdim ; v9pic32: restore 83263320Sdim 84263320SdimIndex: test/CodeGen/SPARC/64cond.ll 85263320Sdim=================================================================== 86263320Sdim--- test/CodeGen/SPARC/64cond.ll 87263320Sdim+++ test/CodeGen/SPARC/64cond.ll 88263320Sdim@@ -80,7 +80,7 @@ entry: 89263320Sdim ; CHECK: selectf32_xcc 90263320Sdim ; CHECK: cmp %i0, %i1 91263320Sdim ; CHECK: fmovsg %xcc, %f5, %f7 92263320Sdim-; CHECK: fmovs %f7, %f1 93263320Sdim+; CHECK: fmovs %f7, %f0 94263320Sdim define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) { 95263320Sdim entry: 96263320Sdim %tobool = icmp sgt i64 %x, %y 97263320SdimIndex: lib/Target/Sparc/SparcISelLowering.cpp 98263320Sdim=================================================================== 99263320Sdim--- lib/Target/Sparc/SparcISelLowering.cpp 100263320Sdim+++ lib/Target/Sparc/SparcISelLowering.cpp 101263320Sdim@@ -254,7 +254,7 @@ SparcTargetLowering::LowerReturn_64(SDValue Chain, 102263320Sdim DAG.getTarget(), RVLocs, *DAG.getContext()); 103263320Sdim 104263320Sdim // Analyze return values. 105263320Sdim- CCInfo.AnalyzeReturn(Outs, CC_Sparc64); 106263320Sdim+ CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64); 107263320Sdim 108263320Sdim SDValue Flag; 109263320Sdim SmallVector<SDValue, 4> RetOps(1, Chain); 110263320Sdim@@ -1258,7 +1258,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering:: 111263320Sdim if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == 0) 112263320Sdim CLI.Ins[0].Flags.setInReg(); 113263320Sdim 114263320Sdim- RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64); 115263320Sdim+ RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64); 116263320Sdim 117263320Sdim // Copy all of the result registers out of their specified physreg. 118263320Sdim for (unsigned i = 0; i != RVLocs.size(); ++i) { 119263320SdimIndex: lib/Target/Sparc/SparcCallingConv.td 120263320Sdim=================================================================== 121263320Sdim--- lib/Target/Sparc/SparcCallingConv.td 122263320Sdim+++ lib/Target/Sparc/SparcCallingConv.td 123263320Sdim@@ -103,7 +103,7 @@ def RetCC_Sparc32 : CallingConv<[ 124263320Sdim // Function return values are passed exactly like function arguments, except a 125263320Sdim // struct up to 32 bytes in size can be returned in registers. 126263320Sdim 127263320Sdim-// Function arguments AND return values. 128263320Sdim+// Function arguments AND most return values. 129263320Sdim def CC_Sparc64 : CallingConv<[ 130263320Sdim // The frontend uses the inreg flag to indicate i32 and float arguments from 131263320Sdim // structs. These arguments are not promoted to 64 bits, but they can still 132263320Sdim@@ -118,6 +118,15 @@ def CC_Sparc64 : CallingConv<[ 133263320Sdim CCCustom<"CC_Sparc64_Full"> 134263320Sdim ]>; 135263320Sdim 136263320Sdim+def RetCC_Sparc64 : CallingConv<[ 137263320Sdim+ // A single f32 return value always goes in %f0. The ABI doesn't specify what 138263320Sdim+ // happens to multiple f32 return values outside a struct. 139263320Sdim+ CCIfType<[f32], CCCustom<"CC_Sparc64_Half">>, 140263320Sdim+ 141263320Sdim+ // Otherwise, return values are passed exactly like arguments. 142263320Sdim+ CCDelegateTo<CC_Sparc64> 143263320Sdim+]>; 144263320Sdim+ 145263320Sdim // Callee-saved registers are handled by the register window mechanism. 146263320Sdim def CSR : CalleeSavedRegs<(add)> { 147263320Sdim let OtherPreserved = (add (sequence "I%u", 0, 7), 148