1263320SdimPull in r198910 from upstream llvm trunk (by Venkatraman Govindaraju): 2263320Sdim 3263320Sdim [Sparc] Emit retl/ret instead of jmp instruction. It improves the readability of the assembly generated. 4263320Sdim 5269012SemasteIntroduced here: http://svnweb.freebsd.org/changeset/base/262261 6263320Sdim 7263320SdimIndex: test/CodeGen/SPARC/ctpop.ll 8263320Sdim=================================================================== 9263320Sdim--- test/CodeGen/SPARC/ctpop.ll 10263320Sdim+++ test/CodeGen/SPARC/ctpop.ll 11263320Sdim@@ -9,12 +9,12 @@ declare i32 @llvm.ctpop.i32(i32) 12263320Sdim 13263320Sdim ; V9-LABEL: test 14263320Sdim ; V9: srl %o0, 0, %o0 15263320Sdim-; V9-NEXT: jmp %o7+8 16263320Sdim+; V9-NEXT: retl 17263320Sdim ; V9-NEXT: popc %o0, %o0 18263320Sdim 19263320Sdim ; SPARC64-LABEL: test 20263320Sdim ; SPARC64: srl %o0, 0, %o0 21263320Sdim-; SPARC64: jmp %o7+8 22263320Sdim+; SPARC64: retl 23263320Sdim ; SPARC64: popc %o0, %o0 24263320Sdim 25263320Sdim define i32 @test(i32 %X) { 26263320SdimIndex: test/CodeGen/SPARC/2011-01-11-Call.ll 27263320Sdim=================================================================== 28263320Sdim--- test/CodeGen/SPARC/2011-01-11-Call.ll 29263320Sdim+++ test/CodeGen/SPARC/2011-01-11-Call.ll 30263320Sdim@@ -8,7 +8,7 @@ 31263320Sdim ; V8-NEXT: nop 32263320Sdim ; V8: call bar 33263320Sdim ; V8-NEXT: nop 34263320Sdim-; V8: jmp %i7+8 35263320Sdim+; V8: ret 36263320Sdim ; V8-NEXT: restore 37263320Sdim 38263320Sdim ; V9-LABEL: test 39263320Sdim@@ -17,7 +17,7 @@ 40263320Sdim ; V9-NEXT: nop 41263320Sdim ; V9: call bar 42263320Sdim ; V9-NEXT: nop 43263320Sdim-; V9: jmp %i7+8 44263320Sdim+; V9: ret 45263320Sdim ; V9-NEXT: restore 46263320Sdim 47263320Sdim define void @test() nounwind { 48263320Sdim@@ -36,7 +36,7 @@ declare void @bar(...) 49263320Sdim ; V8: save %sp 50263320Sdim ; V8: call foo 51263320Sdim ; V8-NEXT: nop 52263320Sdim-; V8: jmp %i7+8 53263320Sdim+; V8: ret 54263320Sdim ; V8-NEXT: restore %g0, %o0, %o0 55263320Sdim 56263320Sdim ; V9-LABEL: test_tail_call_with_return 57263320Sdim@@ -43,7 +43,7 @@ declare void @bar(...) 58263320Sdim ; V9: save %sp 59263320Sdim ; V9: call foo 60263320Sdim ; V9-NEXT: nop 61263320Sdim-; V9: jmp %i7+8 62263320Sdim+; V9: ret 63263320Sdim ; V9-NEXT: restore %g0, %o0, %o0 64263320Sdim 65263320Sdim define i32 @test_tail_call_with_return() nounwind { 66263320SdimIndex: test/CodeGen/SPARC/leafproc.ll 67263320Sdim=================================================================== 68263320Sdim--- test/CodeGen/SPARC/leafproc.ll 69263320Sdim+++ test/CodeGen/SPARC/leafproc.ll 70263320Sdim@@ -1,7 +1,7 @@ 71263320Sdim ; RUN: llc -march=sparc -disable-sparc-leaf-proc=0 < %s | FileCheck %s 72263320Sdim 73263320Sdim ; CHECK-LABEL: func_nobody: 74263320Sdim-; CHECK: jmp %o7+8 75263320Sdim+; CHECK: retl 76263320Sdim ; CHECK-NEXT: nop 77263320Sdim define void @func_nobody() { 78263320Sdim entry: 79263320Sdim@@ -10,7 +10,7 @@ entry: 80263320Sdim 81263320Sdim 82263320Sdim ; CHECK-LABEL: return_int_const: 83263320Sdim-; CHECK: jmp %o7+8 84263320Sdim+; CHECK: retl 85263320Sdim ; CHECK-NEXT: or %g0, 1729, %o0 86263320Sdim define i32 @return_int_const() { 87263320Sdim entry: 88263320Sdim@@ -19,7 +19,7 @@ entry: 89263320Sdim 90263320Sdim ; CHECK-LABEL: return_double_const: 91263320Sdim ; CHECK: sethi 92263320Sdim-; CHECK: jmp %o7+8 93263320Sdim+; CHECK: retl 94263320Sdim ; CHECK-NEXT: ldd {{.*}}, %f0 95263320Sdim 96263320Sdim define double @return_double_const() { 97263320Sdim@@ -29,7 +29,7 @@ entry: 98263320Sdim 99263320Sdim ; CHECK-LABEL: leaf_proc_with_args: 100263320Sdim ; CHECK: add {{%o[0-1]}}, {{%o[0-1]}}, [[R:%[go][0-7]]] 101263320Sdim-; CHECK: jmp %o7+8 102263320Sdim+; CHECK: retl 103263320Sdim ; CHECK-NEXT: add [[R]], %o2, %o0 104263320Sdim 105263320Sdim define i32 @leaf_proc_with_args(i32 %a, i32 %b, i32 %c) { 106263320Sdim@@ -42,7 +42,7 @@ entry: 107263320Sdim ; CHECK-LABEL: leaf_proc_with_args_in_stack: 108263320Sdim ; CHECK-DAG: ld [%sp+92], {{%[go][0-7]}} 109263320Sdim ; CHECK-DAG: ld [%sp+96], {{%[go][0-7]}} 110263320Sdim-; CHECK: jmp %o7+8 111263320Sdim+; CHECK: retl 112263320Sdim ; CHECK-NEXT: add {{.*}}, %o0 113263320Sdim define i32 @leaf_proc_with_args_in_stack(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) { 114263320Sdim entry: 115263320Sdim@@ -63,7 +63,7 @@ entry: 116263320Sdim ; CHECK: or %g0, 2, [[R2:%[go][0-7]]] 117263320Sdim ; CHECK: st [[R2]], [%sp+100] 118263320Sdim ; CHECK: ld {{.+}}, %o0 119263320Sdim-; CHECK: jmp %o7+8 120263320Sdim+; CHECK: retl 121263320Sdim ; CHECK-NEXT: add %sp, 104, %sp 122263320Sdim 123263320Sdim define i32 @leaf_proc_with_local_array(i32 %a, i32 %b, i32 %c) { 124263320SdimIndex: test/CodeGen/SPARC/fp128.ll 125263320Sdim=================================================================== 126263320Sdim--- test/CodeGen/SPARC/fp128.ll 127263320Sdim+++ test/CodeGen/SPARC/fp128.ll 128263320Sdim@@ -45,7 +45,7 @@ entry: 129263320Sdim ; HARD: std %f{{.+}}, [%[[S1:.+]]] 130263320Sdim ; HARD-DAG: ldd [%[[S0]]], %f{{.+}} 131263320Sdim ; HARD-DAG: ldd [%[[S1]]], %f{{.+}} 132263320Sdim-; HARD: jmp 133263320Sdim+; HARD: jmp %o7+12 134263320Sdim 135263320Sdim ; SOFT-LABEL: f128_spill 136263320Sdim ; SOFT: std %f{{.+}}, [%[[S0:.+]]] 137263320Sdim@@ -52,7 +52,7 @@ entry: 138263320Sdim ; SOFT: std %f{{.+}}, [%[[S1:.+]]] 139263320Sdim ; SOFT-DAG: ldd [%[[S0]]], %f{{.+}} 140263320Sdim ; SOFT-DAG: ldd [%[[S1]]], %f{{.+}} 141263320Sdim-; SOFT: jmp 142263320Sdim+; SOFT: jmp %o7+12 143263320Sdim 144263320Sdim define void @f128_spill(fp128* noalias sret %scalar.result, fp128* byval %a) { 145263320Sdim entry: 146263320Sdim@@ -132,13 +132,13 @@ entry: 147263320Sdim ; HARD: ldub 148263320Sdim ; HARD: faddq 149263320Sdim ; HARD: stb 150263320Sdim-; HARD: jmp 151263320Sdim+; HARD: ret 152263320Sdim 153263320Sdim ; SOFT-LABEL: fp128_unaligned 154263320Sdim ; SOFT: ldub 155263320Sdim ; SOFT: call _Q_add 156263320Sdim ; SOFT: stb 157263320Sdim-; SOFT: jmp 158263320Sdim+; SOFT: ret 159263320Sdim 160263320Sdim define void @fp128_unaligned(fp128* %a, fp128* %b, fp128* %c) { 161263320Sdim entry: 162263320SdimIndex: test/CodeGen/SPARC/2011-01-11-FrameAddr.ll 163263320Sdim=================================================================== 164263320Sdim--- test/CodeGen/SPARC/2011-01-11-FrameAddr.ll 165263320Sdim+++ test/CodeGen/SPARC/2011-01-11-FrameAddr.ll 166263320Sdim@@ -9,18 +9,18 @@ define i8* @frameaddr() nounwind readnone { 167263320Sdim entry: 168263320Sdim ;V8-LABEL: frameaddr: 169263320Sdim ;V8: save %sp, -96, %sp 170263320Sdim-;V8: jmp %i7+8 171263320Sdim+;V8: ret 172263320Sdim ;V8: restore %g0, %fp, %o0 173263320Sdim 174263320Sdim ;V9-LABEL: frameaddr: 175263320Sdim ;V9: save %sp, -96, %sp 176263320Sdim-;V9: jmp %i7+8 177263320Sdim+;V9: ret 178263320Sdim ;V9: restore %g0, %fp, %o0 179263320Sdim 180263320Sdim ;SPARC64-LABEL: frameaddr 181263320Sdim ;SPARC64: save %sp, -128, %sp 182263320Sdim ;SPARC64: add %fp, 2047, %i0 183263320Sdim-;SPARC64: jmp %i7+8 184263320Sdim+;SPARC64: ret 185263320Sdim ;SPARC64: restore %g0, %g0, %g0 186263320Sdim 187263320Sdim %0 = tail call i8* @llvm.frameaddress(i32 0) 188263320SdimIndex: test/CodeGen/SPARC/constpool.ll 189263320Sdim=================================================================== 190263320Sdim--- test/CodeGen/SPARC/constpool.ll 191263320Sdim+++ test/CodeGen/SPARC/constpool.ll 192263320Sdim@@ -12,7 +12,7 @@ entry: 193263320Sdim 194263320Sdim ; abs32: floatCP 195263320Sdim ; abs32: sethi %hi(.LCPI0_0), %[[R:[gilo][0-7]]] 196263320Sdim-; abs32: jmp %o7+8 197263320Sdim+; abs32: retl 198263320Sdim ; abs32: ld [%[[R]]+%lo(.LCPI0_0)], %f 199263320Sdim 200263320Sdim 201263320Sdim@@ -20,7 +20,7 @@ entry: 202263320Sdim ; abs44: sethi %h44(.LCPI0_0), %[[R1:[gilo][0-7]]] 203263320Sdim ; abs44: add %[[R1]], %m44(.LCPI0_0), %[[R2:[gilo][0-7]]] 204263320Sdim ; abs44: sllx %[[R2]], 12, %[[R3:[gilo][0-7]]] 205263320Sdim-; abs44: jmp %o7+8 206263320Sdim+; abs44: retl 207263320Sdim ; abs44: ld [%[[R3]]+%l44(.LCPI0_0)], %f1 208263320Sdim 209263320Sdim 210263320Sdim@@ -30,7 +30,7 @@ entry: 211263320Sdim ; abs64: sethi %hh(.LCPI0_0), %[[R3:[gilo][0-7]]] 212263320Sdim ; abs64: add %[[R3]], %hm(.LCPI0_0), %[[R4:[gilo][0-7]]] 213263320Sdim ; abs64: sllx %[[R4]], 32, %[[R5:[gilo][0-7]]] 214263320Sdim-; abs64: jmp %o7+8 215263320Sdim+; abs64: retl 216263320Sdim ; abs64: ld [%[[R5]]+%[[R2]]], %f1 217263320Sdim 218263320Sdim 219263320Sdim@@ -40,7 +40,7 @@ entry: 220263320Sdim ; v8pic32: add %[[R1]], %lo(.LCPI0_0), %[[Goffs:[gilo][0-7]]] 221263320Sdim ; v8pic32: ld [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]] 222263320Sdim ; v8pic32: ld [%[[Gaddr]]], %f0 223263320Sdim-; v8pic32: jmp %i7+8 224263320Sdim+; v8pic32: ret 225263320Sdim ; v8pic32: restore 226263320Sdim 227263320Sdim 228263320Sdim@@ -51,7 +51,7 @@ entry: 229263320Sdim ; v9pic32: add %[[R1]], %lo(.LCPI0_0), %[[Goffs:[gilo][0-7]]] 230263320Sdim ; v9pic32: ldx [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]] 231263320Sdim ; v9pic32: ld [%[[Gaddr]]], %f1 232263320Sdim-; v9pic32: jmp %i7+8 233263320Sdim+; v9pic32: ret 234263320Sdim ; v9pic32: restore 235263320Sdim 236263320Sdim 237263320SdimIndex: test/CodeGen/SPARC/globals.ll 238263320Sdim=================================================================== 239263320Sdim--- test/CodeGen/SPARC/globals.ll 240263320Sdim+++ test/CodeGen/SPARC/globals.ll 241263320Sdim@@ -14,7 +14,7 @@ define zeroext i8 @loadG() { 242263320Sdim 243263320Sdim ; abs32: loadG 244263320Sdim ; abs32: sethi %hi(G), %[[R:[gilo][0-7]]] 245263320Sdim-; abs32: jmp %o7+8 246263320Sdim+; abs32: retl 247263320Sdim ; abs32: ldub [%[[R]]+%lo(G)], %o0 248263320Sdim 249263320Sdim 250263320Sdim@@ -22,7 +22,7 @@ define zeroext i8 @loadG() { 251263320Sdim ; abs44: sethi %h44(G), %[[R1:[gilo][0-7]]] 252263320Sdim ; abs44: add %[[R1]], %m44(G), %[[R2:[gilo][0-7]]] 253263320Sdim ; abs44: sllx %[[R2]], 12, %[[R3:[gilo][0-7]]] 254263320Sdim-; abs44: jmp %o7+8 255263320Sdim+; abs44: retl 256263320Sdim ; abs44: ldub [%[[R3]]+%l44(G)], %o0 257263320Sdim 258263320Sdim 259263320Sdim@@ -32,7 +32,7 @@ define zeroext i8 @loadG() { 260263320Sdim ; abs64: sethi %hh(G), %[[R3:[gilo][0-7]]] 261263320Sdim ; abs64: add %[[R3]], %hm(G), %[[R4:[gilo][0-7]]] 262263320Sdim ; abs64: sllx %[[R4]], 32, %[[R5:[gilo][0-7]]] 263263320Sdim-; abs64: jmp %o7+8 264263320Sdim+; abs64: retl 265263320Sdim ; abs64: ldub [%[[R5]]+%[[R2]]], %o0 266263320Sdim 267263320Sdim 268263320Sdim@@ -42,7 +42,7 @@ define zeroext i8 @loadG() { 269263320Sdim ; v8pic32: add %[[R1]], %lo(G), %[[Goffs:[gilo][0-7]]] 270263320Sdim ; v8pic32: ld [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]] 271263320Sdim ; v8pic32: ldub [%[[Gaddr]]], %i0 272263320Sdim-; v8pic32: jmp %i7+8 273263320Sdim+; v8pic32: ret 274263320Sdim ; v8pic32: restore 275263320Sdim 276263320Sdim 277263320Sdim@@ -52,6 +52,6 @@ define zeroext i8 @loadG() { 278263320Sdim ; v9pic32: add %[[R1]], %lo(G), %[[Goffs:[gilo][0-7]]] 279263320Sdim ; v9pic32: ldx [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]] 280263320Sdim ; v9pic32: ldub [%[[Gaddr]]], %i0 281263320Sdim-; v9pic32: jmp %i7+8 282263320Sdim+; v9pic32: ret 283263320Sdim ; v9pic32: restore 284263320Sdim 285263320SdimIndex: test/CodeGen/SPARC/rem.ll 286263320Sdim=================================================================== 287263320Sdim--- test/CodeGen/SPARC/rem.ll 288263320Sdim+++ test/CodeGen/SPARC/rem.ll 289263320Sdim@@ -3,7 +3,7 @@ 290263320Sdim ; CHECK-LABEL: test1: 291263320Sdim ; CHECK: sdivx %o0, %o1, %o2 292263320Sdim ; CHECK-NEXT: mulx %o2, %o1, %o1 293263320Sdim-; CHECK-NEXT: jmp %o7+8 294263320Sdim+; CHECK-NEXT: retl 295263320Sdim ; CHECK-NEXT: sub %o0, %o1, %o0 296263320Sdim 297263320Sdim define i64 @test1(i64 %X, i64 %Y) { 298263320Sdim@@ -14,7 +14,7 @@ define i64 @test1(i64 %X, i64 %Y) { 299263320Sdim ; CHECK-LABEL: test2: 300263320Sdim ; CHECK: udivx %o0, %o1, %o2 301263320Sdim ; CHECK-NEXT: mulx %o2, %o1, %o1 302263320Sdim-; CHECK-NEXT: jmp %o7+8 303263320Sdim+; CHECK-NEXT: retl 304263320Sdim ; CHECK-NEXT: sub %o0, %o1, %o0 305263320Sdim 306263320Sdim define i64 @test2(i64 %X, i64 %Y) { 307263320SdimIndex: test/CodeGen/SPARC/2011-01-19-DelaySlot.ll 308263320Sdim=================================================================== 309263320Sdim--- test/CodeGen/SPARC/2011-01-19-DelaySlot.ll 310263320Sdim+++ test/CodeGen/SPARC/2011-01-19-DelaySlot.ll 311263320Sdim@@ -7,7 +7,7 @@ entry: 312263320Sdim ; CHECK: test 313263320Sdim ; CHECK: call bar 314263320Sdim ; CHECK-NOT: nop 315263320Sdim-; CHECK: jmp 316263320Sdim+; CHECK: ret 317263320Sdim ; CHECK-NEXT: restore 318263320Sdim %0 = tail call i32 @bar(i32 %a) nounwind 319263320Sdim ret i32 %0 320263320Sdim@@ -18,7 +18,7 @@ entry: 321263320Sdim ; CHECK: test_jmpl 322263320Sdim ; CHECK: call 323263320Sdim ; CHECK-NOT: nop 324263320Sdim-; CHECK: jmp 325263320Sdim+; CHECK: ret 326263320Sdim ; CHECK-NEXT: restore 327263320Sdim %0 = tail call i32 %f(i32 %a, i32 %b) nounwind 328263320Sdim ret i32 %0 329263320Sdim@@ -47,7 +47,7 @@ bb: 330263320Sdim 331263320Sdim bb5: ; preds = %bb, %entry 332263320Sdim %a_addr.1.lcssa = phi i32 [ %a, %entry ], [ %a_addr.0, %bb ] 333263320Sdim-;CHECK: jmp 334263320Sdim+;CHECK: retl 335263320Sdim ;CHECK-NOT: restore 336263320Sdim ret i32 %a_addr.1.lcssa 337263320Sdim } 338263320Sdim@@ -110,7 +110,7 @@ declare i32 @func(i32*) 339263320Sdim define i32 @restore_add(i32 %a, i32 %b) { 340263320Sdim entry: 341263320Sdim ;CHECK-LABEL: restore_add: 342263320Sdim-;CHECK: jmp %i7+8 343263320Sdim+;CHECK: ret 344263320Sdim ;CHECK: restore %o0, %i1, %o0 345263320Sdim %0 = tail call i32 @bar(i32 %a) nounwind 346263320Sdim %1 = add nsw i32 %0, %b 347263320Sdim@@ -120,7 +120,7 @@ entry: 348263320Sdim define i32 @restore_add_imm(i32 %a) { 349263320Sdim entry: 350263320Sdim ;CHECK-LABEL: restore_add_imm: 351263320Sdim-;CHECK: jmp %i7+8 352263320Sdim+;CHECK: ret 353263320Sdim ;CHECK: restore %o0, 20, %o0 354263320Sdim %0 = tail call i32 @bar(i32 %a) nounwind 355263320Sdim %1 = add nsw i32 %0, 20 356263320Sdim@@ -130,7 +130,7 @@ entry: 357263320Sdim define i32 @restore_or(i32 %a) { 358263320Sdim entry: 359263320Sdim ;CHECK-LABEL: restore_or: 360263320Sdim-;CHECK: jmp %i7+8 361263320Sdim+;CHECK: ret 362263320Sdim ;CHECK: restore %g0, %o0, %o0 363263320Sdim %0 = tail call i32 @bar(i32 %a) nounwind 364263320Sdim ret i32 %0 365263320Sdim@@ -140,7 +140,7 @@ define i32 @restore_or_imm(i32 %a) { 366263320Sdim entry: 367263320Sdim ;CHECK-LABEL: restore_or_imm: 368263320Sdim ;CHECK: or %o0, 20, %i0 369263320Sdim-;CHECK: jmp %i7+8 370263320Sdim+;CHECK: ret 371263320Sdim ;CHECK: restore %g0, %g0, %g0 372263320Sdim %0 = tail call i32 @bar(i32 %a) nounwind 373263320Sdim %1 = or i32 %0, 20 374263320SdimIndex: test/CodeGen/SPARC/64bit.ll 375263320Sdim=================================================================== 376263320Sdim--- test/CodeGen/SPARC/64bit.ll 377263320Sdim+++ test/CodeGen/SPARC/64bit.ll 378263320Sdim@@ -5,7 +5,7 @@ 379263320Sdim ; CHECK: or %g0, %i1, %i0 380263320Sdim 381263320Sdim ; OPT-LABEL: ret2: 382263320Sdim-; OPT: jmp %o7+8 383263320Sdim+; OPT: retl 384263320Sdim ; OPT: or %g0, %o1, %o0 385263320Sdim define i64 @ret2(i64 %a, i64 %b) { 386263320Sdim ret i64 %b 387263320Sdim@@ -15,7 +15,7 @@ define i64 @ret2(i64 %a, i64 %b) { 388263320Sdim ; CHECK: sllx %i0, 7, %i0 389263320Sdim 390263320Sdim ; OPT-LABEL: shl_imm: 391263320Sdim-; OPT: jmp %o7+8 392263320Sdim+; OPT: retl 393263320Sdim ; OPT: sllx %o0, 7, %o0 394263320Sdim define i64 @shl_imm(i64 %a) { 395263320Sdim %x = shl i64 %a, 7 396263320Sdim@@ -26,7 +26,7 @@ define i64 @shl_imm(i64 %a) { 397263320Sdim ; CHECK: srax %i0, %i1, %i0 398263320Sdim 399263320Sdim ; OPT-LABEL: sra_reg: 400263320Sdim-; OPT: jmp %o7+8 401263320Sdim+; OPT: retl 402263320Sdim ; OPT: srax %o0, %o1, %o0 403263320Sdim define i64 @sra_reg(i64 %a, i64 %b) { 404263320Sdim %x = ashr i64 %a, %b 405263320Sdim@@ -42,7 +42,7 @@ define i64 @sra_reg(i64 %a, i64 %b) { 406263320Sdim ; CHECK: or %g0, 0, %i0 407263320Sdim 408263320Sdim ; OPT: ret_imm0 409263320Sdim-; OPT: jmp %o7+8 410263320Sdim+; OPT: retl 411263320Sdim ; OPT: or %g0, 0, %o0 412263320Sdim define i64 @ret_imm0() { 413263320Sdim ret i64 0 414263320Sdim@@ -52,7 +52,7 @@ define i64 @ret_imm0() { 415263320Sdim ; CHECK: or %g0, -4096, %i0 416263320Sdim 417263320Sdim ; OPT: ret_simm13 418263320Sdim-; OPT: jmp %o7+8 419263320Sdim+; OPT: retl 420263320Sdim ; OPT: or %g0, -4096, %o0 421263320Sdim define i64 @ret_simm13() { 422263320Sdim ret i64 -4096 423263320Sdim@@ -64,7 +64,7 @@ define i64 @ret_simm13() { 424263320Sdim ; CHECK: restore 425263320Sdim 426263320Sdim ; OPT: ret_sethi 427263320Sdim-; OPT: jmp %o7+8 428263320Sdim+; OPT: retl 429263320Sdim ; OPT: sethi 4, %o0 430263320Sdim define i64 @ret_sethi() { 431263320Sdim ret i64 4096 432263320Sdim@@ -76,7 +76,7 @@ define i64 @ret_sethi() { 433263320Sdim 434263320Sdim ; OPT: ret_sethi_or 435263320Sdim ; OPT: sethi 4, [[R:%[go][0-7]]] 436263320Sdim-; OPT: jmp %o7+8 437263320Sdim+; OPT: retl 438263320Sdim ; OPT: or [[R]], 1, %o0 439263320Sdim 440263320Sdim define i64 @ret_sethi_or() { 441263320Sdim@@ -89,7 +89,7 @@ define i64 @ret_sethi_or() { 442263320Sdim 443263320Sdim ; OPT: ret_nimm33 444263320Sdim ; OPT: sethi 4, [[R:%[go][0-7]]] 445263320Sdim-; OPT: jmp %o7+8 446263320Sdim+; OPT: retl 447263320Sdim ; OPT: xor [[R]], -4, %o0 448263320Sdim 449263320Sdim define i64 @ret_nimm33() { 450263320SdimIndex: lib/Target/Sparc/SparcInstrAliases.td 451263320Sdim=================================================================== 452263320Sdim--- lib/Target/Sparc/SparcInstrAliases.td 453263320Sdim+++ lib/Target/Sparc/SparcInstrAliases.td 454263320Sdim@@ -128,3 +128,9 @@ def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$ad 455263320Sdim // call addr -> jmpl addr, %o7 456263320Sdim def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr)>; 457263320Sdim def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr)>; 458263320Sdim+ 459263320Sdim+// retl -> RETL 8 460263320Sdim+def : InstAlias<"retl", (RETL 8)>; 461263320Sdim+ 462263320Sdim+// ret -> RET 8 463263320Sdim+def : InstAlias<"ret", (RET 8)>; 464