1263320SdimPull in r198893 from upstream llvm trunk (by Venkatraman Govindaraju): 2263320Sdim 3263320Sdim [Sparc] Multiclass for loads/stores. No functionality change intended. 4263320Sdim 5269012SemasteIntroduced here: http://svnweb.freebsd.org/changeset/base/262261 6263320Sdim 7263320SdimIndex: lib/Target/Sparc/SparcInstr64Bit.td 8263320Sdim=================================================================== 9263320Sdim--- lib/Target/Sparc/SparcInstr64Bit.td 10263320Sdim+++ lib/Target/Sparc/SparcInstr64Bit.td 11263320Sdim@@ -235,14 +235,8 @@ def UDIVXri : F3_2<2, 0b001101, 12263320Sdim let Predicates = [Is64Bit] in { 13263320Sdim 14263320Sdim // 64-bit loads. 15263320Sdim-def LDXrr : F3_1<3, 0b001011, 16263320Sdim- (outs I64Regs:$dst), (ins MEMrr:$addr), 17263320Sdim- "ldx [$addr], $dst", 18263320Sdim- [(set i64:$dst, (load ADDRrr:$addr))]>; 19263320Sdim-def LDXri : F3_2<3, 0b001011, 20263320Sdim- (outs I64Regs:$dst), (ins MEMri:$addr), 21263320Sdim- "ldx [$addr], $dst", 22263320Sdim- [(set i64:$dst, (load ADDRri:$addr))]>; 23263320Sdim+defm LDX : Load<"ldx", 0b001011, load, I64Regs, i64>; 24263320Sdim+ 25263320Sdim let mayLoad = 1, isCodeGenOnly = 1, isAsmParserOnly = 1 in 26263320Sdim def TLS_LDXrr : F3_1<3, 0b001011, 27263320Sdim (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym), 28263320Sdim@@ -276,24 +270,10 @@ def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr 29263320Sdim def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 30263320Sdim 31263320Sdim // Sign-extending load of i32 into i64 is a new SPARC v9 instruction. 32263320Sdim-def LDSWrr : F3_1<3, 0b001000, 33263320Sdim- (outs I64Regs:$dst), (ins MEMrr:$addr), 34263320Sdim- "ldsw [$addr], $dst", 35263320Sdim- [(set i64:$dst, (sextloadi32 ADDRrr:$addr))]>; 36263320Sdim-def LDSWri : F3_2<3, 0b001000, 37263320Sdim- (outs I64Regs:$dst), (ins MEMri:$addr), 38263320Sdim- "ldsw [$addr], $dst", 39263320Sdim- [(set i64:$dst, (sextloadi32 ADDRri:$addr))]>; 40263320Sdim+defm LDSW : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>; 41263320Sdim 42263320Sdim // 64-bit stores. 43263320Sdim-def STXrr : F3_1<3, 0b001110, 44263320Sdim- (outs), (ins MEMrr:$addr, I64Regs:$rd), 45263320Sdim- "stx $rd, [$addr]", 46263320Sdim- [(store i64:$rd, ADDRrr:$addr)]>; 47263320Sdim-def STXri : F3_2<3, 0b001110, 48263320Sdim- (outs), (ins MEMri:$addr, I64Regs:$rd), 49263320Sdim- "stx $rd, [$addr]", 50263320Sdim- [(store i64:$rd, ADDRri:$addr)]>; 51263320Sdim+defm STX : Store<"stx", 0b001110, store, I64Regs, i64>; 52263320Sdim 53263320Sdim // Truncating stores from i64 are identical to the i32 stores. 54263320Sdim def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>; 55263320SdimIndex: lib/Target/Sparc/SparcInstrInfo.td 56263320Sdim=================================================================== 57263320Sdim--- lib/Target/Sparc/SparcInstrInfo.td 58263320Sdim+++ lib/Target/Sparc/SparcInstrInfo.td 59263320Sdim@@ -250,6 +250,32 @@ multiclass F3_12np<string OpcStr, bits<6> Op3Val> 60263320Sdim !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>; 61263320Sdim } 62263320Sdim 63263320Sdim+// Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. 64263320Sdim+multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, 65263320Sdim+ RegisterClass RC, ValueType Ty> { 66263320Sdim+ def rr : F3_1<3, Op3Val, 67263320Sdim+ (outs RC:$dst), (ins MEMrr:$addr), 68263320Sdim+ !strconcat(OpcStr, " [$addr], $dst"), 69263320Sdim+ [(set Ty:$dst, (OpNode ADDRrr:$addr))]>; 70263320Sdim+ def ri : F3_2<3, Op3Val, 71263320Sdim+ (outs RC:$dst), (ins MEMri:$addr), 72263320Sdim+ !strconcat(OpcStr, " [$addr], $dst"), 73263320Sdim+ [(set Ty:$dst, (OpNode ADDRri:$addr))]>; 74263320Sdim+} 75263320Sdim+ 76263320Sdim+// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. 77263320Sdim+multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, 78263320Sdim+ RegisterClass RC, ValueType Ty> { 79263320Sdim+ def rr : F3_1<3, Op3Val, 80263320Sdim+ (outs), (ins MEMrr:$addr, RC:$rd), 81263320Sdim+ !strconcat(OpcStr, " $rd, [$addr]"), 82263320Sdim+ [(OpNode Ty:$rd, ADDRrr:$addr)]>; 83263320Sdim+ def ri : F3_2<3, Op3Val, 84263320Sdim+ (outs), (ins MEMri:$addr, RC:$rd), 85263320Sdim+ !strconcat(OpcStr, " $rd, [$addr]"), 86263320Sdim+ [(OpNode Ty:$rd, ADDRri:$addr)]>; 87263320Sdim+} 88263320Sdim+ 89263320Sdim //===----------------------------------------------------------------------===// 90263320Sdim // Instructions 91263320Sdim //===----------------------------------------------------------------------===// 92263320Sdim@@ -350,128 +376,28 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 93263320Sdim } 94263320Sdim 95263320Sdim // Section B.1 - Load Integer Instructions, p. 90 96263320Sdim-def LDSBrr : F3_1<3, 0b001001, 97263320Sdim- (outs IntRegs:$dst), (ins MEMrr:$addr), 98263320Sdim- "ldsb [$addr], $dst", 99263320Sdim- [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>; 100263320Sdim-def LDSBri : F3_2<3, 0b001001, 101263320Sdim- (outs IntRegs:$dst), (ins MEMri:$addr), 102263320Sdim- "ldsb [$addr], $dst", 103263320Sdim- [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>; 104263320Sdim-def LDSHrr : F3_1<3, 0b001010, 105263320Sdim- (outs IntRegs:$dst), (ins MEMrr:$addr), 106263320Sdim- "ldsh [$addr], $dst", 107263320Sdim- [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>; 108263320Sdim-def LDSHri : F3_2<3, 0b001010, 109263320Sdim- (outs IntRegs:$dst), (ins MEMri:$addr), 110263320Sdim- "ldsh [$addr], $dst", 111263320Sdim- [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>; 112263320Sdim-def LDUBrr : F3_1<3, 0b000001, 113263320Sdim- (outs IntRegs:$dst), (ins MEMrr:$addr), 114263320Sdim- "ldub [$addr], $dst", 115263320Sdim- [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>; 116263320Sdim-def LDUBri : F3_2<3, 0b000001, 117263320Sdim- (outs IntRegs:$dst), (ins MEMri:$addr), 118263320Sdim- "ldub [$addr], $dst", 119263320Sdim- [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>; 120263320Sdim-def LDUHrr : F3_1<3, 0b000010, 121263320Sdim- (outs IntRegs:$dst), (ins MEMrr:$addr), 122263320Sdim- "lduh [$addr], $dst", 123263320Sdim- [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>; 124263320Sdim-def LDUHri : F3_2<3, 0b000010, 125263320Sdim- (outs IntRegs:$dst), (ins MEMri:$addr), 126263320Sdim- "lduh [$addr], $dst", 127263320Sdim- [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>; 128263320Sdim-def LDrr : F3_1<3, 0b000000, 129263320Sdim- (outs IntRegs:$dst), (ins MEMrr:$addr), 130263320Sdim- "ld [$addr], $dst", 131263320Sdim- [(set i32:$dst, (load ADDRrr:$addr))]>; 132263320Sdim-def LDri : F3_2<3, 0b000000, 133263320Sdim- (outs IntRegs:$dst), (ins MEMri:$addr), 134263320Sdim- "ld [$addr], $dst", 135263320Sdim- [(set i32:$dst, (load ADDRri:$addr))]>; 136263320Sdim+defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>; 137263320Sdim+defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>; 138263320Sdim+defm LDUB : Load<"ldub", 0b000001, zextloadi8, IntRegs, i32>; 139263320Sdim+defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>; 140263320Sdim+defm LD : Load<"ld", 0b000000, load, IntRegs, i32>; 141263320Sdim 142263320Sdim // Section B.2 - Load Floating-point Instructions, p. 92 143263320Sdim-def LDFrr : F3_1<3, 0b100000, 144263320Sdim- (outs FPRegs:$dst), (ins MEMrr:$addr), 145263320Sdim- "ld [$addr], $dst", 146263320Sdim- [(set f32:$dst, (load ADDRrr:$addr))]>; 147263320Sdim-def LDFri : F3_2<3, 0b100000, 148263320Sdim- (outs FPRegs:$dst), (ins MEMri:$addr), 149263320Sdim- "ld [$addr], $dst", 150263320Sdim- [(set f32:$dst, (load ADDRri:$addr))]>; 151263320Sdim-def LDDFrr : F3_1<3, 0b100011, 152263320Sdim- (outs DFPRegs:$dst), (ins MEMrr:$addr), 153263320Sdim- "ldd [$addr], $dst", 154263320Sdim- [(set f64:$dst, (load ADDRrr:$addr))]>; 155263320Sdim-def LDDFri : F3_2<3, 0b100011, 156263320Sdim- (outs DFPRegs:$dst), (ins MEMri:$addr), 157263320Sdim- "ldd [$addr], $dst", 158263320Sdim- [(set f64:$dst, (load ADDRri:$addr))]>; 159263320Sdim-def LDQFrr : F3_1<3, 0b100010, 160263320Sdim- (outs QFPRegs:$dst), (ins MEMrr:$addr), 161263320Sdim- "ldq [$addr], $dst", 162263320Sdim- [(set f128:$dst, (load ADDRrr:$addr))]>, 163263320Sdim- Requires<[HasV9, HasHardQuad]>; 164263320Sdim-def LDQFri : F3_2<3, 0b100010, 165263320Sdim- (outs QFPRegs:$dst), (ins MEMri:$addr), 166263320Sdim- "ldq [$addr], $dst", 167263320Sdim- [(set f128:$dst, (load ADDRri:$addr))]>, 168263320Sdim- Requires<[HasV9, HasHardQuad]>; 169263320Sdim+defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>; 170263320Sdim+defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>; 171263320Sdim+defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>, 172263320Sdim+ Requires<[HasV9, HasHardQuad]>; 173263320Sdim 174263320Sdim // Section B.4 - Store Integer Instructions, p. 95 175263320Sdim-def STBrr : F3_1<3, 0b000101, 176263320Sdim- (outs), (ins MEMrr:$addr, IntRegs:$rd), 177263320Sdim- "stb $rd, [$addr]", 178263320Sdim- [(truncstorei8 i32:$rd, ADDRrr:$addr)]>; 179263320Sdim-def STBri : F3_2<3, 0b000101, 180263320Sdim- (outs), (ins MEMri:$addr, IntRegs:$rd), 181263320Sdim- "stb $rd, [$addr]", 182263320Sdim- [(truncstorei8 i32:$rd, ADDRri:$addr)]>; 183263320Sdim-def STHrr : F3_1<3, 0b000110, 184263320Sdim- (outs), (ins MEMrr:$addr, IntRegs:$rd), 185263320Sdim- "sth $rd, [$addr]", 186263320Sdim- [(truncstorei16 i32:$rd, ADDRrr:$addr)]>; 187263320Sdim-def STHri : F3_2<3, 0b000110, 188263320Sdim- (outs), (ins MEMri:$addr, IntRegs:$rd), 189263320Sdim- "sth $rd, [$addr]", 190263320Sdim- [(truncstorei16 i32:$rd, ADDRri:$addr)]>; 191263320Sdim-def STrr : F3_1<3, 0b000100, 192263320Sdim- (outs), (ins MEMrr:$addr, IntRegs:$rd), 193263320Sdim- "st $rd, [$addr]", 194263320Sdim- [(store i32:$rd, ADDRrr:$addr)]>; 195263320Sdim-def STri : F3_2<3, 0b000100, 196263320Sdim- (outs), (ins MEMri:$addr, IntRegs:$rd), 197263320Sdim- "st $rd, [$addr]", 198263320Sdim- [(store i32:$rd, ADDRri:$addr)]>; 199263320Sdim+defm STB : Store<"stb", 0b000101, truncstorei8, IntRegs, i32>; 200263320Sdim+defm STH : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>; 201263320Sdim+defm ST : Store<"st", 0b000100, store, IntRegs, i32>; 202263320Sdim 203263320Sdim // Section B.5 - Store Floating-point Instructions, p. 97 204263320Sdim-def STFrr : F3_1<3, 0b100100, 205263320Sdim- (outs), (ins MEMrr:$addr, FPRegs:$rd), 206263320Sdim- "st $rd, [$addr]", 207263320Sdim- [(store f32:$rd, ADDRrr:$addr)]>; 208263320Sdim-def STFri : F3_2<3, 0b100100, 209263320Sdim- (outs), (ins MEMri:$addr, FPRegs:$rd), 210263320Sdim- "st $rd, [$addr]", 211263320Sdim- [(store f32:$rd, ADDRri:$addr)]>; 212263320Sdim-def STDFrr : F3_1<3, 0b100111, 213263320Sdim- (outs), (ins MEMrr:$addr, DFPRegs:$rd), 214263320Sdim- "std $rd, [$addr]", 215263320Sdim- [(store f64:$rd, ADDRrr:$addr)]>; 216263320Sdim-def STDFri : F3_2<3, 0b100111, 217263320Sdim- (outs), (ins MEMri:$addr, DFPRegs:$rd), 218263320Sdim- "std $rd, [$addr]", 219263320Sdim- [(store f64:$rd, ADDRri:$addr)]>; 220263320Sdim-def STQFrr : F3_1<3, 0b100110, 221263320Sdim- (outs), (ins MEMrr:$addr, QFPRegs:$rd), 222263320Sdim- "stq $rd, [$addr]", 223263320Sdim- [(store f128:$rd, ADDRrr:$addr)]>, 224263320Sdim- Requires<[HasV9, HasHardQuad]>; 225263320Sdim-def STQFri : F3_2<3, 0b100110, 226263320Sdim- (outs), (ins MEMri:$addr, QFPRegs:$rd), 227263320Sdim- "stq $rd, [$addr]", 228263320Sdim- [(store f128:$rd, ADDRri:$addr)]>, 229263320Sdim- Requires<[HasV9, HasHardQuad]>; 230263320Sdim+defm STF : Store<"st", 0b100100, store, FPRegs, f32>; 231263320Sdim+defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>; 232263320Sdim+defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>, 233263320Sdim+ Requires<[HasV9, HasHardQuad]>; 234263320Sdim 235263320Sdim // Section B.9 - SETHI Instruction, p. 104 236263320Sdim def SETHIi: F2_1<0b100, 237