1263320SdimPull in r198740 from upstream llvm trunk (by Venkatraman Govindaraju): 2263320Sdim 3263320Sdim [SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly. 4263320Sdim 5269012SemasteIntroduced here: http://svnweb.freebsd.org/changeset/base/262261 6263320Sdim 7263320SdimIndex: test/MC/Sparc/sparc64-alu-instructions.s 8263320Sdim=================================================================== 9263320Sdim--- test/MC/Sparc/sparc64-alu-instructions.s 10263320Sdim+++ test/MC/Sparc/sparc64-alu-instructions.s 11263320Sdim@@ -0,0 +1,38 @@ 12263320Sdim+! RUN: llvm-mc %s -triple=sparc64-unknown-linux-gnu -show-encoding | FileCheck %s 13263320Sdim+ 14263320Sdim+ ! CHECK: sllx %g1, %i2, %i0 ! encoding: [0xb1,0x28,0x50,0x1a] 15263320Sdim+ sllx %g1, %i2, %i0 16263320Sdim+ 17263320Sdim+ ! CHECK: sllx %g1, 63, %i0 ! encoding: [0xb1,0x28,0x70,0x3f] 18263320Sdim+ sllx %g1, 63, %i0 19263320Sdim+ 20263320Sdim+ ! CHECK: srlx %g1, %i2, %i0 ! encoding: [0xb1,0x30,0x50,0x1a] 21263320Sdim+ srlx %g1, %i2, %i0 22263320Sdim+ 23263320Sdim+ ! CHECK: srlx %g1, 63, %i0 ! encoding: [0xb1,0x30,0x70,0x3f] 24263320Sdim+ srlx %g1, 63, %i0 25263320Sdim+ 26263320Sdim+ ! CHECK: srax %g1, %i2, %i0 ! encoding: [0xb1,0x38,0x50,0x1a] 27263320Sdim+ srax %g1, %i2, %i0 28263320Sdim+ 29263320Sdim+ ! CHECK: srax %g1, 63, %i0 ! encoding: [0xb1,0x38,0x70,0x3f] 30263320Sdim+ srax %g1, 63, %i0 31263320Sdim+ 32263320Sdim+ ! CHECK: mulx %g1, %i2, %i0 ! encoding: [0xb0,0x48,0x40,0x1a] 33263320Sdim+ mulx %g1, %i2, %i0 34263320Sdim+ 35263320Sdim+ ! CHECK: mulx %g1, 63, %i0 ! encoding: [0xb0,0x48,0x60,0x3f] 36263320Sdim+ mulx %g1, 63, %i0 37263320Sdim+ 38263320Sdim+ ! CHECK: sdivx %g1, %i2, %i0 ! encoding: [0xb1,0x68,0x40,0x1a] 39263320Sdim+ sdivx %g1, %i2, %i0 40263320Sdim+ 41263320Sdim+ ! CHECK: sdivx %g1, 63, %i0 ! encoding: [0xb1,0x68,0x60,0x3f] 42263320Sdim+ sdivx %g1, 63, %i0 43263320Sdim+ 44263320Sdim+ ! CHECK: udivx %g1, %i2, %i0 ! encoding: [0xb0,0x68,0x40,0x1a] 45263320Sdim+ udivx %g1, %i2, %i0 46263320Sdim+ 47263320Sdim+ ! CHECK: udivx %g1, 63, %i0 ! encoding: [0xb0,0x68,0x60,0x3f] 48263320Sdim+ udivx %g1, 63, %i0 49263320Sdim+ 50263320SdimIndex: lib/Target/Sparc/SparcInstr64Bit.td 51263320Sdim=================================================================== 52263320Sdim--- lib/Target/Sparc/SparcInstr64Bit.td 53263320Sdim+++ lib/Target/Sparc/SparcInstr64Bit.td 54263320Sdim@@ -193,9 +193,9 @@ def MULXrr : F3_1<2, 0b001001, 55263320Sdim "mulx $rs1, $rs2, $rd", 56263320Sdim [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>; 57263320Sdim def MULXri : F3_2<2, 0b001001, 58263320Sdim- (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i), 59263320Sdim- "mulx $rs1, $i, $rd", 60263320Sdim- [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$i)))]>; 61263320Sdim+ (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 62263320Sdim+ "mulx $rs1, $simm13, $rd", 63263320Sdim+ [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>; 64263320Sdim 65263320Sdim // Division can trap. 66263320Sdim let hasSideEffects = 1 in { 67263320Sdim@@ -204,9 +204,9 @@ def SDIVXrr : F3_1<2, 0b101101, 68263320Sdim "sdivx $rs1, $rs2, $rd", 69263320Sdim [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>; 70263320Sdim def SDIVXri : F3_2<2, 0b101101, 71263320Sdim- (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i), 72263320Sdim- "sdivx $rs1, $i, $rd", 73263320Sdim- [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$i)))]>; 74263320Sdim+ (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 75263320Sdim+ "sdivx $rs1, $simm13, $rd", 76263320Sdim+ [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>; 77263320Sdim 78263320Sdim def UDIVXrr : F3_1<2, 0b001101, 79263320Sdim (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 80263320Sdim@@ -213,9 +213,9 @@ def UDIVXrr : F3_1<2, 0b001101, 81263320Sdim "udivx $rs1, $rs2, $rd", 82263320Sdim [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>; 83263320Sdim def UDIVXri : F3_2<2, 0b001101, 84263320Sdim- (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i), 85263320Sdim- "udivx $rs1, $i, $rd", 86263320Sdim- [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$i)))]>; 87263320Sdim+ (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 88263320Sdim+ "udivx $rs1, $simm13, $rd", 89263320Sdim+ [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>; 90263320Sdim } // hasSideEffects = 1 91263320Sdim 92263320Sdim } // Predicates = [Is64Bit] 93263320SdimIndex: lib/Target/Sparc/SparcInstrFormats.td 94263320Sdim=================================================================== 95263320Sdim--- lib/Target/Sparc/SparcInstrFormats.td 96263320Sdim+++ lib/Target/Sparc/SparcInstrFormats.td 97263320Sdim@@ -193,12 +193,12 @@ class F3_Si<bits<2> opVal, bits<6> op3val, bit xVa 98263320Sdim // Define rr and ri shift instructions with patterns. 99263320Sdim multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, 100263320Sdim ValueType VT, RegisterClass RC> { 101263320Sdim- def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, IntRegs:$rs2), 102263320Sdim- !strconcat(OpcStr, " $rs, $rs2, $rd"), 103263320Sdim- [(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>; 104263320Sdim- def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, i32imm:$shcnt), 105263320Sdim- !strconcat(OpcStr, " $rs, $shcnt, $rd"), 106263320Sdim- [(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>; 107263320Sdim+ def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), 108263320Sdim+ !strconcat(OpcStr, " $rs1, $rs2, $rd"), 109263320Sdim+ [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>; 110263320Sdim+ def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt), 111263320Sdim+ !strconcat(OpcStr, " $rs1, $shcnt, $rd"), 112263320Sdim+ [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>; 113263320Sdim } 114263320Sdim 115263320Sdim class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern> 116