1263320SdimPull in r198738 from upstream llvm trunk (by Venkatraman Govindaraju): 2263320Sdim 3263320Sdim [Sparc] Add support for parsing branch instructions and conditional moves. 4263320Sdim 5269012SemasteIntroduced here: http://svnweb.freebsd.org/changeset/base/262261 6263320Sdim 7263320SdimIndex: test/MC/Disassembler/Sparc/sparc.txt 8263320Sdim=================================================================== 9263320Sdim--- test/MC/Disassembler/Sparc/sparc.txt 10263320Sdim+++ test/MC/Disassembler/Sparc/sparc.txt 11263320Sdim@@ -80,3 +80,90 @@ 12263320Sdim 13263320Sdim # CHECK: subxcc %g1, %g2, %g3 14263320Sdim 0x86 0xe0 0x40 0x02 15263320Sdim+ 16263320Sdim+# CHECK: ba 4194303 17263320Sdim+0x10 0xbf 0xff 0xff 18263320Sdim+ 19263320Sdim+# CHECK: bne 4194303 20263320Sdim+0x12 0xbf 0xff 0xff 21263320Sdim+ 22263320Sdim+# CHECK: be 4194303 23263320Sdim+0x02 0xbf 0xff 0xff 24263320Sdim+ 25263320Sdim+# CHECK: bg 4194303 26263320Sdim+0x14 0xbf 0xff 0xff 27263320Sdim+ 28263320Sdim+# CHECK: ble 4194303 29263320Sdim+0x04 0xbf 0xff 0xff 30263320Sdim+ 31263320Sdim+# CHECK: bge 4194303 32263320Sdim+0x16 0xbf 0xff 0xff 33263320Sdim+ 34263320Sdim+# CHECK: bl 4194303 35263320Sdim+0x06 0xbf 0xff 0xff 36263320Sdim+ 37263320Sdim+# CHECK: bgu 4194303 38263320Sdim+0x18 0xbf 0xff 0xff 39263320Sdim+ 40263320Sdim+# CHECK: bleu 4194303 41263320Sdim+0x08 0xbf 0xff 0xff 42263320Sdim+ 43263320Sdim+# CHECK: bcc 4194303 44263320Sdim+0x1a 0xbf 0xff 0xff 45263320Sdim+ 46263320Sdim+# CHECK: bcs 4194303 47263320Sdim+0x0a 0xbf 0xff 0xff 48263320Sdim+ 49263320Sdim+# CHECK: bpos 4194303 50263320Sdim+0x1c 0xbf 0xff 0xff 51263320Sdim+ 52263320Sdim+# CHECK: bneg 4194303 53263320Sdim+0x0c 0xbf 0xff 0xff 54263320Sdim+ 55263320Sdim+# CHECK: bvc 4194303 56263320Sdim+0x1e 0xbf 0xff 0xff 57263320Sdim+ 58263320Sdim+# CHECK: bvs 4194303 59263320Sdim+0x0e 0xbf 0xff 0xff 60263320Sdim+ 61263320Sdim+# CHECK: fbu 4194303 62263320Sdim+0x0f 0xbf 0xff 0xff 63263320Sdim+ 64263320Sdim+# CHECK: fbg 4194303 65263320Sdim+0x0d 0xbf 0xff 0xff 66263320Sdim+ 67263320Sdim+# CHECK: fbug 4194303 68263320Sdim+0x0b 0xbf 0xff 0xff 69263320Sdim+ 70263320Sdim+# CHECK: fbl 4194303 71263320Sdim+0x09 0xbf 0xff 0xff 72263320Sdim+ 73263320Sdim+# CHECK: fbul 4194303 74263320Sdim+0x07 0xbf 0xff 0xff 75263320Sdim+ 76263320Sdim+# CHECK: fblg 4194303 77263320Sdim+0x05 0xbf 0xff 0xff 78263320Sdim+ 79263320Sdim+# CHECK: fbne 4194303 80263320Sdim+0x03 0xbf 0xff 0xff 81263320Sdim+ 82263320Sdim+# CHECK: fbe 4194303 83263320Sdim+0x13 0xbf 0xff 0xff 84263320Sdim+ 85263320Sdim+# CHECK: fbue 4194303 86263320Sdim+0x15 0xbf 0xff 0xff 87263320Sdim+ 88263320Sdim+# CHECK: fbge 4194303 89263320Sdim+0x17 0xbf 0xff 0xff 90263320Sdim+ 91263320Sdim+# CHECK: fbuge 4194303 92263320Sdim+0x19 0xbf 0xff 0xff 93263320Sdim+ 94263320Sdim+# CHECK: fble 4194303 95263320Sdim+0x1b 0xbf 0xff 0xff 96263320Sdim+ 97263320Sdim+# CHECK: fbule 4194303 98263320Sdim+0x1d 0xbf 0xff 0xff 99263320Sdim+ 100263320Sdim+# CHECK: fbo 4194303 101263320Sdim+0x1f 0xbf 0xff 0xff 102263320SdimIndex: test/MC/Sparc/sparc-ctrl-instructions.s 103263320Sdim=================================================================== 104263320Sdim--- test/MC/Sparc/sparc-ctrl-instructions.s 105263320Sdim+++ test/MC/Sparc/sparc-ctrl-instructions.s 106263320Sdim@@ -31,3 +31,117 @@ 107263320Sdim ! CHECK-NEXT: ! fixup A - offset: 0, value: %lo(sym), kind: fixup_sparc_lo10 108263320Sdim jmp %g1+%lo(sym) 109263320Sdim 110263320Sdim+ ! CHECK: ba .BB0 ! encoding: [0x10,0b10AAAAAA,A,A] 111263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 112263320Sdim+ ba .BB0 113263320Sdim+ 114263320Sdim+ ! CHECK: bne .BB0 ! encoding: [0x12,0b10AAAAAA,A,A] 115263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 116263320Sdim+ bne .BB0 117263320Sdim+ 118263320Sdim+ ! CHECK: be .BB0 ! encoding: [0x02,0b10AAAAAA,A,A] 119263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 120263320Sdim+ be .BB0 121263320Sdim+ 122263320Sdim+ ! CHECK: bg .BB0 ! encoding: [0x14,0b10AAAAAA,A,A] 123263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 124263320Sdim+ bg .BB0 125263320Sdim+ 126263320Sdim+ ! CHECK: ble .BB0 ! encoding: [0x04,0b10AAAAAA,A,A] 127263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 128263320Sdim+ ble .BB0 129263320Sdim+ 130263320Sdim+ ! CHECK: bge .BB0 ! encoding: [0x16,0b10AAAAAA,A,A] 131263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 132263320Sdim+ bge .BB0 133263320Sdim+ 134263320Sdim+ ! CHECK: bl .BB0 ! encoding: [0x06,0b10AAAAAA,A,A] 135263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 136263320Sdim+ bl .BB0 137263320Sdim+ 138263320Sdim+ ! CHECK: bgu .BB0 ! encoding: [0x18,0b10AAAAAA,A,A] 139263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 140263320Sdim+ bgu .BB0 141263320Sdim+ 142263320Sdim+ ! CHECK: bleu .BB0 ! encoding: [0x08,0b10AAAAAA,A,A] 143263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 144263320Sdim+ bleu .BB0 145263320Sdim+ 146263320Sdim+ ! CHECK: bcc .BB0 ! encoding: [0x1a,0b10AAAAAA,A,A] 147263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 148263320Sdim+ bcc .BB0 149263320Sdim+ 150263320Sdim+ ! CHECK: bcs .BB0 ! encoding: [0x0a,0b10AAAAAA,A,A] 151263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 152263320Sdim+ bcs .BB0 153263320Sdim+ 154263320Sdim+ ! CHECK: bpos .BB0 ! encoding: [0x1c,0b10AAAAAA,A,A] 155263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 156263320Sdim+ bpos .BB0 157263320Sdim+ 158263320Sdim+ ! CHECK: bneg .BB0 ! encoding: [0x0c,0b10AAAAAA,A,A] 159263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 160263320Sdim+ bneg .BB0 161263320Sdim+ 162263320Sdim+ ! CHECK: bvc .BB0 ! encoding: [0x1e,0b10AAAAAA,A,A] 163263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 164263320Sdim+ bvc .BB0 165263320Sdim+ 166263320Sdim+ ! CHECK: bvs .BB0 ! encoding: [0x0e,0b10AAAAAA,A,A] 167263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 168263320Sdim+ bvs .BB0 169263320Sdim+ 170263320Sdim+ ! CHECK: fbu .BB0 ! encoding: [0x0f,0b10AAAAAA,A,A] 171263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 172263320Sdim+ fbu .BB0 173263320Sdim+ 174263320Sdim+ ! CHECK: fbg .BB0 ! encoding: [0x0d,0b10AAAAAA,A,A] 175263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 176263320Sdim+ fbg .BB0 177263320Sdim+ ! CHECK: fbug .BB0 ! encoding: [0x0b,0b10AAAAAA,A,A] 178263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 179263320Sdim+ fbug .BB0 180263320Sdim+ 181263320Sdim+ ! CHECK: fbl .BB0 ! encoding: [0x09,0b10AAAAAA,A,A] 182263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 183263320Sdim+ fbl .BB0 184263320Sdim+ 185263320Sdim+ ! CHECK: fbul .BB0 ! encoding: [0x07,0b10AAAAAA,A,A] 186263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 187263320Sdim+ fbul .BB0 188263320Sdim+ 189263320Sdim+ ! CHECK: fblg .BB0 ! encoding: [0x05,0b10AAAAAA,A,A] 190263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 191263320Sdim+ fblg .BB0 192263320Sdim+ 193263320Sdim+ ! CHECK: fbne .BB0 ! encoding: [0x03,0b10AAAAAA,A,A] 194263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 195263320Sdim+ fbne .BB0 196263320Sdim+ 197263320Sdim+ ! CHECK: fbe .BB0 ! encoding: [0x13,0b10AAAAAA,A,A] 198263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 199263320Sdim+ fbe .BB0 200263320Sdim+ 201263320Sdim+ ! CHECK: fbue .BB0 ! encoding: [0x15,0b10AAAAAA,A,A] 202263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 203263320Sdim+ fbue .BB0 204263320Sdim+ 205263320Sdim+ ! CHECK: fbge .BB0 ! encoding: [0x17,0b10AAAAAA,A,A] 206263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 207263320Sdim+ fbge .BB0 208263320Sdim+ 209263320Sdim+ ! CHECK: fbuge .BB0 ! encoding: [0x19,0b10AAAAAA,A,A] 210263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 211263320Sdim+ fbuge .BB0 212263320Sdim+ 213263320Sdim+ ! CHECK: fble .BB0 ! encoding: [0x1b,0b10AAAAAA,A,A] 214263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 215263320Sdim+ fble .BB0 216263320Sdim+ 217263320Sdim+ ! CHECK: fbule .BB0 ! encoding: [0x1d,0b10AAAAAA,A,A] 218263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 219263320Sdim+ fbule .BB0 220263320Sdim+ 221263320Sdim+ ! CHECK: fbo .BB0 ! encoding: [0x1f,0b10AAAAAA,A,A] 222263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br22 223263320Sdim+ fbo .BB0 224263320SdimIndex: test/MC/Sparc/sparc64-ctrl-instructions.s 225263320Sdim=================================================================== 226263320Sdim--- test/MC/Sparc/sparc64-ctrl-instructions.s 227263320Sdim+++ test/MC/Sparc/sparc64-ctrl-instructions.s 228263320Sdim@@ -0,0 +1,235 @@ 229263320Sdim+! RUN: llvm-mc %s -triple=sparc64-unknown-linux-gnu -show-encoding | FileCheck %s 230263320Sdim+ 231263320Sdim+ 232263320Sdim+ ! CHECK: bne %xcc, .BB0 ! encoding: [0x12,0b01101AAA,A,A] 233263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 234263320Sdim+ bne %xcc, .BB0 235263320Sdim+ 236263320Sdim+ ! CHECK: be %xcc, .BB0 ! encoding: [0x02,0b01101AAA,A,A] 237263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 238263320Sdim+ be %xcc, .BB0 239263320Sdim+ 240263320Sdim+ ! CHECK: bg %xcc, .BB0 ! encoding: [0x14,0b01101AAA,A,A] 241263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 242263320Sdim+ bg %xcc, .BB0 243263320Sdim+ 244263320Sdim+ ! CHECK: ble %xcc, .BB0 ! encoding: [0x04,0b01101AAA,A,A] 245263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 246263320Sdim+ ble %xcc, .BB0 247263320Sdim+ 248263320Sdim+ ! CHECK: bge %xcc, .BB0 ! encoding: [0x16,0b01101AAA,A,A] 249263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 250263320Sdim+ bge %xcc, .BB0 251263320Sdim+ 252263320Sdim+ ! CHECK: bl %xcc, .BB0 ! encoding: [0x06,0b01101AAA,A,A] 253263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 254263320Sdim+ bl %xcc, .BB0 255263320Sdim+ 256263320Sdim+ ! CHECK: bgu %xcc, .BB0 ! encoding: [0x18,0b01101AAA,A,A] 257263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 258263320Sdim+ bgu %xcc, .BB0 259263320Sdim+ 260263320Sdim+ ! CHECK: bleu %xcc, .BB0 ! encoding: [0x08,0b01101AAA,A,A] 261263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 262263320Sdim+ bleu %xcc, .BB0 263263320Sdim+ 264263320Sdim+ ! CHECK: bcc %xcc, .BB0 ! encoding: [0x1a,0b01101AAA,A,A] 265263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 266263320Sdim+ bcc %xcc, .BB0 267263320Sdim+ 268263320Sdim+ ! CHECK: bcs %xcc, .BB0 ! encoding: [0x0a,0b01101AAA,A,A] 269263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 270263320Sdim+ bcs %xcc, .BB0 271263320Sdim+ 272263320Sdim+ ! CHECK: bpos %xcc, .BB0 ! encoding: [0x1c,0b01101AAA,A,A] 273263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 274263320Sdim+ bpos %xcc, .BB0 275263320Sdim+ 276263320Sdim+ ! CHECK: bneg %xcc, .BB0 ! encoding: [0x0c,0b01101AAA,A,A] 277263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 278263320Sdim+ bneg %xcc, .BB0 279263320Sdim+ 280263320Sdim+ ! CHECK: bvc %xcc, .BB0 ! encoding: [0x1e,0b01101AAA,A,A] 281263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 282263320Sdim+ bvc %xcc, .BB0 283263320Sdim+ 284263320Sdim+ ! CHECK: bvs %xcc, .BB0 ! encoding: [0x0e,0b01101AAA,A,A] 285263320Sdim+ ! CHECK-NEXT: ! fixup A - offset: 0, value: .BB0, kind: fixup_sparc_br19 286263320Sdim+ bvs %xcc, .BB0 287263320Sdim+ 288263320Sdim+ 289263320Sdim+ ! CHECK: movne %icc, %g1, %g2 ! encoding: [0x85,0x66,0x40,0x01] 290263320Sdim+ ! CHECK: move %icc, %g1, %g2 ! encoding: [0x85,0x64,0x40,0x01] 291263320Sdim+ ! CHECK: movg %icc, %g1, %g2 ! encoding: [0x85,0x66,0x80,0x01] 292263320Sdim+ ! CHECK: movle %icc, %g1, %g2 ! encoding: [0x85,0x64,0x80,0x01] 293263320Sdim+ ! CHECK: movge %icc, %g1, %g2 ! encoding: [0x85,0x66,0xc0,0x01] 294263320Sdim+ ! CHECK: movl %icc, %g1, %g2 ! encoding: [0x85,0x64,0xc0,0x01] 295263320Sdim+ ! CHECK: movgu %icc, %g1, %g2 ! encoding: [0x85,0x67,0x00,0x01] 296263320Sdim+ ! CHECK: movleu %icc, %g1, %g2 ! encoding: [0x85,0x65,0x00,0x01] 297263320Sdim+ ! CHECK: movcc %icc, %g1, %g2 ! encoding: [0x85,0x67,0x40,0x01] 298263320Sdim+ ! CHECK: movcs %icc, %g1, %g2 ! encoding: [0x85,0x65,0x40,0x01] 299263320Sdim+ ! CHECK: movpos %icc, %g1, %g2 ! encoding: [0x85,0x67,0x80,0x01] 300263320Sdim+ ! CHECK: movneg %icc, %g1, %g2 ! encoding: [0x85,0x65,0x80,0x01] 301263320Sdim+ ! CHECK: movvc %icc, %g1, %g2 ! encoding: [0x85,0x67,0xc0,0x01] 302263320Sdim+ ! CHECK: movvs %icc, %g1, %g2 ! encoding: [0x85,0x65,0xc0,0x01] 303263320Sdim+ movne %icc, %g1, %g2 304263320Sdim+ move %icc, %g1, %g2 305263320Sdim+ movg %icc, %g1, %g2 306263320Sdim+ movle %icc, %g1, %g2 307263320Sdim+ movge %icc, %g1, %g2 308263320Sdim+ movl %icc, %g1, %g2 309263320Sdim+ movgu %icc, %g1, %g2 310263320Sdim+ movleu %icc, %g1, %g2 311263320Sdim+ movcc %icc, %g1, %g2 312263320Sdim+ movcs %icc, %g1, %g2 313263320Sdim+ movpos %icc, %g1, %g2 314263320Sdim+ movneg %icc, %g1, %g2 315263320Sdim+ movvc %icc, %g1, %g2 316263320Sdim+ movvs %icc, %g1, %g2 317263320Sdim+ 318263320Sdim+ ! CHECK: movne %xcc, %g1, %g2 ! encoding: [0x85,0x66,0x50,0x01] 319263320Sdim+ ! CHECK: move %xcc, %g1, %g2 ! encoding: [0x85,0x64,0x50,0x01] 320263320Sdim+ ! CHECK: movg %xcc, %g1, %g2 ! encoding: [0x85,0x66,0x90,0x01] 321263320Sdim+ ! CHECK: movle %xcc, %g1, %g2 ! encoding: [0x85,0x64,0x90,0x01] 322263320Sdim+ ! CHECK: movge %xcc, %g1, %g2 ! encoding: [0x85,0x66,0xd0,0x01] 323263320Sdim+ ! CHECK: movl %xcc, %g1, %g2 ! encoding: [0x85,0x64,0xd0,0x01] 324263320Sdim+ ! CHECK: movgu %xcc, %g1, %g2 ! encoding: [0x85,0x67,0x10,0x01] 325263320Sdim+ ! CHECK: movleu %xcc, %g1, %g2 ! encoding: [0x85,0x65,0x10,0x01] 326263320Sdim+ ! CHECK: movcc %xcc, %g1, %g2 ! encoding: [0x85,0x67,0x50,0x01] 327263320Sdim+ ! CHECK: movcs %xcc, %g1, %g2 ! encoding: [0x85,0x65,0x50,0x01] 328263320Sdim+ ! CHECK: movpos %xcc, %g1, %g2 ! encoding: [0x85,0x67,0x90,0x01] 329263320Sdim+ ! CHECK: movneg %xcc, %g1, %g2 ! encoding: [0x85,0x65,0x90,0x01] 330263320Sdim+ ! CHECK: movvc %xcc, %g1, %g2 ! encoding: [0x85,0x67,0xd0,0x01] 331263320Sdim+ ! CHECK: movvs %xcc, %g1, %g2 ! encoding: [0x85,0x65,0xd0,0x01] 332263320Sdim+ movne %xcc, %g1, %g2 333263320Sdim+ move %xcc, %g1, %g2 334263320Sdim+ movg %xcc, %g1, %g2 335263320Sdim+ movle %xcc, %g1, %g2 336263320Sdim+ movge %xcc, %g1, %g2 337263320Sdim+ movl %xcc, %g1, %g2 338263320Sdim+ movgu %xcc, %g1, %g2 339263320Sdim+ movleu %xcc, %g1, %g2 340263320Sdim+ movcc %xcc, %g1, %g2 341263320Sdim+ movcs %xcc, %g1, %g2 342263320Sdim+ movpos %xcc, %g1, %g2 343263320Sdim+ movneg %xcc, %g1, %g2 344263320Sdim+ movvc %xcc, %g1, %g2 345263320Sdim+ movvs %xcc, %g1, %g2 346263320Sdim+ 347263320Sdim+ ! CHECK: movu %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0xc0,0x01] 348263320Sdim+ ! CHECK: movg %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0x80,0x01] 349263320Sdim+ ! CHECK: movug %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0x40,0x01] 350263320Sdim+ ! CHECK: movl %fcc0, %g1, %g2 ! encoding: [0x85,0x61,0x00,0x01] 351263320Sdim+ ! CHECK: movul %fcc0, %g1, %g2 ! encoding: [0x85,0x60,0xc0,0x01] 352263320Sdim+ ! CHECK: movlg %fcc0, %g1, %g2 ! encoding: [0x85,0x60,0x80,0x01] 353263320Sdim+ ! CHECK: movne %fcc0, %g1, %g2 ! encoding: [0x85,0x60,0x40,0x01] 354263320Sdim+ ! CHECK: move %fcc0, %g1, %g2 ! encoding: [0x85,0x62,0x40,0x01] 355263320Sdim+ ! CHECK: movue %fcc0, %g1, %g2 ! encoding: [0x85,0x62,0x80,0x01] 356263320Sdim+ ! CHECK: movge %fcc0, %g1, %g2 ! encoding: [0x85,0x62,0xc0,0x01] 357263320Sdim+ ! CHECK: movuge %fcc0, %g1, %g2 ! encoding: [0x85,0x63,0x00,0x01] 358263320Sdim+ ! CHECK: movle %fcc0, %g1, %g2 ! encoding: [0x85,0x63,0x40,0x01] 359263320Sdim+ ! CHECK: movule %fcc0, %g1, %g2 ! encoding: [0x85,0x63,0x80,0x01] 360263320Sdim+ ! CHECK: movo %fcc0, %g1, %g2 ! encoding: [0x85,0x63,0xc0,0x01] 361263320Sdim+ movu %fcc0, %g1, %g2 362263320Sdim+ movg %fcc0, %g1, %g2 363263320Sdim+ movug %fcc0, %g1, %g2 364263320Sdim+ movl %fcc0, %g1, %g2 365263320Sdim+ movul %fcc0, %g1, %g2 366263320Sdim+ movlg %fcc0, %g1, %g2 367263320Sdim+ movne %fcc0, %g1, %g2 368263320Sdim+ move %fcc0, %g1, %g2 369263320Sdim+ movue %fcc0, %g1, %g2 370263320Sdim+ movge %fcc0, %g1, %g2 371263320Sdim+ movuge %fcc0, %g1, %g2 372263320Sdim+ movle %fcc0, %g1, %g2 373263320Sdim+ movule %fcc0, %g1, %g2 374263320Sdim+ movo %fcc0, %g1, %g2 375263320Sdim+ 376263320Sdim+ 377263320Sdim+ ! CHECK fmovsne %icc, %f1, %f2 ! encoding: [0x85,0xaa,0x60,0x21] 378263320Sdim+ ! CHECK fmovse %icc, %f1, %f2 ! encoding: [0x85,0xa8,0x60,0x21] 379263320Sdim+ ! CHECK fmovsg %icc, %f1, %f2 ! encoding: [0x85,0xaa,0xa0,0x21] 380263320Sdim+ ! CHECK fmovsle %icc, %f1, %f2 ! encoding: [0x85,0xa8,0xa0,0x21] 381263320Sdim+ ! CHECK fmovsge %icc, %f1, %f2 ! encoding: [0x85,0xaa,0xe0,0x21] 382263320Sdim+ ! CHECK fmovsl %icc, %f1, %f2 ! encoding: [0x85,0xa8,0xe0,0x21] 383263320Sdim+ ! CHECK fmovsgu %icc, %f1, %f2 ! encoding: [0x85,0xab,0x20,0x21] 384263320Sdim+ ! CHECK fmovsleu %icc, %f1, %f2 ! encoding: [0x85,0xa9,0x20,0x21] 385263320Sdim+ ! CHECK fmovscc %icc, %f1, %f2 ! encoding: [0x85,0xab,0x60,0x21] 386263320Sdim+ ! CHECK fmovscs %icc, %f1, %f2 ! encoding: [0x85,0xa9,0x60,0x21] 387263320Sdim+ ! CHECK fmovspos %icc, %f1, %f2 ! encoding: [0x85,0xab,0xa0,0x21] 388263320Sdim+ ! CHECK fmovsneg %icc, %f1, %f2 ! encoding: [0x85,0xa9,0xa0,0x21] 389263320Sdim+ ! CHECK fmovsvc %icc, %f1, %f2 ! encoding: [0x85,0xab,0xe0,0x21] 390263320Sdim+ ! CHECK fmovsvs %icc, %f1, %f2 ! encoding: [0x85,0xa9,0xe0,0x21] 391263320Sdim+ fmovsne %icc, %f1, %f2 392263320Sdim+ fmovse %icc, %f1, %f2 393263320Sdim+ fmovsg %icc, %f1, %f2 394263320Sdim+ fmovsle %icc, %f1, %f2 395263320Sdim+ fmovsge %icc, %f1, %f2 396263320Sdim+ fmovsl %icc, %f1, %f2 397263320Sdim+ fmovsgu %icc, %f1, %f2 398263320Sdim+ fmovsleu %icc, %f1, %f2 399263320Sdim+ fmovscc %icc, %f1, %f2 400263320Sdim+ fmovscs %icc, %f1, %f2 401263320Sdim+ fmovspos %icc, %f1, %f2 402263320Sdim+ fmovsneg %icc, %f1, %f2 403263320Sdim+ fmovsvc %icc, %f1, %f2 404263320Sdim+ fmovsvs %icc, %f1, %f2 405263320Sdim+ 406263320Sdim+ ! CHECK fmovsne %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0x70,0x21] 407263320Sdim+ ! CHECK fmovse %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0x70,0x21] 408263320Sdim+ ! CHECK fmovsg %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0xb0,0x21] 409263320Sdim+ ! CHECK fmovsle %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0xb0,0x21] 410263320Sdim+ ! CHECK fmovsge %xcc, %f1, %f2 ! encoding: [0x85,0xaa,0xf0,0x21] 411263320Sdim+ ! CHECK fmovsl %xcc, %f1, %f2 ! encoding: [0x85,0xa8,0xf0,0x21] 412263320Sdim+ ! CHECK fmovsgu %xcc, %f1, %f2 ! encoding: [0x85,0xab,0x30,0x21] 413263320Sdim+ ! CHECK fmovsleu %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0x30,0x21] 414263320Sdim+ ! CHECK fmovscc %xcc, %f1, %f2 ! encoding: [0x85,0xab,0x70,0x21] 415263320Sdim+ ! CHECK fmovscs %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0x70,0x21] 416263320Sdim+ ! CHECK fmovspos %xcc, %f1, %f2 ! encoding: [0x85,0xab,0xb0,0x21] 417263320Sdim+ ! CHECK fmovsneg %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0xb0,0x21] 418263320Sdim+ ! CHECK fmovsvc %xcc, %f1, %f2 ! encoding: [0x85,0xab,0xf0,0x21] 419263320Sdim+ ! CHECK fmovsvs %xcc, %f1, %f2 ! encoding: [0x85,0xa9,0xf0,0x21] 420263320Sdim+ fmovsne %xcc, %f1, %f2 421263320Sdim+ fmovse %xcc, %f1, %f2 422263320Sdim+ fmovsg %xcc, %f1, %f2 423263320Sdim+ fmovsle %xcc, %f1, %f2 424263320Sdim+ fmovsge %xcc, %f1, %f2 425263320Sdim+ fmovsl %xcc, %f1, %f2 426263320Sdim+ fmovsgu %xcc, %f1, %f2 427263320Sdim+ fmovsleu %xcc, %f1, %f2 428263320Sdim+ fmovscc %xcc, %f1, %f2 429263320Sdim+ fmovscs %xcc, %f1, %f2 430263320Sdim+ fmovspos %xcc, %f1, %f2 431263320Sdim+ fmovsneg %xcc, %f1, %f2 432263320Sdim+ fmovsvc %xcc, %f1, %f2 433263320Sdim+ fmovsvs %xcc, %f1, %f2 434263320Sdim+ 435263320Sdim+ ! CHECK fmovsu %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0xc0,0x21] 436263320Sdim+ ! CHECK fmovsg %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x80,0x21] 437263320Sdim+ ! CHECK fmovsug %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x40,0x21] 438263320Sdim+ ! CHECK fmovsl %fcc0, %f1, %f2 ! encoding: [0x85,0xa9,0x00,0x21] 439263320Sdim+ ! CHECK fmovsul %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0xc0,0x21] 440263320Sdim+ ! CHECK fmovslg %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0x80,0x21] 441263320Sdim+ ! CHECK fmovsne %fcc0, %f1, %f2 ! encoding: [0x85,0xa8,0x40,0x21] 442263320Sdim+ ! CHECK fmovse %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0x40,0x21] 443263320Sdim+ ! CHECK fmovsue %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0x80,0x21] 444263320Sdim+ ! CHECK fmovsge %fcc0, %f1, %f2 ! encoding: [0x85,0xaa,0xc0,0x21] 445263320Sdim+ ! CHECK fmovsuge %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x00,0x21] 446263320Sdim+ ! CHECK fmovsle %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x40,0x21] 447263320Sdim+ ! CHECK fmovsule %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0x80,0x21] 448263320Sdim+ ! CHECK fmovso %fcc0, %f1, %f2 ! encoding: [0x85,0xab,0xc0,0x21] 449263320Sdim+ fmovsu %fcc0, %f1, %f2 450263320Sdim+ fmovsg %fcc0, %f1, %f2 451263320Sdim+ fmovsug %fcc0, %f1, %f2 452263320Sdim+ fmovsl %fcc0, %f1, %f2 453263320Sdim+ fmovsul %fcc0, %f1, %f2 454263320Sdim+ fmovslg %fcc0, %f1, %f2 455263320Sdim+ fmovsne %fcc0, %f1, %f2 456263320Sdim+ fmovse %fcc0, %f1, %f2 457263320Sdim+ fmovsue %fcc0, %f1, %f2 458263320Sdim+ fmovsge %fcc0, %f1, %f2 459263320Sdim+ fmovsuge %fcc0, %f1, %f2 460263320Sdim+ fmovsle %fcc0, %f1, %f2 461263320Sdim+ fmovsule %fcc0, %f1, %f2 462263320Sdim+ fmovso %fcc0, %f1, %f2 463263320Sdim+ 464263320SdimIndex: lib/Target/Sparc/SparcInstr64Bit.td 465263320Sdim=================================================================== 466263320Sdim--- lib/Target/Sparc/SparcInstr64Bit.td 467263320Sdim+++ lib/Target/Sparc/SparcInstr64Bit.td 468263320Sdim@@ -333,32 +333,42 @@ class XBranchSP<dag ins, string asmstr, list<dag> 469263320Sdim let Predicates = [Is64Bit] in { 470263320Sdim 471263320Sdim let Uses = [ICC] in 472263320Sdim-def BPXCC : XBranchSP<(ins brtarget:$imm22, CCOp:$cond), 473263320Sdim- "b$cond %xcc, $imm22", 474263320Sdim- [(SPbrxcc bb:$imm22, imm:$cond)]>; 475263320Sdim+def BPXCC : XBranchSP<(ins brtarget:$imm19, CCOp:$cond), 476263320Sdim+ "b$cond %xcc, $imm19", 477263320Sdim+ [(SPbrxcc bb:$imm19, imm:$cond)]>; 478263320Sdim 479263320Sdim // Conditional moves on %xcc. 480263320Sdim let Uses = [ICC], Constraints = "$f = $rd" in { 481263320Sdim-def MOVXCCrr : Pseudo<(outs IntRegs:$rd), 482263320Sdim+let cc = 0b110 in { 483263320Sdim+def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd), 484263320Sdim (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 485263320Sdim "mov$cond %xcc, $rs2, $rd", 486263320Sdim [(set i32:$rd, 487263320Sdim (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>; 488263320Sdim-def MOVXCCri : Pseudo<(outs IntRegs:$rd), 489263320Sdim- (ins i32imm:$i, IntRegs:$f, CCOp:$cond), 490263320Sdim- "mov$cond %xcc, $i, $rd", 491263320Sdim+def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd), 492263320Sdim+ (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 493263320Sdim+ "mov$cond %xcc, $simm11, $rd", 494263320Sdim [(set i32:$rd, 495263320Sdim- (SPselectxcc simm11:$i, i32:$f, imm:$cond))]>; 496263320Sdim-def FMOVS_XCC : Pseudo<(outs FPRegs:$rd), 497263320Sdim+ (SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>; 498263320Sdim+} // cc 499263320Sdim+ 500263320Sdim+let opf_cc = 0b110 in { 501263320Sdim+def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 502263320Sdim (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 503263320Sdim "fmovs$cond %xcc, $rs2, $rd", 504263320Sdim [(set f32:$rd, 505263320Sdim (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>; 506263320Sdim-def FMOVD_XCC : Pseudo<(outs DFPRegs:$rd), 507263320Sdim+def FMOVD_XCC : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 508263320Sdim (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 509263320Sdim "fmovd$cond %xcc, $rs2, $rd", 510263320Sdim [(set f64:$rd, 511263320Sdim (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>; 512263320Sdim+def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 513263320Sdim+ (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 514263320Sdim+ "fmovq$cond %xcc, $rs2, $rd", 515263320Sdim+ [(set f128:$rd, 516263320Sdim+ (SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>; 517263320Sdim+} // opf_cc 518263320Sdim } // Uses, Constraints 519263320Sdim 520263320Sdim //===----------------------------------------------------------------------===// 521263320SdimIndex: lib/Target/Sparc/SparcInstrInfo.td 522263320Sdim=================================================================== 523263320Sdim--- lib/Target/Sparc/SparcInstrInfo.td 524263320Sdim+++ lib/Target/Sparc/SparcInstrInfo.td 525263320Sdim@@ -928,8 +928,9 @@ let Predicates = [HasV9], Constraints = "$f = $rd" 526263320Sdim def FMOVQ_ICC 527263320Sdim : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 528263320Sdim (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 529263320Sdim- "fmovd$cond %icc, $rs2, $rd", 530263320Sdim- [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>; 531263320Sdim+ "fmovq$cond %icc, $rs2, $rd", 532263320Sdim+ [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>, 533263320Sdim+ Requires<[HasHardQuad]>; 534263320Sdim } 535263320Sdim 536263320Sdim let Uses = [FCC], opf_cc = 0b000 in { 537263320Sdim@@ -946,8 +947,9 @@ let Predicates = [HasV9], Constraints = "$f = $rd" 538263320Sdim def FMOVQ_FCC 539263320Sdim : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 540263320Sdim (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 541263320Sdim- "fmovd$cond %fcc0, $rs2, $rd", 542263320Sdim- [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>; 543263320Sdim+ "fmovq$cond %fcc0, $rs2, $rd", 544263320Sdim+ [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>, 545263320Sdim+ Requires<[HasHardQuad]>; 546263320Sdim } 547263320Sdim 548263320Sdim } 549263320Sdim@@ -1092,3 +1094,4 @@ def : Pat<(atomic_store ADDRri:$dst, i32:$val), (S 550263320Sdim 551263320Sdim 552263320Sdim include "SparcInstr64Bit.td" 553263320Sdim+include "SparcInstrAliases.td" 554263320SdimIndex: lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 555263320Sdim=================================================================== 556263320Sdim--- lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 557263320Sdim+++ lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 558263320Sdim@@ -537,9 +537,29 @@ SparcAsmParser::parseSparcAsmOperand(SparcOperand 559263320Sdim Parser.Lex(); // Eat the '%'. 560263320Sdim unsigned RegNo; 561263320Sdim if (matchRegisterName(Parser.getTok(), RegNo, false, false)) { 562263320Sdim+ StringRef name = Parser.getTok().getString(); 563263320Sdim Parser.Lex(); // Eat the identifier token. 564263320Sdim E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 565263320Sdim- Op = SparcOperand::CreateReg(RegNo, SparcOperand::rk_None, S, E); 566263320Sdim+ switch (RegNo) { 567263320Sdim+ default: 568263320Sdim+ Op = SparcOperand::CreateReg(RegNo, SparcOperand::rk_None, S, E); 569263320Sdim+ break; 570263320Sdim+ case Sparc::Y: 571263320Sdim+ Op = SparcOperand::CreateToken("%y", S); 572263320Sdim+ break; 573263320Sdim+ 574263320Sdim+ case Sparc::ICC: 575263320Sdim+ if (name == "xcc") 576263320Sdim+ Op = SparcOperand::CreateToken("%xcc", S); 577263320Sdim+ else 578263320Sdim+ Op = SparcOperand::CreateToken("%icc", S); 579263320Sdim+ break; 580263320Sdim+ 581263320Sdim+ case Sparc::FCC: 582263320Sdim+ assert(name == "fcc0" && "Cannot handle %fcc other than %fcc0 yet"); 583263320Sdim+ Op = SparcOperand::CreateToken("%fcc0", S); 584263320Sdim+ break; 585263320Sdim+ } 586263320Sdim break; 587263320Sdim } 588263320Sdim if (matchSparcAsmModifiers(EVal, E)) { 589263320SdimIndex: lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp 590263320Sdim=================================================================== 591263320Sdim--- lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp 592263320Sdim+++ lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp 593263320Sdim@@ -83,6 +83,17 @@ void SparcInstPrinter::printCCOperand(const MCInst 594263320Sdim raw_ostream &O) 595263320Sdim { 596263320Sdim int CC = (int)MI->getOperand(opNum).getImm(); 597263320Sdim+ switch (MI->getOpcode()) { 598263320Sdim+ default: break; 599263320Sdim+ case SP::FBCOND: 600263320Sdim+ case SP::MOVFCCrr: 601263320Sdim+ case SP::MOVFCCri: 602263320Sdim+ case SP::FMOVS_FCC: 603263320Sdim+ case SP::FMOVD_FCC: 604263320Sdim+ case SP::FMOVQ_FCC: // Make sure CC is a fp conditional flag. 605263320Sdim+ CC = (CC < 16) ? (CC + 16) : CC; 606263320Sdim+ break; 607263320Sdim+ } 608263320Sdim O << SPARCCondCodeToString((SPCC::CondCodes)CC); 609263320Sdim } 610263320Sdim 611263320SdimIndex: lib/Target/Sparc/SparcInstrAliases.td 612263320Sdim=================================================================== 613263320Sdim--- lib/Target/Sparc/SparcInstrAliases.td 614263320Sdim+++ lib/Target/Sparc/SparcInstrAliases.td 615263320Sdim@@ -0,0 +1,119 @@ 616263320Sdim+//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===// 617263320Sdim+// 618263320Sdim+// The LLVM Compiler Infrastructure 619263320Sdim+// 620263320Sdim+// This file is distributed under the University of Illinois Open Source 621263320Sdim+// License. See LICENSE.TXT for details. 622263320Sdim+// 623263320Sdim+//===----------------------------------------------------------------------===// 624263320Sdim+// 625263320Sdim+// This file contains instruction aliases for Sparc. 626263320Sdim+//===----------------------------------------------------------------------===// 627263320Sdim+ 628263320Sdim+// Instruction aliases for conditional moves. 629263320Sdim+ 630263320Sdim+// mov<cond> <ccreg> rs2, rd 631263320Sdim+multiclass cond_mov_alias<string cond, int condVal, string ccreg, 632263320Sdim+ Instruction movrr, Instruction movri, 633263320Sdim+ Instruction fmovs, Instruction fmovd> { 634263320Sdim+ 635263320Sdim+ // mov<cond> (%icc|%xcc|%fcc0), rs2, rd 636263320Sdim+ def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg), 637263320Sdim+ ", $rs2, $rd"), 638263320Sdim+ (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>; 639263320Sdim+ 640263320Sdim+ // mov<cond> (%icc|%xcc|%fcc0), simm11, rd 641263320Sdim+ def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg), 642263320Sdim+ ", $simm11, $rd"), 643263320Sdim+ (movri IntRegs:$rd, i32imm:$simm11, condVal)>; 644263320Sdim+ 645263320Sdim+ // fmovs<cond> (%icc|%xcc|%fcc0), $rs2, $rd 646263320Sdim+ def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg), 647263320Sdim+ ", $rs2, $rd"), 648263320Sdim+ (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>; 649263320Sdim+ 650263320Sdim+ // fmovd<cond> (%icc|%xcc|%fcc0), $rs2, $rd 651263320Sdim+ def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg), 652263320Sdim+ ", $rs2, $rd"), 653263320Sdim+ (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>; 654263320Sdim+} 655263320Sdim+ 656263320Sdim+ 657263320Sdim+// Instruction aliases for integer conditional branches and moves. 658263320Sdim+multiclass int_cond_alias<string cond, int condVal> { 659263320Sdim+ 660263320Sdim+ // b<cond> $imm 661263320Sdim+ def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"), 662263320Sdim+ (BCOND brtarget:$imm, condVal)>; 663263320Sdim+ 664263320Sdim+ // b<cond> %xcc, $imm 665263320Sdim+ def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"), 666263320Sdim+ (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>; 667263320Sdim+ 668263320Sdim+ defm : cond_mov_alias<cond, condVal, " %icc", 669263320Sdim+ MOVICCrr, MOVICCri, 670263320Sdim+ FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>; 671263320Sdim+ 672263320Sdim+ defm : cond_mov_alias<cond, condVal, " %xcc", 673263320Sdim+ MOVXCCrr, MOVXCCri, 674263320Sdim+ FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>; 675263320Sdim+ 676263320Sdim+ // fmovq<cond> (%icc|%xcc), $rs2, $rd 677263320Sdim+ def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"), 678263320Sdim+ (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, 679263320Sdim+ Requires<[HasV9, HasHardQuad]>; 680263320Sdim+ def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"), 681263320Sdim+ (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, 682263320Sdim+ Requires<[Is64Bit, HasHardQuad]>; 683263320Sdim+ 684263320Sdim+} 685263320Sdim+ 686263320Sdim+ 687263320Sdim+// Instruction aliases for floating point conditional branches and moves. 688263320Sdim+multiclass fp_cond_alias<string cond, int condVal> { 689263320Sdim+ 690263320Sdim+ // fb<cond> $imm 691263320Sdim+ def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"), 692263320Sdim+ (FBCOND brtarget:$imm, condVal), 0>; 693263320Sdim+ 694263320Sdim+ defm : cond_mov_alias<cond, condVal, " %fcc0", 695263320Sdim+ MOVFCCrr, MOVFCCri, 696263320Sdim+ FMOVS_FCC, FMOVD_FCC>, Requires<[HasV9]>; 697263320Sdim+ 698263320Sdim+ // fmovq<cond> %fcc0, $rs2, $rd 699263320Sdim+ def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %fcc0, $rs2, $rd"), 700263320Sdim+ (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>, 701263320Sdim+ Requires<[HasV9, HasHardQuad]>; 702263320Sdim+} 703263320Sdim+ 704263320Sdim+defm : int_cond_alias<"a", 0b1000>; 705263320Sdim+defm : int_cond_alias<"n", 0b0000>; 706263320Sdim+defm : int_cond_alias<"ne", 0b1001>; 707263320Sdim+defm : int_cond_alias<"e", 0b0001>; 708263320Sdim+defm : int_cond_alias<"g", 0b1010>; 709263320Sdim+defm : int_cond_alias<"le", 0b0010>; 710263320Sdim+defm : int_cond_alias<"ge", 0b1011>; 711263320Sdim+defm : int_cond_alias<"l", 0b0011>; 712263320Sdim+defm : int_cond_alias<"gu", 0b1100>; 713263320Sdim+defm : int_cond_alias<"leu", 0b0100>; 714263320Sdim+defm : int_cond_alias<"cc", 0b1101>; 715263320Sdim+defm : int_cond_alias<"cs", 0b0101>; 716263320Sdim+defm : int_cond_alias<"pos", 0b1110>; 717263320Sdim+defm : int_cond_alias<"neg", 0b0110>; 718263320Sdim+defm : int_cond_alias<"vc", 0b1111>; 719263320Sdim+defm : int_cond_alias<"vs", 0b0111>; 720263320Sdim+ 721263320Sdim+defm : fp_cond_alias<"u", 0b0111>; 722263320Sdim+defm : fp_cond_alias<"g", 0b0110>; 723263320Sdim+defm : fp_cond_alias<"ug", 0b0101>; 724263320Sdim+defm : fp_cond_alias<"l", 0b0100>; 725263320Sdim+defm : fp_cond_alias<"ul", 0b0011>; 726263320Sdim+defm : fp_cond_alias<"lg", 0b0010>; 727263320Sdim+defm : fp_cond_alias<"ne", 0b0001>; 728263320Sdim+defm : fp_cond_alias<"e", 0b1001>; 729263320Sdim+defm : fp_cond_alias<"ue", 0b1010>; 730263320Sdim+defm : fp_cond_alias<"ge", 0b1011>; 731263320Sdim+defm : fp_cond_alias<"uge", 0b1100>; 732263320Sdim+defm : fp_cond_alias<"le", 0b1101>; 733263320Sdim+defm : fp_cond_alias<"ule", 0b1110>; 734263320Sdim+defm : fp_cond_alias<"o", 0b1111>; 735