XCoreRegisterInfo.cpp revision 223017
1235267Sgabor//===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===// 2235267Sgabor// 3235267Sgabor// The LLVM Compiler Infrastructure 4235267Sgabor// 5251245Sgabor// This file is distributed under the University of Illinois Open Source 6235267Sgabor// License. See LICENSE.TXT for details. 7235267Sgabor// 8235267Sgabor//===----------------------------------------------------------------------===// 9235267Sgabor// 10235267Sgabor// This file contains the XCore implementation of the MRegisterInfo class. 11235267Sgabor// 12235267Sgabor//===----------------------------------------------------------------------===// 13235267Sgabor 14235267Sgabor#include "XCoreRegisterInfo.h" 15235267Sgabor#include "XCoreMachineFunctionInfo.h" 16235267Sgabor#include "XCore.h" 17235267Sgabor#include "llvm/CodeGen/MachineInstrBuilder.h" 18235267Sgabor#include "llvm/CodeGen/MachineFunction.h" 19235267Sgabor#include "llvm/CodeGen/MachineFrameInfo.h" 20235267Sgabor#include "llvm/CodeGen/MachineLocation.h" 21235267Sgabor#include "llvm/CodeGen/MachineModuleInfo.h" 22235267Sgabor#include "llvm/CodeGen/MachineRegisterInfo.h" 23235267Sgabor#include "llvm/CodeGen/RegisterScavenging.h" 24235267Sgabor#include "llvm/Target/TargetFrameLowering.h" 25235267Sgabor#include "llvm/Target/TargetMachine.h" 26235267Sgabor#include "llvm/Target/TargetOptions.h" 27235267Sgabor#include "llvm/Target/TargetInstrInfo.h" 28235267Sgabor#include "llvm/Type.h" 29235267Sgabor#include "llvm/Function.h" 30235267Sgabor#include "llvm/ADT/BitVector.h" 31265160Spfg#include "llvm/ADT/STLExtras.h" 32235267Sgabor#include "llvm/Support/Debug.h" 33235267Sgabor#include "llvm/Support/ErrorHandling.h" 34235267Sgabor#include "llvm/Support/raw_ostream.h" 35235267Sgabor 36235267Sgaborusing namespace llvm; 37235267Sgabor 38235267SgaborXCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii) 39235267Sgabor : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), 40235267Sgabor TII(tii) { 41235267Sgabor} 42265160Spfg 43265160Spfg// helper functions 44238108Sgaborstatic inline bool isImmUs(unsigned val) { 45235267Sgabor return val <= 11; 46235267Sgabor} 47235267Sgabor 48235267Sgaborstatic inline bool isImmU6(unsigned val) { 49235267Sgabor return val < (1 << 6); 50235267Sgabor} 51235267Sgabor 52235267Sgaborstatic inline bool isImmU16(unsigned val) { 53235267Sgabor return val < (1 << 16); 54235267Sgabor} 55235267Sgabor 56235267Sgaborstatic const unsigned XCore_ArgRegs[] = { 57235267Sgabor XCore::R0, XCore::R1, XCore::R2, XCore::R3 58235267Sgabor}; 59235267Sgabor 60235267Sgaborconst unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF) 61235267Sgabor{ 62235267Sgabor return XCore_ArgRegs; 63235267Sgabor} 64235267Sgabor 65235267Sgaborunsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF) 66235267Sgabor{ 67235267Sgabor return array_lengthof(XCore_ArgRegs); 68242430Sgabor} 69242430Sgabor 70235267Sgaborbool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) { 71235267Sgabor return MF.getMMI().hasDebugInfo() || 72235267Sgabor MF.getFunction()->needsUnwindTableEntry(); 73235267Sgabor} 74235267Sgabor 75235267Sgaborconst unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) 76235267Sgabor const { 77235267Sgabor static const unsigned CalleeSavedRegs[] = { 78235267Sgabor XCore::R4, XCore::R5, XCore::R6, XCore::R7, 79235267Sgabor XCore::R8, XCore::R9, XCore::R10, XCore::LR, 80235987Sgabor 0 81235987Sgabor }; 82235987Sgabor return CalleeSavedRegs; 83235267Sgabor} 84235267Sgabor 85235267SgaborBitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 86235267Sgabor BitVector Reserved(getNumRegs()); 87235267Sgabor const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 88235267Sgabor 89235267Sgabor Reserved.set(XCore::CP); 90235267Sgabor Reserved.set(XCore::DP); 91235267Sgabor Reserved.set(XCore::SP); 92235267Sgabor Reserved.set(XCore::LR); 93235267Sgabor if (TFI->hasFP(MF)) { 94235267Sgabor Reserved.set(XCore::R10); 95235267Sgabor } 96235267Sgabor return Reserved; 97235267Sgabor} 98235267Sgabor 99235267Sgaborbool 100235267SgaborXCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { 101235267Sgabor const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 102235267Sgabor 103235267Sgabor // TODO can we estimate stack size? 104235267Sgabor return TFI->hasFP(MF); 105235267Sgabor} 106235267Sgabor 107235267Sgaborbool 108235267SgaborXCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { 109235267Sgabor return false; 110235267Sgabor} 111235267Sgabor 112235267Sgabor// This function eliminates ADJCALLSTACKDOWN, 113235267Sgabor// ADJCALLSTACKUP pseudo instructions 114235267Sgaborvoid XCoreRegisterInfo:: 115235267SgaboreliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 116235267Sgabor MachineBasicBlock::iterator I) const { 117235267Sgabor const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 118235267Sgabor 119235267Sgabor if (!TFI->hasReservedCallFrame(MF)) { 120235267Sgabor // Turn the adjcallstackdown instruction into 'extsp <amt>' and the 121235267Sgabor // adjcallstackup instruction into 'ldaw sp, sp[<amt>]' 122235267Sgabor MachineInstr *Old = I; 123235267Sgabor uint64_t Amount = Old->getOperand(0).getImm(); 124235267Sgabor if (Amount != 0) { 125235267Sgabor // We need to keep the stack aligned properly. To do this, we round the 126235267Sgabor // amount of space needed for the outgoing arguments up to the next 127 // alignment boundary. 128 unsigned Align = TFI->getStackAlignment(); 129 Amount = (Amount+Align-1)/Align*Align; 130 131 assert(Amount%4 == 0); 132 Amount /= 4; 133 134 bool isU6 = isImmU6(Amount); 135 if (!isU6 && !isImmU16(Amount)) { 136 // FIX could emit multiple instructions in this case. 137#ifndef NDEBUG 138 errs() << "eliminateCallFramePseudoInstr size too big: " 139 << Amount << "\n"; 140#endif 141 llvm_unreachable(0); 142 } 143 144 MachineInstr *New; 145 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) { 146 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; 147 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode)) 148 .addImm(Amount); 149 } else { 150 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP); 151 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; 152 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP) 153 .addImm(Amount); 154 } 155 156 // Replace the pseudo instruction with a new instruction... 157 MBB.insert(I, New); 158 } 159 } 160 161 MBB.erase(I); 162} 163 164void 165XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 166 int SPAdj, RegScavenger *RS) const { 167 assert(SPAdj == 0 && "Unexpected"); 168 MachineInstr &MI = *II; 169 DebugLoc dl = MI.getDebugLoc(); 170 unsigned i = 0; 171 172 while (!MI.getOperand(i).isFI()) { 173 ++i; 174 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 175 } 176 177 MachineOperand &FrameOp = MI.getOperand(i); 178 int FrameIndex = FrameOp.getIndex(); 179 180 MachineFunction &MF = *MI.getParent()->getParent(); 181 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 182 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 183 int StackSize = MF.getFrameInfo()->getStackSize(); 184 185 #ifndef NDEBUG 186 DEBUG(errs() << "\nFunction : " 187 << MF.getFunction()->getName() << "\n"); 188 DEBUG(errs() << "<--------->\n"); 189 DEBUG(MI.print(errs())); 190 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n"); 191 DEBUG(errs() << "FrameOffset : " << Offset << "\n"); 192 DEBUG(errs() << "StackSize : " << StackSize << "\n"); 193 #endif 194 195 Offset += StackSize; 196 197 // fold constant into offset. 198 Offset += MI.getOperand(i + 1).getImm(); 199 MI.getOperand(i + 1).ChangeToImmediate(0); 200 201 assert(Offset%4 == 0 && "Misaligned stack offset"); 202 203 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n"); 204 205 Offset/=4; 206 207 bool FP = TFI->hasFP(MF); 208 209 unsigned Reg = MI.getOperand(0).getReg(); 210 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill(); 211 212 assert(XCore::GRRegsRegisterClass->contains(Reg) && 213 "Unexpected register operand"); 214 215 MachineBasicBlock &MBB = *MI.getParent(); 216 217 if (FP) { 218 bool isUs = isImmUs(Offset); 219 unsigned FramePtr = XCore::R10; 220 221 if (!isUs) { 222 if (!RS) 223 report_fatal_error("eliminateFrameIndex Frame size too big: " + 224 Twine(Offset)); 225 unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II, 226 SPAdj); 227 loadConstant(MBB, II, ScratchReg, Offset, dl); 228 switch (MI.getOpcode()) { 229 case XCore::LDWFI: 230 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg) 231 .addReg(FramePtr) 232 .addReg(ScratchReg, RegState::Kill); 233 break; 234 case XCore::STWFI: 235 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r)) 236 .addReg(Reg, getKillRegState(isKill)) 237 .addReg(FramePtr) 238 .addReg(ScratchReg, RegState::Kill); 239 break; 240 case XCore::LDAWFI: 241 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg) 242 .addReg(FramePtr) 243 .addReg(ScratchReg, RegState::Kill); 244 break; 245 default: 246 llvm_unreachable("Unexpected Opcode"); 247 } 248 } else { 249 switch (MI.getOpcode()) { 250 case XCore::LDWFI: 251 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) 252 .addReg(FramePtr) 253 .addImm(Offset); 254 break; 255 case XCore::STWFI: 256 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)) 257 .addReg(Reg, getKillRegState(isKill)) 258 .addReg(FramePtr) 259 .addImm(Offset); 260 break; 261 case XCore::LDAWFI: 262 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg) 263 .addReg(FramePtr) 264 .addImm(Offset); 265 break; 266 default: 267 llvm_unreachable("Unexpected Opcode"); 268 } 269 } 270 } else { 271 bool isU6 = isImmU6(Offset); 272 if (!isU6 && !isImmU16(Offset)) 273 report_fatal_error("eliminateFrameIndex Frame size too big: " + 274 Twine(Offset)); 275 276 switch (MI.getOpcode()) { 277 int NewOpcode; 278 case XCore::LDWFI: 279 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; 280 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) 281 .addImm(Offset); 282 break; 283 case XCore::STWFI: 284 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; 285 BuildMI(MBB, II, dl, TII.get(NewOpcode)) 286 .addReg(Reg, getKillRegState(isKill)) 287 .addImm(Offset); 288 break; 289 case XCore::LDAWFI: 290 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; 291 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) 292 .addImm(Offset); 293 break; 294 default: 295 llvm_unreachable("Unexpected Opcode"); 296 } 297 } 298 // Erase old instruction. 299 MBB.erase(II); 300} 301 302void XCoreRegisterInfo:: 303loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 304 unsigned DstReg, int64_t Value, DebugLoc dl) const { 305 // TODO use mkmsk if possible. 306 if (!isImmU16(Value)) { 307 // TODO use constant pool. 308 report_fatal_error("loadConstant value too big " + Twine(Value)); 309 } 310 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6; 311 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value); 312} 313 314int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { 315 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); 316} 317 318int XCoreRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { 319 return XCoreGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); 320} 321 322unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 323 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 324 325 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP; 326} 327 328unsigned XCoreRegisterInfo::getRARegister() const { 329 return XCore::LR; 330} 331 332#include "XCoreGenRegisterInfo.inc" 333 334