XCoreInstrInfo.td revision 249423
1//===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the XCore instructions in TableGen format. 11// 12//===----------------------------------------------------------------------===// 13 14// Uses of CP, DP are not currently reflected in the patterns, since 15// having a physical register as an operand prevents loop hoisting and 16// since the value of these registers never changes during the life of the 17// function. 18 19//===----------------------------------------------------------------------===// 20// Instruction format superclass. 21//===----------------------------------------------------------------------===// 22 23include "XCoreInstrFormats.td" 24 25//===----------------------------------------------------------------------===// 26// XCore specific DAG Nodes. 27// 28 29// Call 30def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 31def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink, 32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 33 SDNPVariadic]>; 34 35def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind, 36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>; 37 38def SDT_XCoreBR_JT : SDTypeProfile<0, 2, 39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 40 41def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT, 42 [SDNPHasChain]>; 43 44def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT, 45 [SDNPHasChain]>; 46 47def SDT_XCoreAddress : SDTypeProfile<1, 1, 48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 49 50def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, 51 []>; 52 53def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, 54 []>; 55 56def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, 57 []>; 58 59def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; 60def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, 61 [SDNPHasChain, SDNPMayStore]>; 62 63// These are target-independent nodes, but have target-specific formats. 64def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 65def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 66 SDTCisVT<1, i32> ]>; 67 68def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart, 69 [SDNPHasChain, SDNPOutGlue]>; 70def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd, 71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 72 73//===----------------------------------------------------------------------===// 74// Instruction Pattern Stuff 75//===----------------------------------------------------------------------===// 76 77def div4_xform : SDNodeXForm<imm, [{ 78 // Transformation function: imm/4 79 assert(N->getZExtValue() % 4 == 0); 80 return getI32Imm(N->getZExtValue()/4); 81}]>; 82 83def msksize_xform : SDNodeXForm<imm, [{ 84 // Transformation function: get the size of a mask 85 assert(isMask_32(N->getZExtValue())); 86 // look for the first non-zero bit 87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue())); 88}]>; 89 90def neg_xform : SDNodeXForm<imm, [{ 91 // Transformation function: -imm 92 uint32_t value = N->getZExtValue(); 93 return getI32Imm(-value); 94}]>; 95 96def bpwsub_xform : SDNodeXForm<imm, [{ 97 // Transformation function: 32-imm 98 uint32_t value = N->getZExtValue(); 99 return getI32Imm(32-value); 100}]>; 101 102def div4neg_xform : SDNodeXForm<imm, [{ 103 // Transformation function: -imm/4 104 uint32_t value = N->getZExtValue(); 105 assert(-value % 4 == 0); 106 return getI32Imm(-value/4); 107}]>; 108 109def immUs4Neg : PatLeaf<(imm), [{ 110 uint32_t value = (uint32_t)N->getZExtValue(); 111 return (-value)%4 == 0 && (-value)/4 <= 11; 112}]>; 113 114def immUs4 : PatLeaf<(imm), [{ 115 uint32_t value = (uint32_t)N->getZExtValue(); 116 return value%4 == 0 && value/4 <= 11; 117}]>; 118 119def immUsNeg : PatLeaf<(imm), [{ 120 return -((uint32_t)N->getZExtValue()) <= 11; 121}]>; 122 123def immUs : PatLeaf<(imm), [{ 124 return (uint32_t)N->getZExtValue() <= 11; 125}]>; 126 127def immU6 : PatLeaf<(imm), [{ 128 return (uint32_t)N->getZExtValue() < (1 << 6); 129}]>; 130 131def immU10 : PatLeaf<(imm), [{ 132 return (uint32_t)N->getZExtValue() < (1 << 10); 133}]>; 134 135def immU16 : PatLeaf<(imm), [{ 136 return (uint32_t)N->getZExtValue() < (1 << 16); 137}]>; 138 139def immU20 : PatLeaf<(imm), [{ 140 return (uint32_t)N->getZExtValue() < (1 << 20); 141}]>; 142 143def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>; 144 145def immBitp : PatLeaf<(imm), [{ 146 uint32_t value = (uint32_t)N->getZExtValue(); 147 return (value >= 1 && value <= 8) 148 || value == 16 149 || value == 24 150 || value == 32; 151}]>; 152 153def immBpwSubBitp : PatLeaf<(imm), [{ 154 uint32_t value = (uint32_t)N->getZExtValue(); 155 return (value >= 24 && value <= 31) 156 || value == 16 157 || value == 8 158 || value == 0; 159}]>; 160 161def lda16f : PatFrag<(ops node:$addr, node:$offset), 162 (add node:$addr, (shl node:$offset, 1))>; 163def lda16b : PatFrag<(ops node:$addr, node:$offset), 164 (sub node:$addr, (shl node:$offset, 1))>; 165def ldawf : PatFrag<(ops node:$addr, node:$offset), 166 (add node:$addr, (shl node:$offset, 2))>; 167def ldawb : PatFrag<(ops node:$addr, node:$offset), 168 (sub node:$addr, (shl node:$offset, 2))>; 169 170// Instruction operand types 171def calltarget : Operand<i32>; 172def brtarget : Operand<OtherVT>; 173def pclabel : Operand<i32>; 174 175// Addressing modes 176def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>; 177def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper], 178 []>; 179def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper], 180 []>; 181 182// Address operands 183def MEMii : Operand<i32> { 184 let PrintMethod = "printMemOperand"; 185 let DecoderMethod = "DecodeMEMiiOperand"; 186 let MIOperandInfo = (ops i32imm, i32imm); 187} 188 189// Jump tables. 190def InlineJT : Operand<i32> { 191 let PrintMethod = "printInlineJT"; 192} 193 194def InlineJT32 : Operand<i32> { 195 let PrintMethod = "printInlineJT32"; 196} 197 198//===----------------------------------------------------------------------===// 199// Instruction Class Templates 200//===----------------------------------------------------------------------===// 201 202// Three operand short 203 204multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> { 205 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 206 !strconcat(OpcStr, " $dst, $b, $c"), 207 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 208 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 209 !strconcat(OpcStr, " $dst, $b, $c"), 210 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 211} 212 213multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> { 214 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 215 !strconcat(OpcStr, " $dst, $b, $c"), []>; 216 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 217 !strconcat(OpcStr, " $dst, $b, $c"), []>; 218} 219 220multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr, 221 SDNode OpNode> { 222 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 223 !strconcat(OpcStr, " $dst, $b, $c"), 224 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 225 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 226 !strconcat(OpcStr, " $dst, $b, $c"), 227 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 228} 229 230class F3R<bits<5> opc, string OpcStr, SDNode OpNode> : 231 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 232 !strconcat(OpcStr, " $dst, $b, $c"), 233 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 234 235class F3R_np<bits<5> opc, string OpcStr> : 236 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 237 !strconcat(OpcStr, " $dst, $b, $c"), []>; 238// Three operand long 239 240/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 241multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr, 242 SDNode OpNode> { 243 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 244 !strconcat(OpcStr, " $dst, $b, $c"), 245 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 246 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 247 !strconcat(OpcStr, " $dst, $b, $c"), 248 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>; 249} 250 251/// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot. 252multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr, 253 SDNode OpNode> { 254 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 255 !strconcat(OpcStr, " $dst, $b, $c"), 256 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 257 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c), 258 !strconcat(OpcStr, " $dst, $b, $c"), 259 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>; 260} 261 262class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> : 263 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c), 264 !strconcat(OpcStr, " $dst, $b, $c"), 265 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>; 266 267// Register - U6 268// Operand register - U6 269multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> { 270 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 271 !strconcat(OpcStr, " $a, $b"), []>; 272 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 273 !strconcat(OpcStr, " $a, $b"), []>; 274} 275 276multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> { 277 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 278 !strconcat(OpcStr, " $a, -$b"), []>; 279 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b), 280 !strconcat(OpcStr, " $a, -$b"), []>; 281} 282 283multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> { 284 def _ru6: _FRU6<opc, (outs RRegs:$a), (ins i32imm:$b), 285 !strconcat(OpcStr, " $a, cp[$b]"), []>; 286 def _lru6: _FLRU6<opc, (outs RRegs:$a), (ins i32imm:$b), 287 !strconcat(OpcStr, " $a, cp[$b]"), []>; 288} 289 290// U6 291multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> { 292 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 293 [(OpNode immU6:$a)]>; 294 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 295 [(OpNode immU16:$a)]>; 296} 297 298multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> { 299 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 300 [(Int immU6:$a)]>; 301 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), 302 [(Int immU16:$a)]>; 303} 304 305multiclass FU6_LU6_np<bits<10> opc, string OpcStr> { 306 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 307 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>; 308} 309 310// Two operand short 311 312class F2R_np<bits<6> opc, string OpcStr> : 313 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b), 314 !strconcat(OpcStr, " $dst, $b"), []>; 315 316// Two operand long 317 318//===----------------------------------------------------------------------===// 319// Pseudo Instructions 320//===----------------------------------------------------------------------===// 321 322let Defs = [SP], Uses = [SP] in { 323def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt), 324 "# ADJCALLSTACKDOWN $amt", 325 [(callseq_start timm:$amt)]>; 326def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2), 327 "# ADJCALLSTACKUP $amt1", 328 [(callseq_end timm:$amt1, timm:$amt2)]>; 329} 330 331def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 332 "# LDWFI $dst, $addr", 333 [(set GRRegs:$dst, (load ADDRspii:$addr))]>; 334 335def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr), 336 "# LDAWFI $dst, $addr", 337 [(set GRRegs:$dst, ADDRspii:$addr)]>; 338 339def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr), 340 "# STWFI $src, $addr", 341 [(store GRRegs:$src, ADDRspii:$addr)]>; 342 343// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 344// instruction selection into a branch sequence. 345let usesCustomInserter = 1 in { 346 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst), 347 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F), 348 "# SELECT_CC PSEUDO!", 349 [(set GRRegs:$dst, 350 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>; 351} 352 353//===----------------------------------------------------------------------===// 354// Instructions 355//===----------------------------------------------------------------------===// 356 357// Three operand short 358defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>; 359defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>; 360let neverHasSideEffects = 1 in { 361defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">; 362def LSS_3r : F3R_np<0b11000, "lss">; 363def LSU_3r : F3R_np<0b11001, "lsu">; 364} 365def AND_3r : F3R<0b00111, "and", and>; 366def OR_3r : F3R<0b01000, "or", or>; 367 368let mayLoad=1 in { 369def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst), 370 (ins GRRegs:$addr, GRRegs:$offset), 371 "ldw $dst, $addr[$offset]", []>; 372 373def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst), 374 (ins GRRegs:$addr, i32imm:$offset), 375 "ldw $dst, $addr[$offset]", []>; 376 377def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst), 378 (ins GRRegs:$addr, GRRegs:$offset), 379 "ld16s $dst, $addr[$offset]", []>; 380 381def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst), 382 (ins GRRegs:$addr, GRRegs:$offset), 383 "ld8u $dst, $addr[$offset]", []>; 384} 385 386let mayStore=1 in { 387def STW_l3r : _FL3R<0b000001100, (outs), 388 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 389 "stw $val, $addr[$offset]", []>; 390 391def STW_2rus : _F2RUS<0b0000, (outs), 392 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset), 393 "stw $val, $addr[$offset]", []>; 394} 395 396defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>; 397defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>; 398 399// The first operand is treated as an immediate since it refers to a register 400// number in another thread. 401def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c), 402 "set t[$c]:r$a, $b", []>; 403 404// Three operand long 405def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst), 406 (ins GRRegs:$addr, GRRegs:$offset), 407 "ldaw $dst, $addr[$offset]", 408 [(set GRRegs:$dst, 409 (ldawf GRRegs:$addr, GRRegs:$offset))]>; 410 411let neverHasSideEffects = 1 in 412def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst), 413 (ins GRRegs:$addr, i32imm:$offset), 414 "ldaw $dst, $addr[$offset]", []>; 415 416def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst), 417 (ins GRRegs:$addr, GRRegs:$offset), 418 "ldaw $dst, $addr[-$offset]", 419 [(set GRRegs:$dst, 420 (ldawb GRRegs:$addr, GRRegs:$offset))]>; 421 422let neverHasSideEffects = 1 in 423def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst), 424 (ins GRRegs:$addr, i32imm:$offset), 425 "ldaw $dst, $addr[-$offset]", []>; 426 427def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst), 428 (ins GRRegs:$addr, GRRegs:$offset), 429 "lda16 $dst, $addr[$offset]", 430 [(set GRRegs:$dst, 431 (lda16f GRRegs:$addr, GRRegs:$offset))]>; 432 433def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst), 434 (ins GRRegs:$addr, GRRegs:$offset), 435 "lda16 $dst, $addr[-$offset]", 436 [(set GRRegs:$dst, 437 (lda16b GRRegs:$addr, GRRegs:$offset))]>; 438 439def MUL_l3r : FL3R<0b001111100, "mul", mul>; 440// Instructions which may trap are marked as side effecting. 441let hasSideEffects = 1 in { 442def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>; 443def DIVU_l3r : FL3R<0b010011100, "divu", udiv>; 444def REMS_l3r : FL3R<0b110001100, "rems", srem>; 445def REMU_l3r : FL3R<0b110011100, "remu", urem>; 446} 447def XOR_l3r : FL3R<0b000011100, "xor", xor>; 448defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>; 449 450let Constraints = "$src1 = $dst" in 451def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst), 452 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 453 "crc32 $dst, $src2, $src3", 454 [(set GRRegs:$dst, 455 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, 456 GRRegs:$src3))]>; 457 458let mayStore=1 in { 459def ST16_l3r : _FL3R<0b100001100, (outs), 460 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 461 "st16 $val, $addr[$offset]", []>; 462 463def ST8_l3r : _FL3R<0b100011100, (outs), 464 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), 465 "st8 $val, $addr[$offset]", []>; 466} 467 468def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a), 469 (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c", 470 []>; 471 472def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs), 473 (ins GRRegs:$a, GRRegs:$b, i32imm:$c), 474 "outpw res[$b], $a, $c", []>; 475 476// Four operand long 477let Constraints = "$e = $a,$f = $b" in { 478def MACCU_l4r : _FL4RSrcDstSrcDst< 479 0b000001, (outs GRRegs:$a, GRRegs:$b), 480 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>; 481 482def MACCS_l4r : _FL4RSrcDstSrcDst< 483 0b000010, (outs GRRegs:$a, GRRegs:$b), 484 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>; 485} 486 487let Constraints = "$e = $b" in 488def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b), 489 (ins GRRegs:$e, GRRegs:$c, GRRegs:$d), 490 "crc8 $b, $a, $c, $d", []>; 491 492// Five operand long 493 494def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2), 495 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 496 "ladd $dst2, $dst1, $src1, $src2, $src3", 497 []>; 498 499def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2), 500 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 501 "lsub $dst2, $dst1, $src1, $src2, $src3", []>; 502 503def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2), 504 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), 505 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>; 506 507// Six operand long 508 509def LMUL_l6r : _FL6R< 510 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2), 511 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4), 512 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>; 513 514// Register - U6 515 516//let Uses = [DP] in ... 517let neverHasSideEffects = 1, isReMaterializable = 1 in 518def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins MEMii:$b), 519 "ldaw $a, dp[$b]", []>; 520 521let isReMaterializable = 1 in 522def LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins MEMii:$b), 523 "ldaw $a, dp[$b]", 524 [(set RRegs:$a, ADDRdpii:$b)]>; 525 526let mayLoad=1 in 527def LDWDP_ru6: _FRU6<0b010110, (outs RRegs:$a), (ins MEMii:$b), 528 "ldw $a, dp[$b]", []>; 529 530def LDWDP_lru6: _FLRU6<0b010110, (outs RRegs:$a), (ins MEMii:$b), 531 "ldw $a, dp[$b]", 532 [(set RRegs:$a, (load ADDRdpii:$b))]>; 533 534let mayStore=1 in 535def STWDP_ru6 : _FRU6<0b010100, (outs), (ins RRegs:$a, MEMii:$b), 536 "stw $a, dp[$b]", []>; 537 538def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, MEMii:$b), 539 "stw $a, dp[$b]", 540 [(store RRegs:$a, ADDRdpii:$b)]>; 541 542//let Uses = [CP] in .. 543let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in 544defm LDWCP : FRU6_LRU6_cp<0b011011, "ldw">; 545 546let Uses = [SP] in { 547let mayStore=1 in { 548def STWSP_ru6 : _FRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), 549 "stw $a, sp[$b]", 550 [(XCoreStwsp RRegs:$a, immU6:$b)]>; 551 552def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b), 553 "stw $a, sp[$b]", 554 [(XCoreStwsp RRegs:$a, immU16:$b)]>; 555} 556 557let mayLoad=1 in { 558def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), 559 "ldw $a, sp[$b]", []>; 560 561def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b), 562 "ldw $a, sp[$b]", []>; 563} 564 565let neverHasSideEffects = 1 in { 566def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 567 "ldaw $a, sp[$b]", []>; 568 569def LDAWSP_lru6 : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), 570 "ldaw $a, sp[$b]", []>; 571} 572} 573 574let isReMaterializable = 1 in { 575def LDC_ru6 : _FRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), 576 "ldc $a, $b", [(set RRegs:$a, immU6:$b)]>; 577 578def LDC_lru6 : _FLRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b), 579 "ldc $a, $b", [(set RRegs:$a, immU16:$b)]>; 580} 581 582def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 583 "setc res[$a], $b", 584 [(int_xcore_setc GRRegs:$a, immU6:$b)]>; 585 586def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), 587 "setc res[$a], $b", 588 [(int_xcore_setc GRRegs:$a, immU16:$b)]>; 589 590// Operand register - U6 591let isBranch = 1, isTerminator = 1 in { 592defm BRFT: FRU6_LRU6_branch<0b011100, "bt">; 593defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">; 594defm BRFF: FRU6_LRU6_branch<0b011110, "bf">; 595defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">; 596} 597 598// U6 599let Defs = [SP], Uses = [SP] in { 600let neverHasSideEffects = 1 in 601defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">; 602 603let mayStore = 1 in 604defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">; 605 606let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in { 607defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>; 608} 609} 610 611let neverHasSideEffects = 1 in 612defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">; 613 614let Uses = [R11], isCall=1 in 615defm BLAT : FU6_LU6_np<0b0111001101, "blat">; 616 617let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 618def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>; 619 620def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>; 621 622def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 623 624def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>; 625} 626 627//let Uses = [CP] in ... 628let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in 629def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]", 630 []>; 631 632let Defs = [R11], isReMaterializable = 1 in 633def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]", 634 [(set R11, ADDRcpii:$a)]>; 635 636let Defs = [R11] in 637defm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">; 638 639defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>; 640 641defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>; 642 643// setsr may cause a branch if it is used to enable events. clrsr may 644// branch if it is executed while events are enabled. 645let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 646 isCodeGenOnly = 1 in { 647defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">; 648defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">; 649} 650 651defm KCALL : FU6_LU6_np<0b0111001111, "kcall">; 652 653let Uses = [SP], Defs = [SP], mayStore = 1 in 654defm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">; 655 656let Uses = [SP], Defs = [SP], mayLoad = 1 in 657defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">; 658 659// U10 660 661let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in 662def LDAPF_u10 : _FU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", []>; 663 664let Defs = [R11], isReMaterializable = 1 in 665def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", 666 [(set R11, (pcrelwrapper tglobaladdr:$a))]>; 667 668let Defs = [R11], isReMaterializable = 1, isCodeGenOnly = 1 in 669def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", 670 [(set R11, (pcrelwrapper tblockaddress:$a))]>; 671 672let isCall=1, 673// All calls clobber the link register and the non-callee-saved registers: 674Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 675def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 676 677def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>; 678 679def BLRF_u10 : _FU10<0b110100, (outs), (ins calltarget:$a), "bl $a", 680 [(XCoreBranchLink immU10:$a)]>; 681 682def BLRF_lu10 : _FLU10<0b110100, (outs), (ins calltarget:$a), "bl $a", 683 [(XCoreBranchLink immU20:$a)]>; 684} 685 686let Defs = [R11], mayLoad = 1, isReMaterializable = 1, 687 neverHasSideEffects = 1 in { 688def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>; 689 690def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", 691 []>; 692} 693 694// Two operand short 695def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b), 696 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>; 697 698def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b), 699 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>; 700 701let Constraints = "$src1 = $dst" in { 702def SEXT_rus : 703 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 704 "sext $dst, $src2", 705 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, 706 immBitp:$src2))]>; 707 708def SEXT_2r : 709 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 710 "sext $dst, $src2", 711 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>; 712 713def ZEXT_rus : 714 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2), 715 "zext $dst, $src2", 716 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, 717 immBitp:$src2))]>; 718 719def ZEXT_2r : 720 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 721 "zext $dst, $src2", 722 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>; 723 724def ANDNOT_2r : 725 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2), 726 "andnot $dst, $src2", 727 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>; 728} 729 730let isReMaterializable = 1, neverHasSideEffects = 1 in 731def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size), 732 "mkmsk $dst, $size", []>; 733 734def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size), 735 "mkmsk $dst, $size", 736 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>; 737 738def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type), 739 "getr $dst, $type", 740 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>; 741 742def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r), 743 "getts $dst, res[$r]", 744 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>; 745 746def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val), 747 "setpt res[$r], $val", 748 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>; 749 750def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val), 751 "outct res[$r], $val", 752 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>; 753 754def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val), 755 "outct res[$r], $val", 756 [(int_xcore_outct GRRegs:$r, immUs:$val)]>; 757 758def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val), 759 "outt res[$r], $val", 760 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>; 761 762def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val), 763 "out res[$r], $val", 764 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>; 765 766let Constraints = "$src = $dst" in 767def OUTSHR_2r : 768 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 769 "outshr res[$r], $src", 770 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>; 771 772def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r), 773 "inct $dst, res[$r]", 774 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>; 775 776def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r), 777 "int $dst, res[$r]", 778 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>; 779 780def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r), 781 "in $dst, res[$r]", 782 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>; 783 784let Constraints = "$src = $dst" in 785def INSHR_2r : 786 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r), 787 "inshr $dst, res[$r]", 788 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>; 789 790def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val), 791 "chkct res[$r], $val", 792 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>; 793 794def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val), 795 "chkct res[$r], $val", 796 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>; 797 798def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src), 799 "testct $dst, res[$src]", 800 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>; 801 802def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src), 803 "testwct $dst, res[$src]", 804 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>; 805 806def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val), 807 "setd res[$r], $val", 808 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>; 809 810def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 811 "setpsc res[$src1], $src2", 812 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>; 813 814def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r), 815 "getst $dst, res[$r]", 816 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>; 817 818def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t), 819 "init t[$t]:sp, $src", 820 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>; 821 822def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t), 823 "init t[$t]:pc, $src", 824 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>; 825 826def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t), 827 "init t[$t]:cp, $src", 828 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>; 829 830def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t), 831 "init t[$t]:dp, $src", 832 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>; 833 834def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src), 835 "peek $dst, res[$src]", 836 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>; 837 838def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src), 839 "endin $dst, res[$src]", 840 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>; 841 842def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b), 843 "eef $a, res[$b]", []>; 844 845def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b), 846 "eet $a, res[$b]", []>; 847 848def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b), 849 "tsetmr r$a, $b", []>; 850 851// Two operand long 852def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src), 853 "bitrev $dst, $src", 854 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>; 855 856def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src), 857 "byterev $dst, $src", 858 [(set GRRegs:$dst, (bswap GRRegs:$src))]>; 859 860def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src), 861 "clz $dst, $src", 862 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>; 863 864def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src), 865 "getd $dst, res[$src]", []>; 866 867def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src), 868 "getn $dst, res[$src]", []>; 869 870def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val), 871 "setc res[$r], $val", 872 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>; 873 874def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val), 875 "settw res[$r], $val", 876 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>; 877 878def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src), 879 "get $dst, ps[$src]", 880 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>; 881 882def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 883 "set ps[$src1], $src2", 884 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>; 885 886def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t), 887 "init t[$t]:lr, $src", 888 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>; 889 890def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2), 891 "setclk res[$src1], $src2", 892 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>; 893 894def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 895 "setn res[$src1], $src2", []>; 896 897def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2), 898 "setrdy res[$src1], $src2", 899 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>; 900 901def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src), 902 "testlcl $dst, res[$src]", []>; 903 904// One operand short 905def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a), 906 "msync res[$a]", 907 [(int_xcore_msync GRRegs:$a)]>; 908def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a), 909 "mjoin res[$a]", 910 [(int_xcore_mjoin GRRegs:$a)]>; 911 912let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 913def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a), 914 "bau $a", 915 [(brind GRRegs:$a)]>; 916 917let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 918def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i), 919 "bru $i\n$t", 920 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>; 921 922let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 923def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), 924 "bru $i\n$t", 925 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; 926 927let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in 928def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>; 929 930let Defs=[SP], neverHasSideEffects=1 in 931def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>; 932 933let neverHasSideEffects=1 in 934def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>; 935 936let neverHasSideEffects=1 in 937def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>; 938 939let hasCtrlDep = 1 in 940def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a), 941 "ecallt $a", 942 []>; 943 944let hasCtrlDep = 1 in 945def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a), 946 "ecallf $a", 947 []>; 948 949let isCall=1, 950// All calls clobber the link register and the non-callee-saved registers: 951Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { 952def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a), 953 "bla $a", 954 [(XCoreBranchLink GRRegs:$a)]>; 955} 956 957def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a), 958 "syncr res[$a]", 959 [(int_xcore_syncr GRRegs:$a)]>; 960 961def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a), 962 "freer res[$a]", 963 [(int_xcore_freer GRRegs:$a)]>; 964 965let Uses=[R11] in { 966def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a), 967 "setv res[$a], r11", 968 [(int_xcore_setv GRRegs:$a, R11)]>; 969 970def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a), 971 "setev res[$a], r11", 972 [(int_xcore_setev GRRegs:$a, R11)]>; 973} 974 975def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>; 976 977def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", []>; 978 979def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a), 980 "eeu res[$a]", 981 [(int_xcore_eeu GRRegs:$a)]>; 982 983def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>; 984 985def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>; 986 987def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>; 988 989def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>; 990 991def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", []>; 992 993// Zero operand short 994 995def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>; 996 997def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>; 998 999let Defs = [SP], Uses = [SP] in 1000def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>; 1001 1002let Defs = [SP] in 1003def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>; 1004 1005def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>; 1006 1007def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>; 1008 1009let Defs = [R11] in { 1010def GETID_0R : _F0R<0b0001001110, (outs), (ins), 1011 "get r11, id", 1012 [(set R11, (int_xcore_getid))]>; 1013 1014def GETED_0R : _F0R<0b0000111110, (outs), (ins), 1015 "get r11, ed", 1016 [(set R11, (int_xcore_geted))]>; 1017 1018def GETET_0R : _F0R<0b0000111111, (outs), (ins), 1019 "get r11, et", 1020 [(set R11, (int_xcore_getet))]>; 1021 1022def GETKEP_0R : _F0R<0b0001001111, (outs), (ins), 1023 "get r11, kep", []>; 1024 1025def GETKSP_0R : _F0R<0b0001011100, (outs), (ins), 1026 "get r11, ksp", []>; 1027} 1028 1029let Defs = [SP] in 1030def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>; 1031 1032let Uses = [SP], mayLoad = 1 in { 1033def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>; 1034 1035def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>; 1036 1037def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>; 1038 1039def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>; 1040} 1041 1042let Uses=[R11] in 1043def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>; 1044 1045def SSYNC_0r : _F0R<0b0000001110, (outs), (ins), 1046 "ssync", 1047 [(int_xcore_ssync)]>; 1048 1049let Uses = [SP], mayStore = 1 in { 1050def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>; 1051 1052def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>; 1053 1054def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>; 1055 1056def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>; 1057} 1058 1059let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1, 1060 hasSideEffects = 1 in 1061def WAITEU_0R : _F0R<0b0000001100, (outs), (ins), 1062 "waiteu", 1063 [(brind (int_xcore_waitevent))]>; 1064 1065//===----------------------------------------------------------------------===// 1066// Non-Instruction Patterns 1067//===----------------------------------------------------------------------===// 1068 1069def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BLRF_lu10 tglobaladdr:$addr)>; 1070def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>; 1071 1072/// sext_inreg 1073def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>; 1074def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>; 1075def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>; 1076 1077/// loads 1078def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1079 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1080def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1081 1082def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1083 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1084def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1085 1086def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)), 1087 (LDW_3r GRRegs:$addr, GRRegs:$offset)>; 1088def : Pat<(load (add GRRegs:$addr, immUs4:$offset)), 1089 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1090def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>; 1091 1092/// anyext 1093def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)), 1094 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>; 1095def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>; 1096def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)), 1097 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>; 1098def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>; 1099 1100/// stores 1101def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)), 1102 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1103def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr), 1104 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1105 1106def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)), 1107 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1108def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr), 1109 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>; 1110 1111def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)), 1112 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>; 1113def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)), 1114 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>; 1115def : Pat<(store GRRegs:$val, GRRegs:$addr), 1116 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>; 1117 1118/// cttz 1119def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; 1120 1121/// trap 1122def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; 1123 1124/// 1125/// branch patterns 1126/// 1127 1128// unconditional branch 1129def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>; 1130 1131// direct match equal/notequal zero brcond 1132def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst), 1133 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>; 1134def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst), 1135 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>; 1136 1137def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1138 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1139def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1140 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>; 1141def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1142 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1143def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1144 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1145def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst), 1146 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>; 1147def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst), 1148 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>; 1149 1150// generic brcond pattern 1151def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>; 1152 1153 1154/// 1155/// Select patterns 1156/// 1157 1158// direct match equal/notequal zero select 1159def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1160 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>; 1161 1162def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1163 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>; 1164 1165def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1166 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1167def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1168 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>; 1169def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1170 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1171def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1172 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1173def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F), 1174 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>; 1175def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F), 1176 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>; 1177 1178/// 1179/// setcc patterns, only matched when none of the above brcond 1180/// patterns match 1181/// 1182 1183// setcc 2 register operands 1184def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs), 1185 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1186def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs), 1187 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>; 1188 1189def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs), 1190 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>; 1191def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs), 1192 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>; 1193 1194def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs), 1195 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1196def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs), 1197 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1198 1199def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs), 1200 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>; 1201def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs), 1202 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>; 1203 1204def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs), 1205 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>; 1206 1207def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs), 1208 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>; 1209 1210// setcc reg/imm operands 1211def : Pat<(seteq GRRegs:$lhs, immUs:$rhs), 1212 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>; 1213def : Pat<(setne GRRegs:$lhs, immUs:$rhs), 1214 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>; 1215 1216// misc 1217def : Pat<(add GRRegs:$addr, immUs4:$offset), 1218 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1219 1220def : Pat<(sub GRRegs:$addr, immUs4:$offset), 1221 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>; 1222 1223def : Pat<(and GRRegs:$val, immMskBitp:$mask), 1224 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>; 1225 1226// (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1227def : Pat<(add GRRegs:$src1, immUsNeg:$src2), 1228 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>; 1229 1230def : Pat<(add GRRegs:$src1, immUs4Neg:$src2), 1231 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>; 1232 1233/// 1234/// Some peepholes 1235/// 1236 1237def : Pat<(mul GRRegs:$src, 3), 1238 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>; 1239 1240def : Pat<(mul GRRegs:$src, 5), 1241 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>; 1242 1243def : Pat<(mul GRRegs:$src, -3), 1244 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>; 1245 1246// ashr X, 32 is equivalent to ashr X, 31 on the XCore. 1247def : Pat<(sra GRRegs:$src, 31), 1248 (ASHR_l2rus GRRegs:$src, 32)>; 1249 1250def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst), 1251 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1252 1253// setge X, 0 is canonicalized to setgt X, -1 1254def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst), 1255 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>; 1256 1257def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F), 1258 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>; 1259 1260def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F), 1261 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>; 1262 1263def : Pat<(setgt GRRegs:$lhs, -1), 1264 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>; 1265 1266def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm), 1267 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>; 1268