XCoreInstrInfo.h revision 208599 
1//===- XCoreInstrInfo.h - XCore Instruction Information ---------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the XCore implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef XCOREINSTRUCTIONINFO_H
15#define XCOREINSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "XCoreRegisterInfo.h"
19
20namespace llvm {
21
22class XCoreInstrInfo : public TargetInstrInfoImpl {
23  const XCoreRegisterInfo RI;
24public:
25  XCoreInstrInfo();
26
27  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
28  /// such, whenever a client has an instance of instruction info, it should
29  /// always be able to get register info as well (through this method).
30  ///
31  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
32
33  /// Return true if the instruction is a register to register move and return
34  /// the source and dest operands and their sub-register indices by reference.
35  virtual bool isMoveInstr(const MachineInstr &MI,
36                           unsigned &SrcReg, unsigned &DstReg,
37                           unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
38
39  /// isLoadFromStackSlot - If the specified machine instruction is a direct
40  /// load from a stack slot, return the virtual or physical register number of
41  /// the destination along with the FrameIndex of the loaded stack slot.  If
42  /// not, return 0.  This predicate must return 0 if the instruction has
43  /// any side effects other than loading from the stack slot.
44  virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
45                                       int &FrameIndex) const;
46
47  /// isStoreToStackSlot - If the specified machine instruction is a direct
48  /// store to a stack slot, return the virtual or physical register number of
49  /// the source reg along with the FrameIndex of the loaded stack slot.  If
50  /// not, return 0.  This predicate must return 0 if the instruction has
51  /// any side effects other than storing to the stack slot.
52  virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
53                                      int &FrameIndex) const;
54
55  virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
56                             MachineBasicBlock *&FBB,
57                             SmallVectorImpl<MachineOperand> &Cond,
58                             bool AllowModify) const;
59
60  virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
61                             MachineBasicBlock *FBB,
62                             const SmallVectorImpl<MachineOperand> &Cond) const;
63
64  virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
65
66  virtual bool copyRegToReg(MachineBasicBlock &MBB,
67                            MachineBasicBlock::iterator I,
68                            unsigned DestReg, unsigned SrcReg,
69                            const TargetRegisterClass *DestRC,
70                            const TargetRegisterClass *SrcRC,
71                            DebugLoc DL) const;
72
73  virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
74                                   MachineBasicBlock::iterator MI,
75                                   unsigned SrcReg, bool isKill, int FrameIndex,
76                                   const TargetRegisterClass *RC,
77                                   const TargetRegisterInfo *TRI) const;
78
79  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
80                                    MachineBasicBlock::iterator MI,
81                                    unsigned DestReg, int FrameIndex,
82                                    const TargetRegisterClass *RC,
83                                    const TargetRegisterInfo *TRI) const;
84
85  virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
86                                        MachineBasicBlock::iterator MI,
87                                        const std::vector<CalleeSavedInfo> &CSI,
88                                         const TargetRegisterInfo *TRI) const;
89
90  virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
91                                         MachineBasicBlock::iterator MI,
92                                        const std::vector<CalleeSavedInfo> &CSI,
93                                           const TargetRegisterInfo *TRI) const;
94
95  virtual bool ReverseBranchCondition(
96                            SmallVectorImpl<MachineOperand> &Cond) const;
97};
98
99}
100
101#endif
102