XCoreInstrInfo.h revision 200581
1236024Sraj//===- XCoreInstrInfo.h - XCore Instruction Information ---------*- C++ -*-===// 2236024Sraj// 3236024Sraj// The LLVM Compiler Infrastructure 4236024Sraj// 5236024Sraj// This file is distributed under the University of Illinois Open Source 6236024Sraj// License. See LICENSE.TXT for details. 7236024Sraj// 8236024Sraj//===----------------------------------------------------------------------===// 9236024Sraj// 10236024Sraj// This file contains the XCore implementation of the TargetInstrInfo class. 11236024Sraj// 12236024Sraj//===----------------------------------------------------------------------===// 13236024Sraj 14236024Sraj#ifndef XCOREINSTRUCTIONINFO_H 15236024Sraj#define XCOREINSTRUCTIONINFO_H 16236024Sraj 17236024Sraj#include "llvm/Target/TargetInstrInfo.h" 18236024Sraj#include "XCoreRegisterInfo.h" 19236024Sraj 20236024Srajnamespace llvm { 21236024Sraj 22236024Srajclass XCoreInstrInfo : public TargetInstrInfoImpl { 23236024Sraj const XCoreRegisterInfo RI; 24236024Srajpublic: 25236024Sraj XCoreInstrInfo(); 26236024Sraj 27236024Sraj /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 28236024Sraj /// such, whenever a client has an instance of instruction info, it should 29236024Sraj /// always be able to get register info as well (through this method). 30236024Sraj /// 31236024Sraj virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } 32236024Sraj 33236024Sraj /// Return true if the instruction is a register to register move and return 34236024Sraj /// the source and dest operands and their sub-register indices by reference. 35236024Sraj virtual bool isMoveInstr(const MachineInstr &MI, 36236024Sraj unsigned &SrcReg, unsigned &DstReg, 37236024Sraj unsigned &SrcSubIdx, unsigned &DstSubIdx) const; 38236024Sraj 39236024Sraj /// isLoadFromStackSlot - If the specified machine instruction is a direct 40236024Sraj /// load from a stack slot, return the virtual or physical register number of 41236024Sraj /// the destination along with the FrameIndex of the loaded stack slot. If 42236024Sraj /// not, return 0. This predicate must return 0 if the instruction has 43236024Sraj /// any side effects other than loading from the stack slot. 44236024Sraj virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 45236024Sraj int &FrameIndex) const; 46236024Sraj 47236024Sraj /// isStoreToStackSlot - If the specified machine instruction is a direct 48236024Sraj /// store to a stack slot, return the virtual or physical register number of 49236024Sraj /// the source reg along with the FrameIndex of the loaded stack slot. If 50236024Sraj /// not, return 0. This predicate must return 0 if the instruction has 51236024Sraj /// any side effects other than storing to the stack slot. 52236024Sraj virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 53236024Sraj int &FrameIndex) const; 54236024Sraj 55236024Sraj virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 56236024Sraj MachineBasicBlock *&FBB, 57236024Sraj SmallVectorImpl<MachineOperand> &Cond, 58236024Sraj bool AllowModify) const; 59236024Sraj 60236024Sraj virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 61236024Sraj MachineBasicBlock *FBB, 62236024Sraj const SmallVectorImpl<MachineOperand> &Cond) const; 63236024Sraj 64236024Sraj virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 65236024Sraj 66236024Sraj virtual bool copyRegToReg(MachineBasicBlock &MBB, 67236024Sraj MachineBasicBlock::iterator I, 68236024Sraj unsigned DestReg, unsigned SrcReg, 69236024Sraj const TargetRegisterClass *DestRC, 70236024Sraj const TargetRegisterClass *SrcRC) const; 71236024Sraj 72236024Sraj virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 73236024Sraj MachineBasicBlock::iterator MI, 74236024Sraj unsigned SrcReg, bool isKill, int FrameIndex, 75236024Sraj const TargetRegisterClass *RC) const; 76236024Sraj 77236024Sraj virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 78236024Sraj MachineBasicBlock::iterator MI, 79236024Sraj unsigned DestReg, int FrameIndex, 80236024Sraj const TargetRegisterClass *RC) const; 81236024Sraj 82236024Sraj virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 83236024Sraj MachineBasicBlock::iterator MI, 84236024Sraj const std::vector<CalleeSavedInfo> &CSI) const; 85236024Sraj 86236024Sraj virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 87236024Sraj MachineBasicBlock::iterator MI, 88236024Sraj const std::vector<CalleeSavedInfo> &CSI) const; 89236024Sraj 90236024Sraj virtual bool ReverseBranchCondition( 91236024Sraj SmallVectorImpl<MachineOperand> &Cond) const; 92236024Sraj}; 93236024Sraj 94236024Sraj} 95236024Sraj 96236024Sraj#endif 97236024Sraj