1193323Sed//===-- XCoreISelDAGToDAG.cpp - A dag to dag inst selector for XCore ------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines an instruction selector for the XCore target. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#include "XCore.h" 15193323Sed#include "XCoreTargetMachine.h" 16193323Sed#include "llvm/CodeGen/MachineFrameInfo.h" 17193323Sed#include "llvm/CodeGen/MachineFunction.h" 18193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 19193323Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 20193323Sed#include "llvm/CodeGen/SelectionDAG.h" 21193323Sed#include "llvm/CodeGen/SelectionDAGISel.h" 22249423Sdim#include "llvm/IR/CallingConv.h" 23249423Sdim#include "llvm/IR/Constants.h" 24249423Sdim#include "llvm/IR/DerivedTypes.h" 25249423Sdim#include "llvm/IR/Function.h" 26249423Sdim#include "llvm/IR/Intrinsics.h" 27249423Sdim#include "llvm/IR/LLVMContext.h" 28193323Sed#include "llvm/Support/Compiler.h" 29193323Sed#include "llvm/Support/Debug.h" 30198090Srdivacky#include "llvm/Support/ErrorHandling.h" 31198090Srdivacky#include "llvm/Support/raw_ostream.h" 32249423Sdim#include "llvm/Target/TargetLowering.h" 33193323Sedusing namespace llvm; 34193323Sed 35193323Sed/// XCoreDAGToDAGISel - XCore specific code to select XCore machine 36193323Sed/// instructions for SelectionDAG operations. 37193323Sed/// 38193323Sednamespace { 39193323Sed class XCoreDAGToDAGISel : public SelectionDAGISel { 40193323Sed const XCoreSubtarget &Subtarget; 41193323Sed 42193323Sed public: 43234353Sdim XCoreDAGToDAGISel(XCoreTargetMachine &TM, CodeGenOpt::Level OptLevel) 44234353Sdim : SelectionDAGISel(TM, OptLevel), 45193323Sed Subtarget(*TM.getSubtargetImpl()) { } 46193323Sed 47202375Srdivacky SDNode *Select(SDNode *N); 48221345Sdim SDNode *SelectBRIND(SDNode *N); 49221345Sdim 50193323Sed /// getI32Imm - Return a target constant with the specified value, of type 51193323Sed /// i32. 52193323Sed inline SDValue getI32Imm(unsigned Imm) { 53193323Sed return CurDAG->getTargetConstant(Imm, MVT::i32); 54193323Sed } 55193323Sed 56212904Sdim inline bool immMskBitp(SDNode *inN) const { 57212904Sdim ConstantSDNode *N = cast<ConstantSDNode>(inN); 58212904Sdim uint32_t value = (uint32_t)N->getZExtValue(); 59212904Sdim if (!isMask_32(value)) { 60212904Sdim return false; 61212904Sdim } 62263508Sdim int msksize = 32 - countLeadingZeros(value); 63212904Sdim return (msksize >= 1 && msksize <= 8) || 64212904Sdim msksize == 16 || msksize == 24 || msksize == 32; 65212904Sdim } 66212904Sdim 67193323Sed // Complex Pattern Selectors. 68218893Sdim bool SelectADDRspii(SDValue Addr, SDValue &Base, SDValue &Offset); 69193323Sed 70193323Sed virtual const char *getPassName() const { 71193323Sed return "XCore DAG->DAG Pattern Instruction Selection"; 72193323Sed } 73193323Sed 74193323Sed // Include the pieces autogenerated from the target description. 75193323Sed #include "XCoreGenDAGISel.inc" 76193323Sed }; 77193323Sed} // end anonymous namespace 78193323Sed 79193323Sed/// createXCoreISelDag - This pass converts a legalized DAG into a 80193323Sed/// XCore-specific DAG, ready for instruction scheduling. 81193323Sed/// 82234353SdimFunctionPass *llvm::createXCoreISelDag(XCoreTargetMachine &TM, 83234353Sdim CodeGenOpt::Level OptLevel) { 84234353Sdim return new XCoreDAGToDAGISel(TM, OptLevel); 85193323Sed} 86193323Sed 87218893Sdimbool XCoreDAGToDAGISel::SelectADDRspii(SDValue Addr, SDValue &Base, 88218893Sdim SDValue &Offset) { 89193323Sed FrameIndexSDNode *FIN = 0; 90193323Sed if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) { 91193323Sed Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 92193323Sed Offset = CurDAG->getTargetConstant(0, MVT::i32); 93193323Sed return true; 94193323Sed } 95193323Sed if (Addr.getOpcode() == ISD::ADD) { 96193323Sed ConstantSDNode *CN = 0; 97193323Sed if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) 98193323Sed && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) 99193323Sed && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { 100193323Sed // Constant positive word offset from frame index 101193323Sed Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 102193323Sed Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); 103193323Sed return true; 104193323Sed } 105193323Sed } 106193323Sed return false; 107193323Sed} 108193323Sed 109202375SrdivackySDNode *XCoreDAGToDAGISel::Select(SDNode *N) { 110263508Sdim SDLoc dl(N); 111221345Sdim switch (N->getOpcode()) { 112221345Sdim default: break; 113221345Sdim case ISD::Constant: { 114221345Sdim uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue(); 115221345Sdim if (immMskBitp(N)) { 116221345Sdim // Transformation function: get the size of a mask 117221345Sdim // Look for the first non-zero bit 118263508Sdim SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val)); 119221345Sdim return CurDAG->getMachineNode(XCore::MKMSK_rus, dl, 120221345Sdim MVT::i32, MskSize); 121193323Sed } 122221345Sdim else if (!isUInt<16>(Val)) { 123221345Sdim SDValue CPIdx = 124221345Sdim CurDAG->getTargetConstantPool(ConstantInt::get( 125221345Sdim Type::getInt32Ty(*CurDAG->getContext()), Val), 126263508Sdim getTargetLowering()->getPointerTy()); 127226633Sdim SDNode *node = CurDAG->getMachineNode(XCore::LDWCP_lru6, dl, MVT::i32, 128226633Sdim MVT::Other, CPIdx, 129226633Sdim CurDAG->getEntryNode()); 130226633Sdim MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 131226633Sdim MemOp[0] = MF->getMachineMemOperand( 132226633Sdim MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad, 4, 4); 133226633Sdim cast<MachineSDNode>(node)->setMemRefs(MemOp, MemOp + 1); 134226633Sdim return node; 135221345Sdim } 136221345Sdim break; 137193323Sed } 138221345Sdim case XCoreISD::LADD: { 139221345Sdim SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 140221345Sdim N->getOperand(2) }; 141221345Sdim return CurDAG->getMachineNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32, 142251662Sdim Ops); 143221345Sdim } 144221345Sdim case XCoreISD::LSUB: { 145221345Sdim SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 146221345Sdim N->getOperand(2) }; 147221345Sdim return CurDAG->getMachineNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32, 148251662Sdim Ops); 149221345Sdim } 150221345Sdim case XCoreISD::MACCU: { 151221345Sdim SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 152221345Sdim N->getOperand(2), N->getOperand(3) }; 153221345Sdim return CurDAG->getMachineNode(XCore::MACCU_l4r, dl, MVT::i32, MVT::i32, 154251662Sdim Ops); 155221345Sdim } 156221345Sdim case XCoreISD::MACCS: { 157221345Sdim SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 158221345Sdim N->getOperand(2), N->getOperand(3) }; 159221345Sdim return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32, 160251662Sdim Ops); 161221345Sdim } 162221345Sdim case XCoreISD::LMUL: { 163221345Sdim SDValue Ops[] = { N->getOperand(0), N->getOperand(1), 164221345Sdim N->getOperand(2), N->getOperand(3) }; 165221345Sdim return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32, 166251662Sdim Ops); 167221345Sdim } 168249423Sdim case XCoreISD::CRC8: { 169249423Sdim SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2) }; 170249423Sdim return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32, 171251662Sdim Ops); 172223017Sdim } 173221345Sdim case ISD::BRIND: 174221345Sdim if (SDNode *ResNode = SelectBRIND(N)) 175221345Sdim return ResNode; 176221345Sdim break; 177221345Sdim // Other cases are autogenerated. 178221345Sdim } 179202375Srdivacky return SelectCode(N); 180193323Sed} 181221345Sdim 182221345Sdim/// Given a chain return a new chain where any appearance of Old is replaced 183221345Sdim/// by New. There must be at most one instruction between Old and Chain and 184221345Sdim/// this instruction must be a TokenFactor. Returns an empty SDValue if 185221345Sdim/// these conditions don't hold. 186221345Sdimstatic SDValue 187221345SdimreplaceInChain(SelectionDAG *CurDAG, SDValue Chain, SDValue Old, SDValue New) 188221345Sdim{ 189221345Sdim if (Chain == Old) 190221345Sdim return New; 191221345Sdim if (Chain->getOpcode() != ISD::TokenFactor) 192221345Sdim return SDValue(); 193221345Sdim SmallVector<SDValue, 8> Ops; 194221345Sdim bool found = false; 195221345Sdim for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) { 196221345Sdim if (Chain->getOperand(i) == Old) { 197221345Sdim Ops.push_back(New); 198221345Sdim found = true; 199221345Sdim } else { 200221345Sdim Ops.push_back(Chain->getOperand(i)); 201221345Sdim } 202221345Sdim } 203221345Sdim if (!found) 204221345Sdim return SDValue(); 205263508Sdim return CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, 206221345Sdim &Ops[0], Ops.size()); 207221345Sdim} 208221345Sdim 209221345SdimSDNode *XCoreDAGToDAGISel::SelectBRIND(SDNode *N) { 210263508Sdim SDLoc dl(N); 211221345Sdim // (brind (int_xcore_checkevent (addr))) 212221345Sdim SDValue Chain = N->getOperand(0); 213221345Sdim SDValue Addr = N->getOperand(1); 214221345Sdim if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN) 215221345Sdim return 0; 216221345Sdim unsigned IntNo = cast<ConstantSDNode>(Addr->getOperand(1))->getZExtValue(); 217221345Sdim if (IntNo != Intrinsic::xcore_checkevent) 218221345Sdim return 0; 219221345Sdim SDValue nextAddr = Addr->getOperand(2); 220221345Sdim SDValue CheckEventChainOut(Addr.getNode(), 1); 221221345Sdim if (!CheckEventChainOut.use_empty()) { 222221345Sdim // If the chain out of the checkevent intrinsic is an operand of the 223221345Sdim // indirect branch or used in a TokenFactor which is the operand of the 224221345Sdim // indirect branch then build a new chain which uses the chain coming into 225221345Sdim // the checkevent intrinsic instead. 226221345Sdim SDValue CheckEventChainIn = Addr->getOperand(0); 227221345Sdim SDValue NewChain = replaceInChain(CurDAG, Chain, CheckEventChainOut, 228221345Sdim CheckEventChainIn); 229221345Sdim if (!NewChain.getNode()) 230221345Sdim return 0; 231221345Sdim Chain = NewChain; 232221345Sdim } 233221345Sdim // Enable events on the thread using setsr 1 and then disable them immediately 234221345Sdim // after with clrsr 1. If any resources owned by the thread are ready an event 235221345Sdim // will be taken. If no resource is ready we branch to the address which was 236221345Sdim // the operand to the checkevent intrinsic. 237221345Sdim SDValue constOne = getI32Imm(1); 238221345Sdim SDValue Glue = 239221345Sdim SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue, 240221345Sdim constOne, Chain), 0); 241221345Sdim Glue = 242221345Sdim SDValue(CurDAG->getMachineNode(XCore::CLRSR_branch_u6, dl, MVT::Glue, 243221345Sdim constOne, Glue), 0); 244221345Sdim if (nextAddr->getOpcode() == XCoreISD::PCRelativeWrapper && 245221345Sdim nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) { 246221345Sdim return CurDAG->SelectNodeTo(N, XCore::BRFU_lu6, MVT::Other, 247221345Sdim nextAddr->getOperand(0), Glue); 248221345Sdim } 249221345Sdim return CurDAG->SelectNodeTo(N, XCore::BAU_1r, MVT::Other, nextAddr, Glue); 250221345Sdim} 251