X86Subtarget.cpp revision 234353 
1//===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the X86 specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "subtarget"
15#include "X86Subtarget.h"
16#include "X86InstrInfo.h"
17#include "llvm/GlobalValue.h"
18#include "llvm/Support/Debug.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Support/raw_ostream.h"
21#include "llvm/Support/Host.h"
22#include "llvm/Target/TargetMachine.h"
23#include "llvm/Target/TargetOptions.h"
24
25#define GET_SUBTARGETINFO_TARGET_DESC
26#define GET_SUBTARGETINFO_CTOR
27#include "X86GenSubtargetInfo.inc"
28
29using namespace llvm;
30
31#if defined(_MSC_VER)
32#include <intrin.h>
33#endif
34
35/// ClassifyBlockAddressReference - Classify a blockaddress reference for the
36/// current subtarget according to how we should reference it in a non-pcrel
37/// context.
38unsigned char X86Subtarget::
39ClassifyBlockAddressReference() const {
40  if (isPICStyleGOT())    // 32-bit ELF targets.
41    return X86II::MO_GOTOFF;
42
43  if (isPICStyleStubPIC())   // Darwin/32 in PIC mode.
44    return X86II::MO_PIC_BASE_OFFSET;
45
46  // Direct static reference to label.
47  return X86II::MO_NO_FLAG;
48}
49
50/// ClassifyGlobalReference - Classify a global variable reference for the
51/// current subtarget according to how we should reference it in a non-pcrel
52/// context.
53unsigned char X86Subtarget::
54ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
55  // DLLImport only exists on windows, it is implemented as a load from a
56  // DLLIMPORT stub.
57  if (GV->hasDLLImportLinkage())
58    return X86II::MO_DLLIMPORT;
59
60  // Determine whether this is a reference to a definition or a declaration.
61  // Materializable GVs (in JIT lazy compilation mode) do not require an extra
62  // load from stub.
63  bool isDecl = GV->hasAvailableExternallyLinkage();
64  if (GV->isDeclaration() && !GV->isMaterializable())
65    isDecl = true;
66
67  // X86-64 in PIC mode.
68  if (isPICStyleRIPRel()) {
69    // Large model never uses stubs.
70    if (TM.getCodeModel() == CodeModel::Large)
71      return X86II::MO_NO_FLAG;
72
73    if (isTargetDarwin()) {
74      // If symbol visibility is hidden, the extra load is not needed if
75      // target is x86-64 or the symbol is definitely defined in the current
76      // translation unit.
77      if (GV->hasDefaultVisibility() &&
78          (isDecl || GV->isWeakForLinker()))
79        return X86II::MO_GOTPCREL;
80    } else if (!isTargetWin64()) {
81      assert(isTargetELF() && "Unknown rip-relative target");
82
83      // Extra load is needed for all externally visible.
84      if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
85        return X86II::MO_GOTPCREL;
86    }
87
88    return X86II::MO_NO_FLAG;
89  }
90
91  if (isPICStyleGOT()) {   // 32-bit ELF targets.
92    // Extra load is needed for all externally visible.
93    if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
94      return X86II::MO_GOTOFF;
95    return X86II::MO_GOT;
96  }
97
98  if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
99    // Determine whether we have a stub reference and/or whether the reference
100    // is relative to the PIC base or not.
101
102    // If this is a strong reference to a definition, it is definitely not
103    // through a stub.
104    if (!isDecl && !GV->isWeakForLinker())
105      return X86II::MO_PIC_BASE_OFFSET;
106
107    // Unless we have a symbol with hidden visibility, we have to go through a
108    // normal $non_lazy_ptr stub because this symbol might be resolved late.
109    if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
110      return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
111
112    // If symbol visibility is hidden, we have a stub for common symbol
113    // references and external declarations.
114    if (isDecl || GV->hasCommonLinkage()) {
115      // Hidden $non_lazy_ptr reference.
116      return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
117    }
118
119    // Otherwise, no stub.
120    return X86II::MO_PIC_BASE_OFFSET;
121  }
122
123  if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
124    // Determine whether we have a stub reference.
125
126    // If this is a strong reference to a definition, it is definitely not
127    // through a stub.
128    if (!isDecl && !GV->isWeakForLinker())
129      return X86II::MO_NO_FLAG;
130
131    // Unless we have a symbol with hidden visibility, we have to go through a
132    // normal $non_lazy_ptr stub because this symbol might be resolved late.
133    if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
134      return X86II::MO_DARWIN_NONLAZY;
135
136    // Otherwise, no stub.
137    return X86II::MO_NO_FLAG;
138  }
139
140  // Direct static reference to global.
141  return X86II::MO_NO_FLAG;
142}
143
144
145/// getBZeroEntry - This function returns the name of a function which has an
146/// interface like the non-standard bzero function, if such a function exists on
147/// the current subtarget and it is considered prefereable over memset with zero
148/// passed as the second argument. Otherwise it returns null.
149const char *X86Subtarget::getBZeroEntry() const {
150  // Darwin 10 has a __bzero entry point for this purpose.
151  if (getTargetTriple().isMacOSX() &&
152      !getTargetTriple().isMacOSXVersionLT(10, 6))
153    return "__bzero";
154
155  return 0;
156}
157
158/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
159/// to immediate address.
160bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
161  if (In64BitMode)
162    return false;
163  return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
164}
165
166/// getSpecialAddressLatency - For targets where it is beneficial to
167/// backschedule instructions that compute addresses, return a value
168/// indicating the number of scheduling cycles of backscheduling that
169/// should be attempted.
170unsigned X86Subtarget::getSpecialAddressLatency() const {
171  // For x86 out-of-order targets, back-schedule address computations so
172  // that loads and stores aren't blocked.
173  // This value was chosen arbitrarily.
174  return 200;
175}
176
177void X86Subtarget::AutoDetectSubtargetFeatures() {
178  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
179  unsigned MaxLevel;
180  union {
181    unsigned u[3];
182    char     c[12];
183  } text;
184
185  if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
186      MaxLevel < 1)
187    return;
188
189  X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
190
191  if ((EDX >> 15) & 1) { HasCMov = true;      ToggleFeature(X86::FeatureCMOV); }
192  if ((EDX >> 23) & 1) { X86SSELevel = MMX;   ToggleFeature(X86::FeatureMMX);  }
193  if ((EDX >> 25) & 1) { X86SSELevel = SSE1;  ToggleFeature(X86::FeatureSSE1); }
194  if ((EDX >> 26) & 1) { X86SSELevel = SSE2;  ToggleFeature(X86::FeatureSSE2); }
195  if (ECX & 0x1)       { X86SSELevel = SSE3;  ToggleFeature(X86::FeatureSSE3); }
196  if ((ECX >> 9)  & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
197  if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
198  if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
199  // FIXME: AVX codegen support is not ready.
200  //if ((ECX >> 28) & 1) { X86SSELevel = AVX;  ToggleFeature(X86::FeatureAVX); }
201
202  bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
203  bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
204
205  if (IsIntel && ((ECX >> 1) & 0x1)) {
206    HasCLMUL = true;
207    ToggleFeature(X86::FeatureCLMUL);
208  }
209  if (IsIntel && ((ECX >> 12) & 0x1)) {
210    HasFMA3 = true;
211    ToggleFeature(X86::FeatureFMA3);
212  }
213  if (IsIntel && ((ECX >> 22) & 0x1)) {
214    HasMOVBE = true;
215    ToggleFeature(X86::FeatureMOVBE);
216  }
217  if (IsIntel && ((ECX >> 23) & 0x1)) {
218    HasPOPCNT = true;
219    ToggleFeature(X86::FeaturePOPCNT);
220  }
221  if (IsIntel && ((ECX >> 25) & 0x1)) {
222    HasAES = true;
223    ToggleFeature(X86::FeatureAES);
224  }
225  if (IsIntel && ((ECX >> 29) & 0x1)) {
226    HasF16C = true;
227    ToggleFeature(X86::FeatureF16C);
228  }
229  if (IsIntel && ((ECX >> 30) & 0x1)) {
230    HasRDRAND = true;
231    ToggleFeature(X86::FeatureRDRAND);
232  }
233
234  if ((ECX >> 13) & 0x1) {
235    HasCmpxchg16b = true;
236    ToggleFeature(X86::FeatureCMPXCHG16B);
237  }
238
239  if (IsIntel || IsAMD) {
240    // Determine if bit test memory instructions are slow.
241    unsigned Family = 0;
242    unsigned Model  = 0;
243    X86_MC::DetectFamilyModel(EAX, Family, Model);
244    if (IsAMD || (Family == 6 && Model >= 13)) {
245      IsBTMemSlow = true;
246      ToggleFeature(X86::FeatureSlowBTMem);
247    }
248
249    // If it's Nehalem, unaligned memory access is fast.
250    // FIXME: Nehalem is family 6. Also include Westmere and later processors?
251    if (Family == 15 && Model == 26) {
252      IsUAMemFast = true;
253      ToggleFeature(X86::FeatureFastUAMem);
254    }
255
256    // Set processor type. Currently only Atom is detected.
257    if (Family == 6 && Model == 28) {
258      X86ProcFamily = IntelAtom;
259      ToggleFeature(X86::FeatureLeaForSP);
260    }
261
262    unsigned MaxExtLevel;
263    X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
264
265    if (MaxExtLevel >= 0x80000001) {
266      X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
267      if ((EDX >> 29) & 0x1) {
268        HasX86_64 = true;
269        ToggleFeature(X86::Feature64Bit);
270      }
271      if ((ECX >> 5) & 0x1) {
272        HasLZCNT = true;
273        ToggleFeature(X86::FeatureLZCNT);
274      }
275      if (IsAMD) {
276        if ((ECX >> 6) & 0x1) {
277          HasSSE4A = true;
278          ToggleFeature(X86::FeatureSSE4A);
279        }
280        if ((ECX >> 11) & 0x1) {
281          HasXOP = true;
282          ToggleFeature(X86::FeatureXOP);
283        }
284        if ((ECX >> 16) & 0x1) {
285          HasFMA4 = true;
286          ToggleFeature(X86::FeatureFMA4);
287        }
288      }
289    }
290  }
291
292  if (IsIntel && MaxLevel >= 7) {
293    if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
294      if (EBX & 0x1) {
295        HasFSGSBase = true;
296        ToggleFeature(X86::FeatureFSGSBase);
297      }
298      if ((EBX >> 3) & 0x1) {
299        HasBMI = true;
300        ToggleFeature(X86::FeatureBMI);
301      }
302      // FIXME: AVX2 codegen support is not ready.
303      //if ((EBX >> 5) & 0x1) {
304      //  X86SSELevel = AVX2;
305      //  ToggleFeature(X86::FeatureAVX2);
306      //}
307      if ((EBX >> 8) & 0x1) {
308        HasBMI2 = true;
309        ToggleFeature(X86::FeatureBMI2);
310      }
311    }
312  }
313}
314
315X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
316                           const std::string &FS,
317                           unsigned StackAlignOverride, bool is64Bit)
318  : X86GenSubtargetInfo(TT, CPU, FS)
319  , X86ProcFamily(Others)
320  , PICStyle(PICStyles::None)
321  , X86SSELevel(NoMMXSSE)
322  , X863DNowLevel(NoThreeDNow)
323  , HasCMov(false)
324  , HasX86_64(false)
325  , HasPOPCNT(false)
326  , HasSSE4A(false)
327  , HasAES(false)
328  , HasCLMUL(false)
329  , HasFMA3(false)
330  , HasFMA4(false)
331  , HasXOP(false)
332  , HasMOVBE(false)
333  , HasRDRAND(false)
334  , HasF16C(false)
335  , HasFSGSBase(false)
336  , HasLZCNT(false)
337  , HasBMI(false)
338  , HasBMI2(false)
339  , IsBTMemSlow(false)
340  , IsUAMemFast(false)
341  , HasVectorUAMem(false)
342  , HasCmpxchg16b(false)
343  , UseLeaForSP(false)
344  , PostRAScheduler(false)
345  , stackAlignment(4)
346  // FIXME: this is a known good value for Yonah. How about others?
347  , MaxInlineSizeThreshold(128)
348  , TargetTriple(TT)
349  , In64BitMode(is64Bit) {
350  // Determine default and user specified characteristics
351  std::string CPUName = CPU;
352  if (!FS.empty() || !CPU.empty()) {
353    if (CPUName.empty()) {
354#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
355    || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
356      CPUName = sys::getHostCPUName();
357#else
358      CPUName = "generic";
359#endif
360    }
361
362    // Make sure 64-bit features are available in 64-bit mode. (But make sure
363    // SSE2 can be turned off explicitly.)
364    std::string FullFS = FS;
365    if (In64BitMode) {
366      if (!FullFS.empty())
367        FullFS = "+64bit,+sse2," + FullFS;
368      else
369        FullFS = "+64bit,+sse2";
370    }
371
372    // If feature string is not empty, parse features string.
373    ParseSubtargetFeatures(CPUName, FullFS);
374  } else {
375    if (CPUName.empty()) {
376#if defined (__x86_64__) || defined(__i386__)
377      CPUName = sys::getHostCPUName();
378#else
379      CPUName = "generic";
380#endif
381    }
382    // Otherwise, use CPUID to auto-detect feature set.
383    AutoDetectSubtargetFeatures();
384
385    // Make sure 64-bit features are available in 64-bit mode.
386    if (In64BitMode) {
387      HasX86_64 = true; ToggleFeature(X86::Feature64Bit);
388      HasCMov = true;   ToggleFeature(X86::FeatureCMOV);
389
390      if (X86SSELevel < SSE2) {
391        X86SSELevel = SSE2;
392        ToggleFeature(X86::FeatureSSE1);
393        ToggleFeature(X86::FeatureSSE2);
394      }
395    }
396  }
397
398  if (X86ProcFamily == IntelAtom) {
399    PostRAScheduler = true;
400    InstrItins = getInstrItineraryForCPU(CPUName);
401  }
402
403  // It's important to keep the MCSubtargetInfo feature bits in sync with
404  // target data structure which is shared with MC code emitter, etc.
405  if (In64BitMode)
406    ToggleFeature(X86::Mode64Bit);
407
408  DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
409               << ", 3DNowLevel " << X863DNowLevel
410               << ", 64bit " << HasX86_64 << "\n");
411  assert((!In64BitMode || HasX86_64) &&
412         "64-bit code requested on a subtarget that doesn't support it!");
413
414  // Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both
415  // 32 and 64 bit) and for all 64-bit targets.
416  if (StackAlignOverride)
417    stackAlignment = StackAlignOverride;
418  else if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() ||
419           isTargetSolaris() || In64BitMode)
420    stackAlignment = 16;
421}
422
423bool X86Subtarget::enablePostRAScheduler(
424           CodeGenOpt::Level OptLevel,
425           TargetSubtargetInfo::AntiDepBreakMode& Mode,
426           RegClassVector& CriticalPathRCs) const {
427  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
428  CriticalPathRCs.clear();
429  return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
430}
431