X86Subtarget.cpp revision 226633 
1//===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the X86 specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "subtarget"
15#include "X86Subtarget.h"
16#include "X86InstrInfo.h"
17#include "llvm/GlobalValue.h"
18#include "llvm/Support/Debug.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Support/raw_ostream.h"
21#include "llvm/Support/Host.h"
22#include "llvm/Target/TargetMachine.h"
23#include "llvm/Target/TargetOptions.h"
24#include "llvm/ADT/SmallVector.h"
25
26#define GET_SUBTARGETINFO_TARGET_DESC
27#define GET_SUBTARGETINFO_CTOR
28#include "X86GenSubtargetInfo.inc"
29
30using namespace llvm;
31
32#if defined(_MSC_VER)
33#include <intrin.h>
34#endif
35
36/// ClassifyBlockAddressReference - Classify a blockaddress reference for the
37/// current subtarget according to how we should reference it in a non-pcrel
38/// context.
39unsigned char X86Subtarget::
40ClassifyBlockAddressReference() const {
41  if (isPICStyleGOT())    // 32-bit ELF targets.
42    return X86II::MO_GOTOFF;
43
44  if (isPICStyleStubPIC())   // Darwin/32 in PIC mode.
45    return X86II::MO_PIC_BASE_OFFSET;
46
47  // Direct static reference to label.
48  return X86II::MO_NO_FLAG;
49}
50
51/// ClassifyGlobalReference - Classify a global variable reference for the
52/// current subtarget according to how we should reference it in a non-pcrel
53/// context.
54unsigned char X86Subtarget::
55ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
56  // DLLImport only exists on windows, it is implemented as a load from a
57  // DLLIMPORT stub.
58  if (GV->hasDLLImportLinkage())
59    return X86II::MO_DLLIMPORT;
60
61  // Determine whether this is a reference to a definition or a declaration.
62  // Materializable GVs (in JIT lazy compilation mode) do not require an extra
63  // load from stub.
64  bool isDecl = GV->hasAvailableExternallyLinkage();
65  if (GV->isDeclaration() && !GV->isMaterializable())
66    isDecl = true;
67
68  // X86-64 in PIC mode.
69  if (isPICStyleRIPRel()) {
70    // Large model never uses stubs.
71    if (TM.getCodeModel() == CodeModel::Large)
72      return X86II::MO_NO_FLAG;
73
74    if (isTargetDarwin()) {
75      // If symbol visibility is hidden, the extra load is not needed if
76      // target is x86-64 or the symbol is definitely defined in the current
77      // translation unit.
78      if (GV->hasDefaultVisibility() &&
79          (isDecl || GV->isWeakForLinker()))
80        return X86II::MO_GOTPCREL;
81    } else if (!isTargetWin64()) {
82      assert(isTargetELF() && "Unknown rip-relative target");
83
84      // Extra load is needed for all externally visible.
85      if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
86        return X86II::MO_GOTPCREL;
87    }
88
89    return X86II::MO_NO_FLAG;
90  }
91
92  if (isPICStyleGOT()) {   // 32-bit ELF targets.
93    // Extra load is needed for all externally visible.
94    if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
95      return X86II::MO_GOTOFF;
96    return X86II::MO_GOT;
97  }
98
99  if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
100    // Determine whether we have a stub reference and/or whether the reference
101    // is relative to the PIC base or not.
102
103    // If this is a strong reference to a definition, it is definitely not
104    // through a stub.
105    if (!isDecl && !GV->isWeakForLinker())
106      return X86II::MO_PIC_BASE_OFFSET;
107
108    // Unless we have a symbol with hidden visibility, we have to go through a
109    // normal $non_lazy_ptr stub because this symbol might be resolved late.
110    if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
111      return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
112
113    // If symbol visibility is hidden, we have a stub for common symbol
114    // references and external declarations.
115    if (isDecl || GV->hasCommonLinkage()) {
116      // Hidden $non_lazy_ptr reference.
117      return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
118    }
119
120    // Otherwise, no stub.
121    return X86II::MO_PIC_BASE_OFFSET;
122  }
123
124  if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
125    // Determine whether we have a stub reference.
126
127    // If this is a strong reference to a definition, it is definitely not
128    // through a stub.
129    if (!isDecl && !GV->isWeakForLinker())
130      return X86II::MO_NO_FLAG;
131
132    // Unless we have a symbol with hidden visibility, we have to go through a
133    // normal $non_lazy_ptr stub because this symbol might be resolved late.
134    if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
135      return X86II::MO_DARWIN_NONLAZY;
136
137    // Otherwise, no stub.
138    return X86II::MO_NO_FLAG;
139  }
140
141  // Direct static reference to global.
142  return X86II::MO_NO_FLAG;
143}
144
145
146/// getBZeroEntry - This function returns the name of a function which has an
147/// interface like the non-standard bzero function, if such a function exists on
148/// the current subtarget and it is considered prefereable over memset with zero
149/// passed as the second argument. Otherwise it returns null.
150const char *X86Subtarget::getBZeroEntry() const {
151  // Darwin 10 has a __bzero entry point for this purpose.
152  if (getTargetTriple().isMacOSX() &&
153      !getTargetTriple().isMacOSXVersionLT(10, 6))
154    return "__bzero";
155
156  return 0;
157}
158
159/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
160/// to immediate address.
161bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
162  if (In64BitMode)
163    return false;
164  return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
165}
166
167/// getSpecialAddressLatency - For targets where it is beneficial to
168/// backschedule instructions that compute addresses, return a value
169/// indicating the number of scheduling cycles of backscheduling that
170/// should be attempted.
171unsigned X86Subtarget::getSpecialAddressLatency() const {
172  // For x86 out-of-order targets, back-schedule address computations so
173  // that loads and stores aren't blocked.
174  // This value was chosen arbitrarily.
175  return 200;
176}
177
178void X86Subtarget::AutoDetectSubtargetFeatures() {
179  unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
180  union {
181    unsigned u[3];
182    char     c[12];
183  } text;
184
185  if (X86_MC::GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
186    return;
187
188  X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
189
190  if ((EDX >> 15) & 1) { HasCMov = true;      ToggleFeature(X86::FeatureCMOV); }
191  if ((EDX >> 23) & 1) { X86SSELevel = MMX;   ToggleFeature(X86::FeatureMMX);  }
192  if ((EDX >> 25) & 1) { X86SSELevel = SSE1;  ToggleFeature(X86::FeatureSSE1); }
193  if ((EDX >> 26) & 1) { X86SSELevel = SSE2;  ToggleFeature(X86::FeatureSSE2); }
194  if (ECX & 0x1)       { X86SSELevel = SSE3;  ToggleFeature(X86::FeatureSSE3); }
195  if ((ECX >> 9)  & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
196  if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
197  if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
198  // FIXME: AVX codegen support is not ready.
199  //if ((ECX >> 28) & 1) { HasAVX = true;  ToggleFeature(X86::FeatureAVX); }
200
201  bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
202  bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
203
204  if (IsIntel && ((ECX >> 1) & 0x1)) {
205    HasCLMUL = true;
206    ToggleFeature(X86::FeatureCLMUL);
207  }
208  if (IsIntel && ((ECX >> 12) & 0x1)) {
209    HasFMA3 = true;
210    ToggleFeature(X86::FeatureFMA3);
211  }
212  if (IsIntel && ((ECX >> 22) & 0x1)) {
213    HasMOVBE = true;
214    ToggleFeature(X86::FeatureMOVBE);
215  }
216  if (IsIntel && ((ECX >> 23) & 0x1)) {
217    HasPOPCNT = true;
218    ToggleFeature(X86::FeaturePOPCNT);
219  }
220  if (IsIntel && ((ECX >> 25) & 0x1)) {
221    HasAES = true;
222    ToggleFeature(X86::FeatureAES);
223  }
224  if (IsIntel && ((ECX >> 29) & 0x1)) {
225    HasF16C = true;
226    ToggleFeature(X86::FeatureF16C);
227  }
228  if (IsIntel && ((ECX >> 30) & 0x1)) {
229    HasRDRAND = true;
230    ToggleFeature(X86::FeatureRDRAND);
231  }
232
233  if ((ECX >> 13) & 0x1) {
234    HasCmpxchg16b = true;
235    ToggleFeature(X86::FeatureCMPXCHG16B);
236  }
237
238  if (IsIntel || IsAMD) {
239    // Determine if bit test memory instructions are slow.
240    unsigned Family = 0;
241    unsigned Model  = 0;
242    X86_MC::DetectFamilyModel(EAX, Family, Model);
243    if (IsAMD || (Family == 6 && Model >= 13)) {
244      IsBTMemSlow = true;
245      ToggleFeature(X86::FeatureSlowBTMem);
246    }
247    // If it's Nehalem, unaligned memory access is fast.
248    if (Family == 15 && Model == 26) {
249      IsUAMemFast = true;
250      ToggleFeature(X86::FeatureFastUAMem);
251    }
252
253    X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
254    if ((EDX >> 29) & 0x1) {
255      HasX86_64 = true;
256      ToggleFeature(X86::Feature64Bit);
257    }
258    if ((ECX >> 5) & 0x1) {
259      HasLZCNT = true;
260      ToggleFeature(X86::FeatureLZCNT);
261    }
262    if (IsAMD && ((ECX >> 6) & 0x1)) {
263      HasSSE4A = true;
264      ToggleFeature(X86::FeatureSSE4A);
265    }
266    if (IsAMD && ((ECX >> 16) & 0x1)) {
267      HasFMA4 = true;
268      ToggleFeature(X86::FeatureFMA4);
269    }
270  }
271}
272
273X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
274                           const std::string &FS,
275                           unsigned StackAlignOverride, bool is64Bit)
276  : X86GenSubtargetInfo(TT, CPU, FS)
277  , PICStyle(PICStyles::None)
278  , X86SSELevel(NoMMXSSE)
279  , X863DNowLevel(NoThreeDNow)
280  , HasCMov(false)
281  , HasX86_64(false)
282  , HasPOPCNT(false)
283  , HasSSE4A(false)
284  , HasAVX(false)
285  , HasAES(false)
286  , HasCLMUL(false)
287  , HasFMA3(false)
288  , HasFMA4(false)
289  , HasMOVBE(false)
290  , HasRDRAND(false)
291  , HasF16C(false)
292  , HasLZCNT(false)
293  , HasBMI(false)
294  , IsBTMemSlow(false)
295  , IsUAMemFast(false)
296  , HasVectorUAMem(false)
297  , HasCmpxchg16b(false)
298  , stackAlignment(8)
299  // FIXME: this is a known good value for Yonah. How about others?
300  , MaxInlineSizeThreshold(128)
301  , TargetTriple(TT)
302  , In64BitMode(is64Bit)
303  , InNaClMode(false) {
304  // Determine default and user specified characteristics
305  if (!FS.empty() || !CPU.empty()) {
306    std::string CPUName = CPU;
307    if (CPUName.empty()) {
308#if defined (__x86_64__) || defined(__i386__)
309      CPUName = sys::getHostCPUName();
310#else
311      CPUName = "generic";
312#endif
313    }
314
315    // Make sure 64-bit features are available in 64-bit mode. (But make sure
316    // SSE2 can be turned off explicitly.)
317    std::string FullFS = FS;
318    if (In64BitMode) {
319      if (!FullFS.empty())
320        FullFS = "+64bit,+sse2," + FullFS;
321      else
322        FullFS = "+64bit,+sse2";
323    }
324
325    // If feature string is not empty, parse features string.
326    ParseSubtargetFeatures(CPUName, FullFS);
327  } else {
328    // Otherwise, use CPUID to auto-detect feature set.
329    AutoDetectSubtargetFeatures();
330
331    // Make sure 64-bit features are available in 64-bit mode.
332    if (In64BitMode) {
333      HasX86_64 = true; ToggleFeature(X86::Feature64Bit);
334      HasCMov = true;   ToggleFeature(X86::FeatureCMOV);
335
336      if (!HasAVX && X86SSELevel < SSE2) {
337        X86SSELevel = SSE2;
338        ToggleFeature(X86::FeatureSSE1);
339        ToggleFeature(X86::FeatureSSE2);
340      }
341    }
342  }
343
344  // It's important to keep the MCSubtargetInfo feature bits in sync with
345  // target data structure which is shared with MC code emitter, etc.
346  if (In64BitMode)
347    ToggleFeature(X86::Mode64Bit);
348
349  if (isTargetNaCl()) {
350    InNaClMode = true;
351    ToggleFeature(X86::ModeNaCl);
352  }
353
354  if (HasAVX)
355    X86SSELevel = NoMMXSSE;
356
357  DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
358               << ", 3DNowLevel " << X863DNowLevel
359               << ", 64bit " << HasX86_64 << "\n");
360  assert((!In64BitMode || HasX86_64) &&
361         "64-bit code requested on a subtarget that doesn't support it!");
362
363  if(EnableSegmentedStacks && !isTargetELF())
364    report_fatal_error("Segmented stacks are only implemented on ELF.");
365
366  // Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both
367  // 32 and 64 bit) and for all 64-bit targets.
368  if (StackAlignOverride)
369    stackAlignment = StackAlignOverride;
370  else if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() ||
371           isTargetSolaris() || In64BitMode)
372    stackAlignment = 16;
373}
374