X86InstrInfo.cpp revision 205218
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86InstrInfo.h" 15#include "X86.h" 16#include "X86GenInstrInfo.inc" 17#include "X86InstrBuilder.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86Subtarget.h" 20#include "X86TargetMachine.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/ADT/STLExtras.h" 24#include "llvm/CodeGen/MachineConstantPool.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/LiveVariables.h" 29#include "llvm/CodeGen/PseudoSourceValue.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/MC/MCAsmInfo.h" 36 37#include <limits> 38 39using namespace llvm; 40 41static cl::opt<bool> 42NoFusing("disable-spill-fusing", 43 cl::desc("Disable fusing of spill code into instructions")); 44static cl::opt<bool> 45PrintFailedFusing("print-failed-fuse-candidates", 46 cl::desc("Print instructions that the allocator wants to" 47 " fuse, but the X86 backend currently can't"), 48 cl::Hidden); 49static cl::opt<bool> 50ReMatPICStubLoad("remat-pic-stub-load", 51 cl::desc("Re-materialize load from stub in PIC mode"), 52 cl::init(false), cl::Hidden); 53 54X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 55 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)), 56 TM(tm), RI(tm, *this) { 57 SmallVector<unsigned,16> AmbEntries; 58 static const unsigned OpTbl2Addr[][2] = { 59 { X86::ADC32ri, X86::ADC32mi }, 60 { X86::ADC32ri8, X86::ADC32mi8 }, 61 { X86::ADC32rr, X86::ADC32mr }, 62 { X86::ADC64ri32, X86::ADC64mi32 }, 63 { X86::ADC64ri8, X86::ADC64mi8 }, 64 { X86::ADC64rr, X86::ADC64mr }, 65 { X86::ADD16ri, X86::ADD16mi }, 66 { X86::ADD16ri8, X86::ADD16mi8 }, 67 { X86::ADD16rr, X86::ADD16mr }, 68 { X86::ADD32ri, X86::ADD32mi }, 69 { X86::ADD32ri8, X86::ADD32mi8 }, 70 { X86::ADD32rr, X86::ADD32mr }, 71 { X86::ADD64ri32, X86::ADD64mi32 }, 72 { X86::ADD64ri8, X86::ADD64mi8 }, 73 { X86::ADD64rr, X86::ADD64mr }, 74 { X86::ADD8ri, X86::ADD8mi }, 75 { X86::ADD8rr, X86::ADD8mr }, 76 { X86::AND16ri, X86::AND16mi }, 77 { X86::AND16ri8, X86::AND16mi8 }, 78 { X86::AND16rr, X86::AND16mr }, 79 { X86::AND32ri, X86::AND32mi }, 80 { X86::AND32ri8, X86::AND32mi8 }, 81 { X86::AND32rr, X86::AND32mr }, 82 { X86::AND64ri32, X86::AND64mi32 }, 83 { X86::AND64ri8, X86::AND64mi8 }, 84 { X86::AND64rr, X86::AND64mr }, 85 { X86::AND8ri, X86::AND8mi }, 86 { X86::AND8rr, X86::AND8mr }, 87 { X86::DEC16r, X86::DEC16m }, 88 { X86::DEC32r, X86::DEC32m }, 89 { X86::DEC64_16r, X86::DEC64_16m }, 90 { X86::DEC64_32r, X86::DEC64_32m }, 91 { X86::DEC64r, X86::DEC64m }, 92 { X86::DEC8r, X86::DEC8m }, 93 { X86::INC16r, X86::INC16m }, 94 { X86::INC32r, X86::INC32m }, 95 { X86::INC64_16r, X86::INC64_16m }, 96 { X86::INC64_32r, X86::INC64_32m }, 97 { X86::INC64r, X86::INC64m }, 98 { X86::INC8r, X86::INC8m }, 99 { X86::NEG16r, X86::NEG16m }, 100 { X86::NEG32r, X86::NEG32m }, 101 { X86::NEG64r, X86::NEG64m }, 102 { X86::NEG8r, X86::NEG8m }, 103 { X86::NOT16r, X86::NOT16m }, 104 { X86::NOT32r, X86::NOT32m }, 105 { X86::NOT64r, X86::NOT64m }, 106 { X86::NOT8r, X86::NOT8m }, 107 { X86::OR16ri, X86::OR16mi }, 108 { X86::OR16ri8, X86::OR16mi8 }, 109 { X86::OR16rr, X86::OR16mr }, 110 { X86::OR32ri, X86::OR32mi }, 111 { X86::OR32ri8, X86::OR32mi8 }, 112 { X86::OR32rr, X86::OR32mr }, 113 { X86::OR64ri32, X86::OR64mi32 }, 114 { X86::OR64ri8, X86::OR64mi8 }, 115 { X86::OR64rr, X86::OR64mr }, 116 { X86::OR8ri, X86::OR8mi }, 117 { X86::OR8rr, X86::OR8mr }, 118 { X86::ROL16r1, X86::ROL16m1 }, 119 { X86::ROL16rCL, X86::ROL16mCL }, 120 { X86::ROL16ri, X86::ROL16mi }, 121 { X86::ROL32r1, X86::ROL32m1 }, 122 { X86::ROL32rCL, X86::ROL32mCL }, 123 { X86::ROL32ri, X86::ROL32mi }, 124 { X86::ROL64r1, X86::ROL64m1 }, 125 { X86::ROL64rCL, X86::ROL64mCL }, 126 { X86::ROL64ri, X86::ROL64mi }, 127 { X86::ROL8r1, X86::ROL8m1 }, 128 { X86::ROL8rCL, X86::ROL8mCL }, 129 { X86::ROL8ri, X86::ROL8mi }, 130 { X86::ROR16r1, X86::ROR16m1 }, 131 { X86::ROR16rCL, X86::ROR16mCL }, 132 { X86::ROR16ri, X86::ROR16mi }, 133 { X86::ROR32r1, X86::ROR32m1 }, 134 { X86::ROR32rCL, X86::ROR32mCL }, 135 { X86::ROR32ri, X86::ROR32mi }, 136 { X86::ROR64r1, X86::ROR64m1 }, 137 { X86::ROR64rCL, X86::ROR64mCL }, 138 { X86::ROR64ri, X86::ROR64mi }, 139 { X86::ROR8r1, X86::ROR8m1 }, 140 { X86::ROR8rCL, X86::ROR8mCL }, 141 { X86::ROR8ri, X86::ROR8mi }, 142 { X86::SAR16r1, X86::SAR16m1 }, 143 { X86::SAR16rCL, X86::SAR16mCL }, 144 { X86::SAR16ri, X86::SAR16mi }, 145 { X86::SAR32r1, X86::SAR32m1 }, 146 { X86::SAR32rCL, X86::SAR32mCL }, 147 { X86::SAR32ri, X86::SAR32mi }, 148 { X86::SAR64r1, X86::SAR64m1 }, 149 { X86::SAR64rCL, X86::SAR64mCL }, 150 { X86::SAR64ri, X86::SAR64mi }, 151 { X86::SAR8r1, X86::SAR8m1 }, 152 { X86::SAR8rCL, X86::SAR8mCL }, 153 { X86::SAR8ri, X86::SAR8mi }, 154 { X86::SBB32ri, X86::SBB32mi }, 155 { X86::SBB32ri8, X86::SBB32mi8 }, 156 { X86::SBB32rr, X86::SBB32mr }, 157 { X86::SBB64ri32, X86::SBB64mi32 }, 158 { X86::SBB64ri8, X86::SBB64mi8 }, 159 { X86::SBB64rr, X86::SBB64mr }, 160 { X86::SHL16rCL, X86::SHL16mCL }, 161 { X86::SHL16ri, X86::SHL16mi }, 162 { X86::SHL32rCL, X86::SHL32mCL }, 163 { X86::SHL32ri, X86::SHL32mi }, 164 { X86::SHL64rCL, X86::SHL64mCL }, 165 { X86::SHL64ri, X86::SHL64mi }, 166 { X86::SHL8rCL, X86::SHL8mCL }, 167 { X86::SHL8ri, X86::SHL8mi }, 168 { X86::SHLD16rrCL, X86::SHLD16mrCL }, 169 { X86::SHLD16rri8, X86::SHLD16mri8 }, 170 { X86::SHLD32rrCL, X86::SHLD32mrCL }, 171 { X86::SHLD32rri8, X86::SHLD32mri8 }, 172 { X86::SHLD64rrCL, X86::SHLD64mrCL }, 173 { X86::SHLD64rri8, X86::SHLD64mri8 }, 174 { X86::SHR16r1, X86::SHR16m1 }, 175 { X86::SHR16rCL, X86::SHR16mCL }, 176 { X86::SHR16ri, X86::SHR16mi }, 177 { X86::SHR32r1, X86::SHR32m1 }, 178 { X86::SHR32rCL, X86::SHR32mCL }, 179 { X86::SHR32ri, X86::SHR32mi }, 180 { X86::SHR64r1, X86::SHR64m1 }, 181 { X86::SHR64rCL, X86::SHR64mCL }, 182 { X86::SHR64ri, X86::SHR64mi }, 183 { X86::SHR8r1, X86::SHR8m1 }, 184 { X86::SHR8rCL, X86::SHR8mCL }, 185 { X86::SHR8ri, X86::SHR8mi }, 186 { X86::SHRD16rrCL, X86::SHRD16mrCL }, 187 { X86::SHRD16rri8, X86::SHRD16mri8 }, 188 { X86::SHRD32rrCL, X86::SHRD32mrCL }, 189 { X86::SHRD32rri8, X86::SHRD32mri8 }, 190 { X86::SHRD64rrCL, X86::SHRD64mrCL }, 191 { X86::SHRD64rri8, X86::SHRD64mri8 }, 192 { X86::SUB16ri, X86::SUB16mi }, 193 { X86::SUB16ri8, X86::SUB16mi8 }, 194 { X86::SUB16rr, X86::SUB16mr }, 195 { X86::SUB32ri, X86::SUB32mi }, 196 { X86::SUB32ri8, X86::SUB32mi8 }, 197 { X86::SUB32rr, X86::SUB32mr }, 198 { X86::SUB64ri32, X86::SUB64mi32 }, 199 { X86::SUB64ri8, X86::SUB64mi8 }, 200 { X86::SUB64rr, X86::SUB64mr }, 201 { X86::SUB8ri, X86::SUB8mi }, 202 { X86::SUB8rr, X86::SUB8mr }, 203 { X86::XOR16ri, X86::XOR16mi }, 204 { X86::XOR16ri8, X86::XOR16mi8 }, 205 { X86::XOR16rr, X86::XOR16mr }, 206 { X86::XOR32ri, X86::XOR32mi }, 207 { X86::XOR32ri8, X86::XOR32mi8 }, 208 { X86::XOR32rr, X86::XOR32mr }, 209 { X86::XOR64ri32, X86::XOR64mi32 }, 210 { X86::XOR64ri8, X86::XOR64mi8 }, 211 { X86::XOR64rr, X86::XOR64mr }, 212 { X86::XOR8ri, X86::XOR8mi }, 213 { X86::XOR8rr, X86::XOR8mr } 214 }; 215 216 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 217 unsigned RegOp = OpTbl2Addr[i][0]; 218 unsigned MemOp = OpTbl2Addr[i][1]; 219 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, 220 std::make_pair(MemOp,0))).second) 221 assert(false && "Duplicated entries?"); 222 // Index 0, folded load and store, no alignment requirement. 223 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); 224 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 225 std::make_pair(RegOp, 226 AuxInfo))).second) 227 AmbEntries.push_back(MemOp); 228 } 229 230 // If the third value is 1, then it's folding either a load or a store. 231 static const unsigned OpTbl0[][4] = { 232 { X86::BT16ri8, X86::BT16mi8, 1, 0 }, 233 { X86::BT32ri8, X86::BT32mi8, 1, 0 }, 234 { X86::BT64ri8, X86::BT64mi8, 1, 0 }, 235 { X86::CALL32r, X86::CALL32m, 1, 0 }, 236 { X86::CALL64r, X86::CALL64m, 1, 0 }, 237 { X86::CMP16ri, X86::CMP16mi, 1, 0 }, 238 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 }, 239 { X86::CMP16rr, X86::CMP16mr, 1, 0 }, 240 { X86::CMP32ri, X86::CMP32mi, 1, 0 }, 241 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 }, 242 { X86::CMP32rr, X86::CMP32mr, 1, 0 }, 243 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 }, 244 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 }, 245 { X86::CMP64rr, X86::CMP64mr, 1, 0 }, 246 { X86::CMP8ri, X86::CMP8mi, 1, 0 }, 247 { X86::CMP8rr, X86::CMP8mr, 1, 0 }, 248 { X86::DIV16r, X86::DIV16m, 1, 0 }, 249 { X86::DIV32r, X86::DIV32m, 1, 0 }, 250 { X86::DIV64r, X86::DIV64m, 1, 0 }, 251 { X86::DIV8r, X86::DIV8m, 1, 0 }, 252 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 }, 253 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 }, 254 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 }, 255 { X86::IDIV16r, X86::IDIV16m, 1, 0 }, 256 { X86::IDIV32r, X86::IDIV32m, 1, 0 }, 257 { X86::IDIV64r, X86::IDIV64m, 1, 0 }, 258 { X86::IDIV8r, X86::IDIV8m, 1, 0 }, 259 { X86::IMUL16r, X86::IMUL16m, 1, 0 }, 260 { X86::IMUL32r, X86::IMUL32m, 1, 0 }, 261 { X86::IMUL64r, X86::IMUL64m, 1, 0 }, 262 { X86::IMUL8r, X86::IMUL8m, 1, 0 }, 263 { X86::JMP32r, X86::JMP32m, 1, 0 }, 264 { X86::JMP64r, X86::JMP64m, 1, 0 }, 265 { X86::MOV16ri, X86::MOV16mi, 0, 0 }, 266 { X86::MOV16rr, X86::MOV16mr, 0, 0 }, 267 { X86::MOV32ri, X86::MOV32mi, 0, 0 }, 268 { X86::MOV32rr, X86::MOV32mr, 0, 0 }, 269 { X86::MOV32rr_TC, X86::MOV32mr_TC, 0, 0 }, 270 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 }, 271 { X86::MOV64rr, X86::MOV64mr, 0, 0 }, 272 { X86::MOV8ri, X86::MOV8mi, 0, 0 }, 273 { X86::MOV8rr, X86::MOV8mr, 0, 0 }, 274 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 }, 275 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 }, 276 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 }, 277 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 }, 278 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 }, 279 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 }, 280 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 }, 281 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 }, 282 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 }, 283 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 }, 284 { X86::MUL16r, X86::MUL16m, 1, 0 }, 285 { X86::MUL32r, X86::MUL32m, 1, 0 }, 286 { X86::MUL64r, X86::MUL64m, 1, 0 }, 287 { X86::MUL8r, X86::MUL8m, 1, 0 }, 288 { X86::SETAEr, X86::SETAEm, 0, 0 }, 289 { X86::SETAr, X86::SETAm, 0, 0 }, 290 { X86::SETBEr, X86::SETBEm, 0, 0 }, 291 { X86::SETBr, X86::SETBm, 0, 0 }, 292 { X86::SETEr, X86::SETEm, 0, 0 }, 293 { X86::SETGEr, X86::SETGEm, 0, 0 }, 294 { X86::SETGr, X86::SETGm, 0, 0 }, 295 { X86::SETLEr, X86::SETLEm, 0, 0 }, 296 { X86::SETLr, X86::SETLm, 0, 0 }, 297 { X86::SETNEr, X86::SETNEm, 0, 0 }, 298 { X86::SETNOr, X86::SETNOm, 0, 0 }, 299 { X86::SETNPr, X86::SETNPm, 0, 0 }, 300 { X86::SETNSr, X86::SETNSm, 0, 0 }, 301 { X86::SETOr, X86::SETOm, 0, 0 }, 302 { X86::SETPr, X86::SETPm, 0, 0 }, 303 { X86::SETSr, X86::SETSm, 0, 0 }, 304 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 }, 305 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 }, 306 { X86::TEST16ri, X86::TEST16mi, 1, 0 }, 307 { X86::TEST32ri, X86::TEST32mi, 1, 0 }, 308 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 }, 309 { X86::TEST8ri, X86::TEST8mi, 1, 0 } 310 }; 311 312 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 313 unsigned RegOp = OpTbl0[i][0]; 314 unsigned MemOp = OpTbl0[i][1]; 315 unsigned Align = OpTbl0[i][3]; 316 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, 317 std::make_pair(MemOp,Align))).second) 318 assert(false && "Duplicated entries?"); 319 unsigned FoldedLoad = OpTbl0[i][2]; 320 // Index 0, folded load or store. 321 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); 322 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 323 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 324 std::make_pair(RegOp, AuxInfo))).second) 325 AmbEntries.push_back(MemOp); 326 } 327 328 static const unsigned OpTbl1[][3] = { 329 { X86::CMP16rr, X86::CMP16rm, 0 }, 330 { X86::CMP32rr, X86::CMP32rm, 0 }, 331 { X86::CMP64rr, X86::CMP64rm, 0 }, 332 { X86::CMP8rr, X86::CMP8rm, 0 }, 333 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 334 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 335 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 336 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 337 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 338 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 339 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 340 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 341 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 342 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 343 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 }, 344 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 }, 345 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 346 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 347 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 348 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 349 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 350 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 351 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 352 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 353 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 354 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 355 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 }, 356 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 }, 357 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 }, 358 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 }, 359 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 }, 360 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 }, 361 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 }, 362 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 }, 363 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 364 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 365 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 366 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 367 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 368 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 369 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 }, 370 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 }, 371 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 }, 372 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 }, 373 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 374 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 375 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 376 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 377 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 378 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 379 { X86::MOV16rr, X86::MOV16rm, 0 }, 380 { X86::MOV32rr, X86::MOV32rm, 0 }, 381 { X86::MOV32rr_TC, X86::MOV32rm_TC, 0 }, 382 { X86::MOV64rr, X86::MOV64rm, 0 }, 383 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 384 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 385 { X86::MOV8rr, X86::MOV8rm, 0 }, 386 { X86::MOVAPDrr, X86::MOVAPDrm, 16 }, 387 { X86::MOVAPSrr, X86::MOVAPSrm, 16 }, 388 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 389 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 390 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 391 { X86::MOVDQArr, X86::MOVDQArm, 16 }, 392 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 }, 393 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 }, 394 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 395 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 396 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 397 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 398 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 399 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 400 { X86::MOVUPDrr, X86::MOVUPDrm, 16 }, 401 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 402 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 }, 403 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 404 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 }, 405 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 406 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 407 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 408 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 409 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 }, 410 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 }, 411 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 }, 412 { X86::PSHUFDri, X86::PSHUFDmi, 16 }, 413 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 }, 414 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 }, 415 { X86::RCPPSr, X86::RCPPSm, 16 }, 416 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 }, 417 { X86::RSQRTPSr, X86::RSQRTPSm, 16 }, 418 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 }, 419 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 420 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 421 { X86::SQRTPDr, X86::SQRTPDm, 16 }, 422 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 }, 423 { X86::SQRTPSr, X86::SQRTPSm, 16 }, 424 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 }, 425 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 426 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 427 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 428 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 429 { X86::TEST16rr, X86::TEST16rm, 0 }, 430 { X86::TEST32rr, X86::TEST32rm, 0 }, 431 { X86::TEST64rr, X86::TEST64rm, 0 }, 432 { X86::TEST8rr, X86::TEST8rm, 0 }, 433 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 434 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 435 { X86::UCOMISSrr, X86::UCOMISSrm, 0 } 436 }; 437 438 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 439 unsigned RegOp = OpTbl1[i][0]; 440 unsigned MemOp = OpTbl1[i][1]; 441 unsigned Align = OpTbl1[i][2]; 442 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, 443 std::make_pair(MemOp,Align))).second) 444 assert(false && "Duplicated entries?"); 445 // Index 1, folded load 446 unsigned AuxInfo = 1 | (1 << 4); 447 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 448 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 449 std::make_pair(RegOp, AuxInfo))).second) 450 AmbEntries.push_back(MemOp); 451 } 452 453 static const unsigned OpTbl2[][3] = { 454 { X86::ADC32rr, X86::ADC32rm, 0 }, 455 { X86::ADC64rr, X86::ADC64rm, 0 }, 456 { X86::ADD16rr, X86::ADD16rm, 0 }, 457 { X86::ADD32rr, X86::ADD32rm, 0 }, 458 { X86::ADD64rr, X86::ADD64rm, 0 }, 459 { X86::ADD8rr, X86::ADD8rm, 0 }, 460 { X86::ADDPDrr, X86::ADDPDrm, 16 }, 461 { X86::ADDPSrr, X86::ADDPSrm, 16 }, 462 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 463 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 464 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 }, 465 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 }, 466 { X86::AND16rr, X86::AND16rm, 0 }, 467 { X86::AND32rr, X86::AND32rm, 0 }, 468 { X86::AND64rr, X86::AND64rm, 0 }, 469 { X86::AND8rr, X86::AND8rm, 0 }, 470 { X86::ANDNPDrr, X86::ANDNPDrm, 16 }, 471 { X86::ANDNPSrr, X86::ANDNPSrm, 16 }, 472 { X86::ANDPDrr, X86::ANDPDrm, 16 }, 473 { X86::ANDPSrr, X86::ANDPSrm, 16 }, 474 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 475 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 476 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 477 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 478 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 479 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 480 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 481 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 482 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 483 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 484 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 485 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 486 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 487 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 488 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 489 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 490 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 491 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 492 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 493 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 494 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 495 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 496 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 497 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 498 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 499 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 500 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 501 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 502 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 503 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 504 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 505 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 506 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 507 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 508 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 509 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 510 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 511 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 512 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 513 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 514 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 515 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 516 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 517 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 518 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 519 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 520 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 521 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 522 { X86::CMPPDrri, X86::CMPPDrmi, 16 }, 523 { X86::CMPPSrri, X86::CMPPSrmi, 16 }, 524 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 525 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 526 { X86::DIVPDrr, X86::DIVPDrm, 16 }, 527 { X86::DIVPSrr, X86::DIVPSrm, 16 }, 528 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 529 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 530 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 }, 531 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 }, 532 { X86::FsANDPDrr, X86::FsANDPDrm, 16 }, 533 { X86::FsANDPSrr, X86::FsANDPSrm, 16 }, 534 { X86::FsORPDrr, X86::FsORPDrm, 16 }, 535 { X86::FsORPSrr, X86::FsORPSrm, 16 }, 536 { X86::FsXORPDrr, X86::FsXORPDrm, 16 }, 537 { X86::FsXORPSrr, X86::FsXORPSrm, 16 }, 538 { X86::HADDPDrr, X86::HADDPDrm, 16 }, 539 { X86::HADDPSrr, X86::HADDPSrm, 16 }, 540 { X86::HSUBPDrr, X86::HSUBPDrm, 16 }, 541 { X86::HSUBPSrr, X86::HSUBPSrm, 16 }, 542 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 543 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 544 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 545 { X86::MAXPDrr, X86::MAXPDrm, 16 }, 546 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 }, 547 { X86::MAXPSrr, X86::MAXPSrm, 16 }, 548 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 }, 549 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 550 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 }, 551 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 552 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 }, 553 { X86::MINPDrr, X86::MINPDrm, 16 }, 554 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 }, 555 { X86::MINPSrr, X86::MINPSrm, 16 }, 556 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 }, 557 { X86::MINSDrr, X86::MINSDrm, 0 }, 558 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 }, 559 { X86::MINSSrr, X86::MINSSrm, 0 }, 560 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 }, 561 { X86::MULPDrr, X86::MULPDrm, 16 }, 562 { X86::MULPSrr, X86::MULPSrm, 16 }, 563 { X86::MULSDrr, X86::MULSDrm, 0 }, 564 { X86::MULSSrr, X86::MULSSrm, 0 }, 565 { X86::OR16rr, X86::OR16rm, 0 }, 566 { X86::OR32rr, X86::OR32rm, 0 }, 567 { X86::OR64rr, X86::OR64rm, 0 }, 568 { X86::OR8rr, X86::OR8rm, 0 }, 569 { X86::ORPDrr, X86::ORPDrm, 16 }, 570 { X86::ORPSrr, X86::ORPSrm, 16 }, 571 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 }, 572 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 }, 573 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 }, 574 { X86::PADDBrr, X86::PADDBrm, 16 }, 575 { X86::PADDDrr, X86::PADDDrm, 16 }, 576 { X86::PADDQrr, X86::PADDQrm, 16 }, 577 { X86::PADDSBrr, X86::PADDSBrm, 16 }, 578 { X86::PADDSWrr, X86::PADDSWrm, 16 }, 579 { X86::PADDWrr, X86::PADDWrm, 16 }, 580 { X86::PANDNrr, X86::PANDNrm, 16 }, 581 { X86::PANDrr, X86::PANDrm, 16 }, 582 { X86::PAVGBrr, X86::PAVGBrm, 16 }, 583 { X86::PAVGWrr, X86::PAVGWrm, 16 }, 584 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 }, 585 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 }, 586 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 }, 587 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 }, 588 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 }, 589 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 }, 590 { X86::PINSRWrri, X86::PINSRWrmi, 16 }, 591 { X86::PMADDWDrr, X86::PMADDWDrm, 16 }, 592 { X86::PMAXSWrr, X86::PMAXSWrm, 16 }, 593 { X86::PMAXUBrr, X86::PMAXUBrm, 16 }, 594 { X86::PMINSWrr, X86::PMINSWrm, 16 }, 595 { X86::PMINUBrr, X86::PMINUBrm, 16 }, 596 { X86::PMULDQrr, X86::PMULDQrm, 16 }, 597 { X86::PMULHUWrr, X86::PMULHUWrm, 16 }, 598 { X86::PMULHWrr, X86::PMULHWrm, 16 }, 599 { X86::PMULLDrr, X86::PMULLDrm, 16 }, 600 { X86::PMULLDrr_int, X86::PMULLDrm_int, 16 }, 601 { X86::PMULLWrr, X86::PMULLWrm, 16 }, 602 { X86::PMULUDQrr, X86::PMULUDQrm, 16 }, 603 { X86::PORrr, X86::PORrm, 16 }, 604 { X86::PSADBWrr, X86::PSADBWrm, 16 }, 605 { X86::PSLLDrr, X86::PSLLDrm, 16 }, 606 { X86::PSLLQrr, X86::PSLLQrm, 16 }, 607 { X86::PSLLWrr, X86::PSLLWrm, 16 }, 608 { X86::PSRADrr, X86::PSRADrm, 16 }, 609 { X86::PSRAWrr, X86::PSRAWrm, 16 }, 610 { X86::PSRLDrr, X86::PSRLDrm, 16 }, 611 { X86::PSRLQrr, X86::PSRLQrm, 16 }, 612 { X86::PSRLWrr, X86::PSRLWrm, 16 }, 613 { X86::PSUBBrr, X86::PSUBBrm, 16 }, 614 { X86::PSUBDrr, X86::PSUBDrm, 16 }, 615 { X86::PSUBSBrr, X86::PSUBSBrm, 16 }, 616 { X86::PSUBSWrr, X86::PSUBSWrm, 16 }, 617 { X86::PSUBWrr, X86::PSUBWrm, 16 }, 618 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 }, 619 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 }, 620 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 }, 621 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 }, 622 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 }, 623 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 }, 624 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 }, 625 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 }, 626 { X86::PXORrr, X86::PXORrm, 16 }, 627 { X86::SBB32rr, X86::SBB32rm, 0 }, 628 { X86::SBB64rr, X86::SBB64rm, 0 }, 629 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 }, 630 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 }, 631 { X86::SUB16rr, X86::SUB16rm, 0 }, 632 { X86::SUB32rr, X86::SUB32rm, 0 }, 633 { X86::SUB64rr, X86::SUB64rm, 0 }, 634 { X86::SUB8rr, X86::SUB8rm, 0 }, 635 { X86::SUBPDrr, X86::SUBPDrm, 16 }, 636 { X86::SUBPSrr, X86::SUBPSrm, 16 }, 637 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 638 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 639 // FIXME: TEST*rr -> swapped operand of TEST*mr. 640 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 }, 641 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 }, 642 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 }, 643 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 }, 644 { X86::XOR16rr, X86::XOR16rm, 0 }, 645 { X86::XOR32rr, X86::XOR32rm, 0 }, 646 { X86::XOR64rr, X86::XOR64rm, 0 }, 647 { X86::XOR8rr, X86::XOR8rm, 0 }, 648 { X86::XORPDrr, X86::XORPDrm, 16 }, 649 { X86::XORPSrr, X86::XORPSrm, 16 } 650 }; 651 652 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 653 unsigned RegOp = OpTbl2[i][0]; 654 unsigned MemOp = OpTbl2[i][1]; 655 unsigned Align = OpTbl2[i][2]; 656 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, 657 std::make_pair(MemOp,Align))).second) 658 assert(false && "Duplicated entries?"); 659 // Index 2, folded load 660 unsigned AuxInfo = 2 | (1 << 4); 661 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 662 std::make_pair(RegOp, AuxInfo))).second) 663 AmbEntries.push_back(MemOp); 664 } 665 666 // Remove ambiguous entries. 667 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?"); 668} 669 670bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, 671 unsigned &SrcReg, unsigned &DstReg, 672 unsigned &SrcSubIdx, unsigned &DstSubIdx) const { 673 switch (MI.getOpcode()) { 674 default: 675 return false; 676 case X86::MOV8rr: 677 case X86::MOV8rr_NOREX: 678 case X86::MOV16rr: 679 case X86::MOV32rr: 680 case X86::MOV64rr: 681 case X86::MOV32rr_TC: 682 case X86::MOV64rr_TC: 683 684 // FP Stack register class copies 685 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080: 686 case X86::MOV_Fp3264: case X86::MOV_Fp3280: 687 case X86::MOV_Fp6432: case X86::MOV_Fp8032: 688 689 // Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and FR64 690 // copies are done with FsMOVAPSrr and FsMOVAPDrr. 691 692 case X86::FsMOVAPSrr: 693 case X86::FsMOVAPDrr: 694 case X86::MOVAPSrr: 695 case X86::MOVAPDrr: 696 case X86::MOVDQArr: 697 case X86::MMX_MOVQ64rr: 698 assert(MI.getNumOperands() >= 2 && 699 MI.getOperand(0).isReg() && 700 MI.getOperand(1).isReg() && 701 "invalid register-register move instruction"); 702 SrcReg = MI.getOperand(1).getReg(); 703 DstReg = MI.getOperand(0).getReg(); 704 SrcSubIdx = MI.getOperand(1).getSubReg(); 705 DstSubIdx = MI.getOperand(0).getSubReg(); 706 return true; 707 } 708} 709 710bool 711X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 712 unsigned &SrcReg, unsigned &DstReg, 713 unsigned &SubIdx) const { 714 switch (MI.getOpcode()) { 715 default: break; 716 case X86::MOVSX16rr8: 717 case X86::MOVZX16rr8: 718 case X86::MOVSX32rr8: 719 case X86::MOVZX32rr8: 720 case X86::MOVSX64rr8: 721 case X86::MOVZX64rr8: 722 if (!TM.getSubtarget<X86Subtarget>().is64Bit()) 723 // It's not always legal to reference the low 8-bit of the larger 724 // register in 32-bit mode. 725 return false; 726 case X86::MOVSX32rr16: 727 case X86::MOVZX32rr16: 728 case X86::MOVSX64rr16: 729 case X86::MOVZX64rr16: 730 case X86::MOVSX64rr32: 731 case X86::MOVZX64rr32: { 732 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 733 // Be conservative. 734 return false; 735 SrcReg = MI.getOperand(1).getReg(); 736 DstReg = MI.getOperand(0).getReg(); 737 switch (MI.getOpcode()) { 738 default: 739 llvm_unreachable(0); 740 break; 741 case X86::MOVSX16rr8: 742 case X86::MOVZX16rr8: 743 case X86::MOVSX32rr8: 744 case X86::MOVZX32rr8: 745 case X86::MOVSX64rr8: 746 case X86::MOVZX64rr8: 747 SubIdx = 1; 748 break; 749 case X86::MOVSX32rr16: 750 case X86::MOVZX32rr16: 751 case X86::MOVSX64rr16: 752 case X86::MOVZX64rr16: 753 SubIdx = 3; 754 break; 755 case X86::MOVSX64rr32: 756 case X86::MOVZX64rr32: 757 SubIdx = 4; 758 break; 759 } 760 return true; 761 } 762 } 763 return false; 764} 765 766/// isFrameOperand - Return true and the FrameIndex if the specified 767/// operand and follow operands form a reference to the stack frame. 768bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 769 int &FrameIndex) const { 770 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() && 771 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() && 772 MI->getOperand(Op+1).getImm() == 1 && 773 MI->getOperand(Op+2).getReg() == 0 && 774 MI->getOperand(Op+3).getImm() == 0) { 775 FrameIndex = MI->getOperand(Op).getIndex(); 776 return true; 777 } 778 return false; 779} 780 781static bool isFrameLoadOpcode(int Opcode) { 782 switch (Opcode) { 783 default: break; 784 case X86::MOV8rm: 785 case X86::MOV16rm: 786 case X86::MOV32rm: 787 case X86::MOV64rm: 788 case X86::LD_Fp64m: 789 case X86::MOVSSrm: 790 case X86::MOVSDrm: 791 case X86::MOVAPSrm: 792 case X86::MOVAPDrm: 793 case X86::MOVDQArm: 794 case X86::MMX_MOVD64rm: 795 case X86::MMX_MOVQ64rm: 796 return true; 797 break; 798 } 799 return false; 800} 801 802static bool isFrameStoreOpcode(int Opcode) { 803 switch (Opcode) { 804 default: break; 805 case X86::MOV8mr: 806 case X86::MOV16mr: 807 case X86::MOV32mr: 808 case X86::MOV64mr: 809 case X86::ST_FpP64m: 810 case X86::MOVSSmr: 811 case X86::MOVSDmr: 812 case X86::MOVAPSmr: 813 case X86::MOVAPDmr: 814 case X86::MOVDQAmr: 815 case X86::MMX_MOVD64mr: 816 case X86::MMX_MOVQ64mr: 817 case X86::MMX_MOVNTQmr: 818 return true; 819 } 820 return false; 821} 822 823unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 824 int &FrameIndex) const { 825 if (isFrameLoadOpcode(MI->getOpcode())) 826 if (isFrameOperand(MI, 1, FrameIndex)) 827 return MI->getOperand(0).getReg(); 828 return 0; 829} 830 831unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 832 int &FrameIndex) const { 833 if (isFrameLoadOpcode(MI->getOpcode())) { 834 unsigned Reg; 835 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 836 return Reg; 837 // Check for post-frame index elimination operations 838 const MachineMemOperand *Dummy; 839 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 840 } 841 return 0; 842} 843 844bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, 845 const MachineMemOperand *&MMO, 846 int &FrameIndex) const { 847 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 848 oe = MI->memoperands_end(); 849 o != oe; 850 ++o) { 851 if ((*o)->isLoad() && (*o)->getValue()) 852 if (const FixedStackPseudoSourceValue *Value = 853 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 854 FrameIndex = Value->getFrameIndex(); 855 MMO = *o; 856 return true; 857 } 858 } 859 return false; 860} 861 862unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 863 int &FrameIndex) const { 864 if (isFrameStoreOpcode(MI->getOpcode())) 865 if (isFrameOperand(MI, 0, FrameIndex)) 866 return MI->getOperand(X86AddrNumOperands).getReg(); 867 return 0; 868} 869 870unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 871 int &FrameIndex) const { 872 if (isFrameStoreOpcode(MI->getOpcode())) { 873 unsigned Reg; 874 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 875 return Reg; 876 // Check for post-frame index elimination operations 877 const MachineMemOperand *Dummy; 878 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 879 } 880 return 0; 881} 882 883bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI, 884 const MachineMemOperand *&MMO, 885 int &FrameIndex) const { 886 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 887 oe = MI->memoperands_end(); 888 o != oe; 889 ++o) { 890 if ((*o)->isStore() && (*o)->getValue()) 891 if (const FixedStackPseudoSourceValue *Value = 892 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 893 FrameIndex = Value->getFrameIndex(); 894 MMO = *o; 895 return true; 896 } 897 } 898 return false; 899} 900 901/// regIsPICBase - Return true if register is PIC base (i.e.g defined by 902/// X86::MOVPC32r. 903static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 904 bool isPICBase = false; 905 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 906 E = MRI.def_end(); I != E; ++I) { 907 MachineInstr *DefMI = I.getOperand().getParent(); 908 if (DefMI->getOpcode() != X86::MOVPC32r) 909 return false; 910 assert(!isPICBase && "More than one PIC base?"); 911 isPICBase = true; 912 } 913 return isPICBase; 914} 915 916bool 917X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 918 AliasAnalysis *AA) const { 919 switch (MI->getOpcode()) { 920 default: break; 921 case X86::MOV8rm: 922 case X86::MOV16rm: 923 case X86::MOV32rm: 924 case X86::MOV64rm: 925 case X86::LD_Fp64m: 926 case X86::MOVSSrm: 927 case X86::MOVSDrm: 928 case X86::MOVAPSrm: 929 case X86::MOVUPSrm: 930 case X86::MOVUPSrm_Int: 931 case X86::MOVAPDrm: 932 case X86::MOVDQArm: 933 case X86::MMX_MOVD64rm: 934 case X86::MMX_MOVQ64rm: 935 case X86::FsMOVAPSrm: 936 case X86::FsMOVAPDrm: { 937 // Loads from constant pools are trivially rematerializable. 938 if (MI->getOperand(1).isReg() && 939 MI->getOperand(2).isImm() && 940 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 941 MI->isInvariantLoad(AA)) { 942 unsigned BaseReg = MI->getOperand(1).getReg(); 943 if (BaseReg == 0 || BaseReg == X86::RIP) 944 return true; 945 // Allow re-materialization of PIC load. 946 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 947 return false; 948 const MachineFunction &MF = *MI->getParent()->getParent(); 949 const MachineRegisterInfo &MRI = MF.getRegInfo(); 950 bool isPICBase = false; 951 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 952 E = MRI.def_end(); I != E; ++I) { 953 MachineInstr *DefMI = I.getOperand().getParent(); 954 if (DefMI->getOpcode() != X86::MOVPC32r) 955 return false; 956 assert(!isPICBase && "More than one PIC base?"); 957 isPICBase = true; 958 } 959 return isPICBase; 960 } 961 return false; 962 } 963 964 case X86::LEA32r: 965 case X86::LEA64r: { 966 if (MI->getOperand(2).isImm() && 967 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 968 !MI->getOperand(4).isReg()) { 969 // lea fi#, lea GV, etc. are all rematerializable. 970 if (!MI->getOperand(1).isReg()) 971 return true; 972 unsigned BaseReg = MI->getOperand(1).getReg(); 973 if (BaseReg == 0) 974 return true; 975 // Allow re-materialization of lea PICBase + x. 976 const MachineFunction &MF = *MI->getParent()->getParent(); 977 const MachineRegisterInfo &MRI = MF.getRegInfo(); 978 return regIsPICBase(BaseReg, MRI); 979 } 980 return false; 981 } 982 } 983 984 // All other instructions marked M_REMATERIALIZABLE are always trivially 985 // rematerializable. 986 return true; 987} 988 989/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 990/// would clobber the EFLAGS condition register. Note the result may be 991/// conservative. If it cannot definitely determine the safety after visiting 992/// a few instructions in each direction it assumes it's not safe. 993static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 994 MachineBasicBlock::iterator I) { 995 // It's always safe to clobber EFLAGS at the end of a block. 996 if (I == MBB.end()) 997 return true; 998 999 // For compile time consideration, if we are not able to determine the 1000 // safety after visiting 4 instructions in each direction, we will assume 1001 // it's not safe. 1002 MachineBasicBlock::iterator Iter = I; 1003 for (unsigned i = 0; i < 4; ++i) { 1004 bool SeenDef = false; 1005 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1006 MachineOperand &MO = Iter->getOperand(j); 1007 if (!MO.isReg()) 1008 continue; 1009 if (MO.getReg() == X86::EFLAGS) { 1010 if (MO.isUse()) 1011 return false; 1012 SeenDef = true; 1013 } 1014 } 1015 1016 if (SeenDef) 1017 // This instruction defines EFLAGS, no need to look any further. 1018 return true; 1019 ++Iter; 1020 1021 // If we make it to the end of the block, it's safe to clobber EFLAGS. 1022 if (Iter == MBB.end()) 1023 return true; 1024 } 1025 1026 Iter = I; 1027 for (unsigned i = 0; i < 4; ++i) { 1028 // If we make it to the beginning of the block, it's safe to clobber 1029 // EFLAGS iff EFLAGS is not live-in. 1030 if (Iter == MBB.begin()) 1031 return !MBB.isLiveIn(X86::EFLAGS); 1032 1033 --Iter; 1034 bool SawKill = false; 1035 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1036 MachineOperand &MO = Iter->getOperand(j); 1037 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1038 if (MO.isDef()) return MO.isDead(); 1039 if (MO.isKill()) SawKill = true; 1040 } 1041 } 1042 1043 if (SawKill) 1044 // This instruction kills EFLAGS and doesn't redefine it, so 1045 // there's no need to look further. 1046 return true; 1047 } 1048 1049 // Conservative answer. 1050 return false; 1051} 1052 1053void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1054 MachineBasicBlock::iterator I, 1055 unsigned DestReg, unsigned SubIdx, 1056 const MachineInstr *Orig, 1057 const TargetRegisterInfo *TRI) const { 1058 DebugLoc DL = MBB.findDebugLoc(I); 1059 1060 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) { 1061 DestReg = TRI->getSubReg(DestReg, SubIdx); 1062 SubIdx = 0; 1063 } 1064 1065 // MOV32r0 etc. are implemented with xor which clobbers condition code. 1066 // Re-materialize them as movri instructions to avoid side effects. 1067 bool Clone = true; 1068 unsigned Opc = Orig->getOpcode(); 1069 switch (Opc) { 1070 default: break; 1071 case X86::MOV8r0: 1072 case X86::MOV16r0: 1073 case X86::MOV32r0: 1074 case X86::MOV64r0: { 1075 if (!isSafeToClobberEFLAGS(MBB, I)) { 1076 switch (Opc) { 1077 default: break; 1078 case X86::MOV8r0: Opc = X86::MOV8ri; break; 1079 case X86::MOV16r0: Opc = X86::MOV16ri; break; 1080 case X86::MOV32r0: Opc = X86::MOV32ri; break; 1081 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break; 1082 } 1083 Clone = false; 1084 } 1085 break; 1086 } 1087 } 1088 1089 if (Clone) { 1090 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1091 MI->getOperand(0).setReg(DestReg); 1092 MBB.insert(I, MI); 1093 } else { 1094 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0); 1095 } 1096 1097 MachineInstr *NewMI = prior(I); 1098 NewMI->getOperand(0).setSubReg(SubIdx); 1099} 1100 1101/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 1102/// is not marked dead. 1103static bool hasLiveCondCodeDef(MachineInstr *MI) { 1104 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1105 MachineOperand &MO = MI->getOperand(i); 1106 if (MO.isReg() && MO.isDef() && 1107 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 1108 return true; 1109 } 1110 } 1111 return false; 1112} 1113 1114/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 1115/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 1116/// to a 32-bit superregister and then truncating back down to a 16-bit 1117/// subregister. 1118MachineInstr * 1119X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 1120 MachineFunction::iterator &MFI, 1121 MachineBasicBlock::iterator &MBBI, 1122 LiveVariables *LV) const { 1123 MachineInstr *MI = MBBI; 1124 unsigned Dest = MI->getOperand(0).getReg(); 1125 unsigned Src = MI->getOperand(1).getReg(); 1126 bool isDead = MI->getOperand(0).isDead(); 1127 bool isKill = MI->getOperand(1).isKill(); 1128 1129 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1130 ? X86::LEA64_32r : X86::LEA32r; 1131 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1132 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1133 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1134 1135 // Build and insert into an implicit UNDEF value. This is OK because 1136 // well be shifting and then extracting the lower 16-bits. 1137 // This has the potential to cause partial register stall. e.g. 1138 // movw (%rbp,%rcx,2), %dx 1139 // leal -65(%rdx), %esi 1140 // But testing has shown this *does* help performance in 64-bit mode (at 1141 // least on modern x86 machines). 1142 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1143 MachineInstr *InsMI = 1144 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg) 1145 .addReg(leaInReg) 1146 .addReg(Src, getKillRegState(isKill)) 1147 .addImm(X86::SUBREG_16BIT); 1148 1149 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 1150 get(Opc), leaOutReg); 1151 switch (MIOpc) { 1152 default: 1153 llvm_unreachable(0); 1154 break; 1155 case X86::SHL16ri: { 1156 unsigned ShAmt = MI->getOperand(2).getImm(); 1157 MIB.addReg(0).addImm(1 << ShAmt) 1158 .addReg(leaInReg, RegState::Kill).addImm(0); 1159 break; 1160 } 1161 case X86::INC16r: 1162 case X86::INC64_16r: 1163 addLeaRegOffset(MIB, leaInReg, true, 1); 1164 break; 1165 case X86::DEC16r: 1166 case X86::DEC64_16r: 1167 addLeaRegOffset(MIB, leaInReg, true, -1); 1168 break; 1169 case X86::ADD16ri: 1170 case X86::ADD16ri8: 1171 addLeaRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1172 break; 1173 case X86::ADD16rr: { 1174 unsigned Src2 = MI->getOperand(2).getReg(); 1175 bool isKill2 = MI->getOperand(2).isKill(); 1176 unsigned leaInReg2 = 0; 1177 MachineInstr *InsMI2 = 0; 1178 if (Src == Src2) { 1179 // ADD16rr %reg1028<kill>, %reg1028 1180 // just a single insert_subreg. 1181 addRegReg(MIB, leaInReg, true, leaInReg, false); 1182 } else { 1183 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1184 // Build and insert into an implicit UNDEF value. This is OK because 1185 // well be shifting and then extracting the lower 16-bits. 1186 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2); 1187 InsMI2 = 1188 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg2) 1189 .addReg(leaInReg2) 1190 .addReg(Src2, getKillRegState(isKill2)) 1191 .addImm(X86::SUBREG_16BIT); 1192 addRegReg(MIB, leaInReg, true, leaInReg2, true); 1193 } 1194 if (LV && isKill2 && InsMI2) 1195 LV->replaceKillInstruction(Src2, MI, InsMI2); 1196 break; 1197 } 1198 } 1199 1200 MachineInstr *NewMI = MIB; 1201 MachineInstr *ExtMI = 1202 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG)) 1203 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1204 .addReg(leaOutReg, RegState::Kill) 1205 .addImm(X86::SUBREG_16BIT); 1206 1207 if (LV) { 1208 // Update live variables 1209 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1210 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1211 if (isKill) 1212 LV->replaceKillInstruction(Src, MI, InsMI); 1213 if (isDead) 1214 LV->replaceKillInstruction(Dest, MI, ExtMI); 1215 } 1216 1217 return ExtMI; 1218} 1219 1220/// convertToThreeAddress - This method must be implemented by targets that 1221/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1222/// may be able to convert a two-address instruction into a true 1223/// three-address instruction on demand. This allows the X86 target (for 1224/// example) to convert ADD and SHL instructions into LEA instructions if they 1225/// would require register copies due to two-addressness. 1226/// 1227/// This method returns a null pointer if the transformation cannot be 1228/// performed, otherwise it returns the new instruction. 1229/// 1230MachineInstr * 1231X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1232 MachineBasicBlock::iterator &MBBI, 1233 LiveVariables *LV) const { 1234 MachineInstr *MI = MBBI; 1235 MachineFunction &MF = *MI->getParent()->getParent(); 1236 // All instructions input are two-addr instructions. Get the known operands. 1237 unsigned Dest = MI->getOperand(0).getReg(); 1238 unsigned Src = MI->getOperand(1).getReg(); 1239 bool isDead = MI->getOperand(0).isDead(); 1240 bool isKill = MI->getOperand(1).isKill(); 1241 1242 MachineInstr *NewMI = NULL; 1243 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1244 // we have better subtarget support, enable the 16-bit LEA generation here. 1245 // 16-bit LEA is also slow on Core2. 1246 bool DisableLEA16 = true; 1247 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1248 1249 unsigned MIOpc = MI->getOpcode(); 1250 switch (MIOpc) { 1251 case X86::SHUFPSrri: { 1252 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1253 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1254 1255 unsigned B = MI->getOperand(1).getReg(); 1256 unsigned C = MI->getOperand(2).getReg(); 1257 if (B != C) return 0; 1258 unsigned A = MI->getOperand(0).getReg(); 1259 unsigned M = MI->getOperand(3).getImm(); 1260 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1261 .addReg(A, RegState::Define | getDeadRegState(isDead)) 1262 .addReg(B, getKillRegState(isKill)).addImm(M); 1263 break; 1264 } 1265 case X86::SHL64ri: { 1266 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1267 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1268 // the flags produced by a shift yet, so this is safe. 1269 unsigned ShAmt = MI->getOperand(2).getImm(); 1270 if (ShAmt == 0 || ShAmt >= 4) return 0; 1271 1272 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1273 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1274 .addReg(0).addImm(1 << ShAmt) 1275 .addReg(Src, getKillRegState(isKill)) 1276 .addImm(0); 1277 break; 1278 } 1279 case X86::SHL32ri: { 1280 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1281 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1282 // the flags produced by a shift yet, so this is safe. 1283 unsigned ShAmt = MI->getOperand(2).getImm(); 1284 if (ShAmt == 0 || ShAmt >= 4) return 0; 1285 1286 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1287 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1288 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1289 .addReg(0).addImm(1 << ShAmt) 1290 .addReg(Src, getKillRegState(isKill)).addImm(0); 1291 break; 1292 } 1293 case X86::SHL16ri: { 1294 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1295 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1296 // the flags produced by a shift yet, so this is safe. 1297 unsigned ShAmt = MI->getOperand(2).getImm(); 1298 if (ShAmt == 0 || ShAmt >= 4) return 0; 1299 1300 if (DisableLEA16) 1301 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1302 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1303 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1304 .addReg(0).addImm(1 << ShAmt) 1305 .addReg(Src, getKillRegState(isKill)) 1306 .addImm(0); 1307 break; 1308 } 1309 default: { 1310 // The following opcodes also sets the condition code register(s). Only 1311 // convert them to equivalent lea if the condition code register def's 1312 // are dead! 1313 if (hasLiveCondCodeDef(MI)) 1314 return 0; 1315 1316 switch (MIOpc) { 1317 default: return 0; 1318 case X86::INC64r: 1319 case X86::INC32r: 1320 case X86::INC64_32r: { 1321 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1322 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 1323 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1324 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1325 .addReg(Dest, RegState::Define | 1326 getDeadRegState(isDead)), 1327 Src, isKill, 1); 1328 break; 1329 } 1330 case X86::INC16r: 1331 case X86::INC64_16r: 1332 if (DisableLEA16) 1333 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1334 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1335 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1336 .addReg(Dest, RegState::Define | 1337 getDeadRegState(isDead)), 1338 Src, isKill, 1); 1339 break; 1340 case X86::DEC64r: 1341 case X86::DEC32r: 1342 case X86::DEC64_32r: { 1343 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1344 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 1345 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1346 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1347 .addReg(Dest, RegState::Define | 1348 getDeadRegState(isDead)), 1349 Src, isKill, -1); 1350 break; 1351 } 1352 case X86::DEC16r: 1353 case X86::DEC64_16r: 1354 if (DisableLEA16) 1355 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1356 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1357 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1358 .addReg(Dest, RegState::Define | 1359 getDeadRegState(isDead)), 1360 Src, isKill, -1); 1361 break; 1362 case X86::ADD64rr: 1363 case X86::ADD32rr: { 1364 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1365 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r 1366 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1367 unsigned Src2 = MI->getOperand(2).getReg(); 1368 bool isKill2 = MI->getOperand(2).isKill(); 1369 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1370 .addReg(Dest, RegState::Define | 1371 getDeadRegState(isDead)), 1372 Src, isKill, Src2, isKill2); 1373 if (LV && isKill2) 1374 LV->replaceKillInstruction(Src2, MI, NewMI); 1375 break; 1376 } 1377 case X86::ADD16rr: { 1378 if (DisableLEA16) 1379 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1380 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1381 unsigned Src2 = MI->getOperand(2).getReg(); 1382 bool isKill2 = MI->getOperand(2).isKill(); 1383 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1384 .addReg(Dest, RegState::Define | 1385 getDeadRegState(isDead)), 1386 Src, isKill, Src2, isKill2); 1387 if (LV && isKill2) 1388 LV->replaceKillInstruction(Src2, MI, NewMI); 1389 break; 1390 } 1391 case X86::ADD64ri32: 1392 case X86::ADD64ri8: 1393 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1394 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1395 .addReg(Dest, RegState::Define | 1396 getDeadRegState(isDead)), 1397 Src, isKill, MI->getOperand(2).getImm()); 1398 break; 1399 case X86::ADD32ri: 1400 case X86::ADD32ri8: { 1401 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1402 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1403 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1404 .addReg(Dest, RegState::Define | 1405 getDeadRegState(isDead)), 1406 Src, isKill, MI->getOperand(2).getImm()); 1407 break; 1408 } 1409 case X86::ADD16ri: 1410 case X86::ADD16ri8: 1411 if (DisableLEA16) 1412 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1413 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1414 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1415 .addReg(Dest, RegState::Define | 1416 getDeadRegState(isDead)), 1417 Src, isKill, MI->getOperand(2).getImm()); 1418 break; 1419 } 1420 } 1421 } 1422 1423 if (!NewMI) return 0; 1424 1425 if (LV) { // Update live variables 1426 if (isKill) 1427 LV->replaceKillInstruction(Src, MI, NewMI); 1428 if (isDead) 1429 LV->replaceKillInstruction(Dest, MI, NewMI); 1430 } 1431 1432 MFI->insert(MBBI, NewMI); // Insert the new inst 1433 return NewMI; 1434} 1435 1436/// commuteInstruction - We have a few instructions that must be hacked on to 1437/// commute them. 1438/// 1439MachineInstr * 1440X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1441 switch (MI->getOpcode()) { 1442 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 1443 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 1444 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 1445 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 1446 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 1447 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 1448 unsigned Opc; 1449 unsigned Size; 1450 switch (MI->getOpcode()) { 1451 default: llvm_unreachable("Unreachable!"); 1452 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 1453 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 1454 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 1455 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 1456 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 1457 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 1458 } 1459 unsigned Amt = MI->getOperand(3).getImm(); 1460 if (NewMI) { 1461 MachineFunction &MF = *MI->getParent()->getParent(); 1462 MI = MF.CloneMachineInstr(MI); 1463 NewMI = false; 1464 } 1465 MI->setDesc(get(Opc)); 1466 MI->getOperand(3).setImm(Size-Amt); 1467 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1468 } 1469 case X86::CMOVB16rr: 1470 case X86::CMOVB32rr: 1471 case X86::CMOVB64rr: 1472 case X86::CMOVAE16rr: 1473 case X86::CMOVAE32rr: 1474 case X86::CMOVAE64rr: 1475 case X86::CMOVE16rr: 1476 case X86::CMOVE32rr: 1477 case X86::CMOVE64rr: 1478 case X86::CMOVNE16rr: 1479 case X86::CMOVNE32rr: 1480 case X86::CMOVNE64rr: 1481 case X86::CMOVBE16rr: 1482 case X86::CMOVBE32rr: 1483 case X86::CMOVBE64rr: 1484 case X86::CMOVA16rr: 1485 case X86::CMOVA32rr: 1486 case X86::CMOVA64rr: 1487 case X86::CMOVL16rr: 1488 case X86::CMOVL32rr: 1489 case X86::CMOVL64rr: 1490 case X86::CMOVGE16rr: 1491 case X86::CMOVGE32rr: 1492 case X86::CMOVGE64rr: 1493 case X86::CMOVLE16rr: 1494 case X86::CMOVLE32rr: 1495 case X86::CMOVLE64rr: 1496 case X86::CMOVG16rr: 1497 case X86::CMOVG32rr: 1498 case X86::CMOVG64rr: 1499 case X86::CMOVS16rr: 1500 case X86::CMOVS32rr: 1501 case X86::CMOVS64rr: 1502 case X86::CMOVNS16rr: 1503 case X86::CMOVNS32rr: 1504 case X86::CMOVNS64rr: 1505 case X86::CMOVP16rr: 1506 case X86::CMOVP32rr: 1507 case X86::CMOVP64rr: 1508 case X86::CMOVNP16rr: 1509 case X86::CMOVNP32rr: 1510 case X86::CMOVNP64rr: 1511 case X86::CMOVO16rr: 1512 case X86::CMOVO32rr: 1513 case X86::CMOVO64rr: 1514 case X86::CMOVNO16rr: 1515 case X86::CMOVNO32rr: 1516 case X86::CMOVNO64rr: { 1517 unsigned Opc = 0; 1518 switch (MI->getOpcode()) { 1519 default: break; 1520 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 1521 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 1522 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 1523 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 1524 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 1525 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 1526 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 1527 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 1528 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 1529 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 1530 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 1531 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 1532 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 1533 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 1534 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 1535 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 1536 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 1537 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 1538 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 1539 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 1540 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 1541 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 1542 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 1543 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 1544 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 1545 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 1546 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 1547 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 1548 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 1549 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 1550 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 1551 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 1552 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 1553 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 1554 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 1555 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 1556 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 1557 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 1558 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 1559 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 1560 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 1561 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 1562 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 1563 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 1564 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 1565 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 1566 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 1567 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 1568 } 1569 if (NewMI) { 1570 MachineFunction &MF = *MI->getParent()->getParent(); 1571 MI = MF.CloneMachineInstr(MI); 1572 NewMI = false; 1573 } 1574 MI->setDesc(get(Opc)); 1575 // Fallthrough intended. 1576 } 1577 default: 1578 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1579 } 1580} 1581 1582static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { 1583 switch (BrOpc) { 1584 default: return X86::COND_INVALID; 1585 case X86::JE_4: return X86::COND_E; 1586 case X86::JNE_4: return X86::COND_NE; 1587 case X86::JL_4: return X86::COND_L; 1588 case X86::JLE_4: return X86::COND_LE; 1589 case X86::JG_4: return X86::COND_G; 1590 case X86::JGE_4: return X86::COND_GE; 1591 case X86::JB_4: return X86::COND_B; 1592 case X86::JBE_4: return X86::COND_BE; 1593 case X86::JA_4: return X86::COND_A; 1594 case X86::JAE_4: return X86::COND_AE; 1595 case X86::JS_4: return X86::COND_S; 1596 case X86::JNS_4: return X86::COND_NS; 1597 case X86::JP_4: return X86::COND_P; 1598 case X86::JNP_4: return X86::COND_NP; 1599 case X86::JO_4: return X86::COND_O; 1600 case X86::JNO_4: return X86::COND_NO; 1601 } 1602} 1603 1604unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 1605 switch (CC) { 1606 default: llvm_unreachable("Illegal condition code!"); 1607 case X86::COND_E: return X86::JE_4; 1608 case X86::COND_NE: return X86::JNE_4; 1609 case X86::COND_L: return X86::JL_4; 1610 case X86::COND_LE: return X86::JLE_4; 1611 case X86::COND_G: return X86::JG_4; 1612 case X86::COND_GE: return X86::JGE_4; 1613 case X86::COND_B: return X86::JB_4; 1614 case X86::COND_BE: return X86::JBE_4; 1615 case X86::COND_A: return X86::JA_4; 1616 case X86::COND_AE: return X86::JAE_4; 1617 case X86::COND_S: return X86::JS_4; 1618 case X86::COND_NS: return X86::JNS_4; 1619 case X86::COND_P: return X86::JP_4; 1620 case X86::COND_NP: return X86::JNP_4; 1621 case X86::COND_O: return X86::JO_4; 1622 case X86::COND_NO: return X86::JNO_4; 1623 } 1624} 1625 1626/// GetOppositeBranchCondition - Return the inverse of the specified condition, 1627/// e.g. turning COND_E to COND_NE. 1628X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 1629 switch (CC) { 1630 default: llvm_unreachable("Illegal condition code!"); 1631 case X86::COND_E: return X86::COND_NE; 1632 case X86::COND_NE: return X86::COND_E; 1633 case X86::COND_L: return X86::COND_GE; 1634 case X86::COND_LE: return X86::COND_G; 1635 case X86::COND_G: return X86::COND_LE; 1636 case X86::COND_GE: return X86::COND_L; 1637 case X86::COND_B: return X86::COND_AE; 1638 case X86::COND_BE: return X86::COND_A; 1639 case X86::COND_A: return X86::COND_BE; 1640 case X86::COND_AE: return X86::COND_B; 1641 case X86::COND_S: return X86::COND_NS; 1642 case X86::COND_NS: return X86::COND_S; 1643 case X86::COND_P: return X86::COND_NP; 1644 case X86::COND_NP: return X86::COND_P; 1645 case X86::COND_O: return X86::COND_NO; 1646 case X86::COND_NO: return X86::COND_O; 1647 } 1648} 1649 1650bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 1651 const TargetInstrDesc &TID = MI->getDesc(); 1652 if (!TID.isTerminator()) return false; 1653 1654 // Conditional branch is a special case. 1655 if (TID.isBranch() && !TID.isBarrier()) 1656 return true; 1657 if (!TID.isPredicable()) 1658 return true; 1659 return !isPredicated(MI); 1660} 1661 1662// For purposes of branch analysis do not count FP_REG_KILL as a terminator. 1663static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI, 1664 const X86InstrInfo &TII) { 1665 if (MI->getOpcode() == X86::FP_REG_KILL) 1666 return false; 1667 return TII.isUnpredicatedTerminator(MI); 1668} 1669 1670bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 1671 MachineBasicBlock *&TBB, 1672 MachineBasicBlock *&FBB, 1673 SmallVectorImpl<MachineOperand> &Cond, 1674 bool AllowModify) const { 1675 // Start from the bottom of the block and work up, examining the 1676 // terminator instructions. 1677 MachineBasicBlock::iterator I = MBB.end(); 1678 while (I != MBB.begin()) { 1679 --I; 1680 1681 // Working from the bottom, when we see a non-terminator instruction, we're 1682 // done. 1683 if (!isBrAnalysisUnpredicatedTerminator(I, *this)) 1684 break; 1685 1686 // A terminator that isn't a branch can't easily be handled by this 1687 // analysis. 1688 if (!I->getDesc().isBranch()) 1689 return true; 1690 1691 // Handle unconditional branches. 1692 if (I->getOpcode() == X86::JMP_4) { 1693 if (!AllowModify) { 1694 TBB = I->getOperand(0).getMBB(); 1695 continue; 1696 } 1697 1698 // If the block has any instructions after a JMP, delete them. 1699 while (llvm::next(I) != MBB.end()) 1700 llvm::next(I)->eraseFromParent(); 1701 1702 Cond.clear(); 1703 FBB = 0; 1704 1705 // Delete the JMP if it's equivalent to a fall-through. 1706 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 1707 TBB = 0; 1708 I->eraseFromParent(); 1709 I = MBB.end(); 1710 continue; 1711 } 1712 1713 // TBB is used to indicate the unconditinal destination. 1714 TBB = I->getOperand(0).getMBB(); 1715 continue; 1716 } 1717 1718 // Handle conditional branches. 1719 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode()); 1720 if (BranchCode == X86::COND_INVALID) 1721 return true; // Can't handle indirect branch. 1722 1723 // Working from the bottom, handle the first conditional branch. 1724 if (Cond.empty()) { 1725 FBB = TBB; 1726 TBB = I->getOperand(0).getMBB(); 1727 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 1728 continue; 1729 } 1730 1731 // Handle subsequent conditional branches. Only handle the case where all 1732 // conditional branches branch to the same destination and their condition 1733 // opcodes fit one of the special multi-branch idioms. 1734 assert(Cond.size() == 1); 1735 assert(TBB); 1736 1737 // Only handle the case where all conditional branches branch to the same 1738 // destination. 1739 if (TBB != I->getOperand(0).getMBB()) 1740 return true; 1741 1742 // If the conditions are the same, we can leave them alone. 1743 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 1744 if (OldBranchCode == BranchCode) 1745 continue; 1746 1747 // If they differ, see if they fit one of the known patterns. Theoretically, 1748 // we could handle more patterns here, but we shouldn't expect to see them 1749 // if instruction selection has done a reasonable job. 1750 if ((OldBranchCode == X86::COND_NP && 1751 BranchCode == X86::COND_E) || 1752 (OldBranchCode == X86::COND_E && 1753 BranchCode == X86::COND_NP)) 1754 BranchCode = X86::COND_NP_OR_E; 1755 else if ((OldBranchCode == X86::COND_P && 1756 BranchCode == X86::COND_NE) || 1757 (OldBranchCode == X86::COND_NE && 1758 BranchCode == X86::COND_P)) 1759 BranchCode = X86::COND_NE_OR_P; 1760 else 1761 return true; 1762 1763 // Update the MachineOperand. 1764 Cond[0].setImm(BranchCode); 1765 } 1766 1767 return false; 1768} 1769 1770unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 1771 MachineBasicBlock::iterator I = MBB.end(); 1772 unsigned Count = 0; 1773 1774 while (I != MBB.begin()) { 1775 --I; 1776 if (I->getOpcode() != X86::JMP_4 && 1777 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 1778 break; 1779 // Remove the branch. 1780 I->eraseFromParent(); 1781 I = MBB.end(); 1782 ++Count; 1783 } 1784 1785 return Count; 1786} 1787 1788unsigned 1789X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 1790 MachineBasicBlock *FBB, 1791 const SmallVectorImpl<MachineOperand> &Cond) const { 1792 // FIXME this should probably have a DebugLoc operand 1793 DebugLoc dl = DebugLoc::getUnknownLoc(); 1794 // Shouldn't be a fall through. 1795 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 1796 assert((Cond.size() == 1 || Cond.size() == 0) && 1797 "X86 branch conditions have one component!"); 1798 1799 if (Cond.empty()) { 1800 // Unconditional branch? 1801 assert(!FBB && "Unconditional branch with multiple successors!"); 1802 BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(TBB); 1803 return 1; 1804 } 1805 1806 // Conditional branch. 1807 unsigned Count = 0; 1808 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 1809 switch (CC) { 1810 case X86::COND_NP_OR_E: 1811 // Synthesize NP_OR_E with two branches. 1812 BuildMI(&MBB, dl, get(X86::JNP_4)).addMBB(TBB); 1813 ++Count; 1814 BuildMI(&MBB, dl, get(X86::JE_4)).addMBB(TBB); 1815 ++Count; 1816 break; 1817 case X86::COND_NE_OR_P: 1818 // Synthesize NE_OR_P with two branches. 1819 BuildMI(&MBB, dl, get(X86::JNE_4)).addMBB(TBB); 1820 ++Count; 1821 BuildMI(&MBB, dl, get(X86::JP_4)).addMBB(TBB); 1822 ++Count; 1823 break; 1824 default: { 1825 unsigned Opc = GetCondBranchFromCond(CC); 1826 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB); 1827 ++Count; 1828 } 1829 } 1830 if (FBB) { 1831 // Two-way Conditional branch. Insert the second branch. 1832 BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(FBB); 1833 ++Count; 1834 } 1835 return Count; 1836} 1837 1838/// isHReg - Test if the given register is a physical h register. 1839static bool isHReg(unsigned Reg) { 1840 return X86::GR8_ABCD_HRegClass.contains(Reg); 1841} 1842 1843bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, 1844 MachineBasicBlock::iterator MI, 1845 unsigned DestReg, unsigned SrcReg, 1846 const TargetRegisterClass *DestRC, 1847 const TargetRegisterClass *SrcRC) const { 1848 DebugLoc DL = MBB.findDebugLoc(MI); 1849 1850 // Determine if DstRC and SrcRC have a common superclass in common. 1851 const TargetRegisterClass *CommonRC = DestRC; 1852 if (DestRC == SrcRC) 1853 /* Source and destination have the same register class. */; 1854 else if (CommonRC->hasSuperClass(SrcRC)) 1855 CommonRC = SrcRC; 1856 else if (!DestRC->hasSubClass(SrcRC)) { 1857 // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other, 1858 // but we want to copy them as GR64. Similarly, for GR32_NOREX and 1859 // GR32_NOSP, copy as GR32. 1860 if (SrcRC->hasSuperClass(&X86::GR64RegClass) && 1861 DestRC->hasSuperClass(&X86::GR64RegClass)) 1862 CommonRC = &X86::GR64RegClass; 1863 else if (SrcRC->hasSuperClass(&X86::GR32RegClass) && 1864 DestRC->hasSuperClass(&X86::GR32RegClass)) 1865 CommonRC = &X86::GR32RegClass; 1866 else 1867 CommonRC = 0; 1868 } 1869 1870 if (CommonRC) { 1871 unsigned Opc; 1872 if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) { 1873 Opc = X86::MOV64rr; 1874 } else if (CommonRC == &X86::GR32RegClass || 1875 CommonRC == &X86::GR32_NOSPRegClass) { 1876 Opc = X86::MOV32rr; 1877 } else if (CommonRC == &X86::GR16RegClass) { 1878 Opc = X86::MOV16rr; 1879 } else if (CommonRC == &X86::GR8RegClass) { 1880 // Copying to or from a physical H register on x86-64 requires a NOREX 1881 // move. Otherwise use a normal move. 1882 if ((isHReg(DestReg) || isHReg(SrcReg)) && 1883 TM.getSubtarget<X86Subtarget>().is64Bit()) 1884 Opc = X86::MOV8rr_NOREX; 1885 else 1886 Opc = X86::MOV8rr; 1887 } else if (CommonRC == &X86::GR64_ABCDRegClass) { 1888 Opc = X86::MOV64rr; 1889 } else if (CommonRC == &X86::GR32_ABCDRegClass) { 1890 Opc = X86::MOV32rr; 1891 } else if (CommonRC == &X86::GR16_ABCDRegClass) { 1892 Opc = X86::MOV16rr; 1893 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) { 1894 Opc = X86::MOV8rr; 1895 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) { 1896 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 1897 Opc = X86::MOV8rr_NOREX; 1898 else 1899 Opc = X86::MOV8rr; 1900 } else if (CommonRC == &X86::GR64_NOREXRegClass || 1901 CommonRC == &X86::GR64_NOREX_NOSPRegClass) { 1902 Opc = X86::MOV64rr; 1903 } else if (CommonRC == &X86::GR32_NOREXRegClass) { 1904 Opc = X86::MOV32rr; 1905 } else if (CommonRC == &X86::GR16_NOREXRegClass) { 1906 Opc = X86::MOV16rr; 1907 } else if (CommonRC == &X86::GR8_NOREXRegClass) { 1908 Opc = X86::MOV8rr; 1909 } else if (CommonRC == &X86::GR64_TCRegClass) { 1910 Opc = X86::MOV64rr_TC; 1911 } else if (CommonRC == &X86::GR32_TCRegClass) { 1912 Opc = X86::MOV32rr_TC; 1913 } else if (CommonRC == &X86::RFP32RegClass) { 1914 Opc = X86::MOV_Fp3232; 1915 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) { 1916 Opc = X86::MOV_Fp6464; 1917 } else if (CommonRC == &X86::RFP80RegClass) { 1918 Opc = X86::MOV_Fp8080; 1919 } else if (CommonRC == &X86::FR32RegClass) { 1920 Opc = X86::FsMOVAPSrr; 1921 } else if (CommonRC == &X86::FR64RegClass) { 1922 Opc = X86::FsMOVAPDrr; 1923 } else if (CommonRC == &X86::VR128RegClass) { 1924 Opc = X86::MOVAPSrr; 1925 } else if (CommonRC == &X86::VR64RegClass) { 1926 Opc = X86::MMX_MOVQ64rr; 1927 } else { 1928 return false; 1929 } 1930 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg); 1931 return true; 1932 } 1933 1934 // Moving EFLAGS to / from another register requires a push and a pop. 1935 if (SrcRC == &X86::CCRRegClass) { 1936 if (SrcReg != X86::EFLAGS) 1937 return false; 1938 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) { 1939 BuildMI(MBB, MI, DL, get(X86::PUSHFQ64)); 1940 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 1941 return true; 1942 } else if (DestRC == &X86::GR32RegClass || 1943 DestRC == &X86::GR32_NOSPRegClass) { 1944 BuildMI(MBB, MI, DL, get(X86::PUSHFD)); 1945 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 1946 return true; 1947 } 1948 } else if (DestRC == &X86::CCRRegClass) { 1949 if (DestReg != X86::EFLAGS) 1950 return false; 1951 if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) { 1952 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg); 1953 BuildMI(MBB, MI, DL, get(X86::POPFQ)); 1954 return true; 1955 } else if (SrcRC == &X86::GR32RegClass || 1956 DestRC == &X86::GR32_NOSPRegClass) { 1957 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg); 1958 BuildMI(MBB, MI, DL, get(X86::POPFD)); 1959 return true; 1960 } 1961 } 1962 1963 // Moving from ST(0) turns into FpGET_ST0_32 etc. 1964 if (SrcRC == &X86::RSTRegClass) { 1965 // Copying from ST(0)/ST(1). 1966 if (SrcReg != X86::ST0 && SrcReg != X86::ST1) 1967 // Can only copy from ST(0)/ST(1) right now 1968 return false; 1969 bool isST0 = SrcReg == X86::ST0; 1970 unsigned Opc; 1971 if (DestRC == &X86::RFP32RegClass) 1972 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32; 1973 else if (DestRC == &X86::RFP64RegClass) 1974 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64; 1975 else { 1976 if (DestRC != &X86::RFP80RegClass) 1977 return false; 1978 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80; 1979 } 1980 BuildMI(MBB, MI, DL, get(Opc), DestReg); 1981 return true; 1982 } 1983 1984 // Moving to ST(0) turns into FpSET_ST0_32 etc. 1985 if (DestRC == &X86::RSTRegClass) { 1986 // Copying to ST(0) / ST(1). 1987 if (DestReg != X86::ST0 && DestReg != X86::ST1) 1988 // Can only copy to TOS right now 1989 return false; 1990 bool isST0 = DestReg == X86::ST0; 1991 unsigned Opc; 1992 if (SrcRC == &X86::RFP32RegClass) 1993 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32; 1994 else if (SrcRC == &X86::RFP64RegClass) 1995 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64; 1996 else { 1997 if (SrcRC != &X86::RFP80RegClass) 1998 return false; 1999 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80; 2000 } 2001 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg); 2002 return true; 2003 } 2004 2005 // Not yet supported! 2006 return false; 2007} 2008 2009static unsigned getStoreRegOpcode(unsigned SrcReg, 2010 const TargetRegisterClass *RC, 2011 bool isStackAligned, 2012 TargetMachine &TM) { 2013 unsigned Opc = 0; 2014 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) { 2015 Opc = X86::MOV64mr; 2016 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) { 2017 Opc = X86::MOV32mr; 2018 } else if (RC == &X86::GR16RegClass) { 2019 Opc = X86::MOV16mr; 2020 } else if (RC == &X86::GR8RegClass) { 2021 // Copying to or from a physical H register on x86-64 requires a NOREX 2022 // move. Otherwise use a normal move. 2023 if (isHReg(SrcReg) && 2024 TM.getSubtarget<X86Subtarget>().is64Bit()) 2025 Opc = X86::MOV8mr_NOREX; 2026 else 2027 Opc = X86::MOV8mr; 2028 } else if (RC == &X86::GR64_ABCDRegClass) { 2029 Opc = X86::MOV64mr; 2030 } else if (RC == &X86::GR32_ABCDRegClass) { 2031 Opc = X86::MOV32mr; 2032 } else if (RC == &X86::GR16_ABCDRegClass) { 2033 Opc = X86::MOV16mr; 2034 } else if (RC == &X86::GR8_ABCD_LRegClass) { 2035 Opc = X86::MOV8mr; 2036 } else if (RC == &X86::GR8_ABCD_HRegClass) { 2037 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2038 Opc = X86::MOV8mr_NOREX; 2039 else 2040 Opc = X86::MOV8mr; 2041 } else if (RC == &X86::GR64_NOREXRegClass || 2042 RC == &X86::GR64_NOREX_NOSPRegClass) { 2043 Opc = X86::MOV64mr; 2044 } else if (RC == &X86::GR32_NOREXRegClass) { 2045 Opc = X86::MOV32mr; 2046 } else if (RC == &X86::GR16_NOREXRegClass) { 2047 Opc = X86::MOV16mr; 2048 } else if (RC == &X86::GR8_NOREXRegClass) { 2049 Opc = X86::MOV8mr; 2050 } else if (RC == &X86::GR64_TCRegClass) { 2051 Opc = X86::MOV64mr_TC; 2052 } else if (RC == &X86::GR32_TCRegClass) { 2053 Opc = X86::MOV32mr_TC; 2054 } else if (RC == &X86::RFP80RegClass) { 2055 Opc = X86::ST_FpP80m; // pops 2056 } else if (RC == &X86::RFP64RegClass) { 2057 Opc = X86::ST_Fp64m; 2058 } else if (RC == &X86::RFP32RegClass) { 2059 Opc = X86::ST_Fp32m; 2060 } else if (RC == &X86::FR32RegClass) { 2061 Opc = X86::MOVSSmr; 2062 } else if (RC == &X86::FR64RegClass) { 2063 Opc = X86::MOVSDmr; 2064 } else if (RC == &X86::VR128RegClass) { 2065 // If stack is realigned we can use aligned stores. 2066 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr; 2067 } else if (RC == &X86::VR64RegClass) { 2068 Opc = X86::MMX_MOVQ64mr; 2069 } else { 2070 llvm_unreachable("Unknown regclass"); 2071 } 2072 2073 return Opc; 2074} 2075 2076void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 2077 MachineBasicBlock::iterator MI, 2078 unsigned SrcReg, bool isKill, int FrameIdx, 2079 const TargetRegisterClass *RC) const { 2080 const MachineFunction &MF = *MBB.getParent(); 2081 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF); 2082 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2083 DebugLoc DL = MBB.findDebugLoc(MI); 2084 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 2085 .addReg(SrcReg, getKillRegState(isKill)); 2086} 2087 2088void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 2089 bool isKill, 2090 SmallVectorImpl<MachineOperand> &Addr, 2091 const TargetRegisterClass *RC, 2092 MachineInstr::mmo_iterator MMOBegin, 2093 MachineInstr::mmo_iterator MMOEnd, 2094 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2095 bool isAligned = (*MMOBegin)->getAlignment() >= 16; 2096 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2097 DebugLoc DL = DebugLoc::getUnknownLoc(); 2098 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 2099 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2100 MIB.addOperand(Addr[i]); 2101 MIB.addReg(SrcReg, getKillRegState(isKill)); 2102 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2103 NewMIs.push_back(MIB); 2104} 2105 2106static unsigned getLoadRegOpcode(unsigned DestReg, 2107 const TargetRegisterClass *RC, 2108 bool isStackAligned, 2109 const TargetMachine &TM) { 2110 unsigned Opc = 0; 2111 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) { 2112 Opc = X86::MOV64rm; 2113 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) { 2114 Opc = X86::MOV32rm; 2115 } else if (RC == &X86::GR16RegClass) { 2116 Opc = X86::MOV16rm; 2117 } else if (RC == &X86::GR8RegClass) { 2118 // Copying to or from a physical H register on x86-64 requires a NOREX 2119 // move. Otherwise use a normal move. 2120 if (isHReg(DestReg) && 2121 TM.getSubtarget<X86Subtarget>().is64Bit()) 2122 Opc = X86::MOV8rm_NOREX; 2123 else 2124 Opc = X86::MOV8rm; 2125 } else if (RC == &X86::GR64_ABCDRegClass) { 2126 Opc = X86::MOV64rm; 2127 } else if (RC == &X86::GR32_ABCDRegClass) { 2128 Opc = X86::MOV32rm; 2129 } else if (RC == &X86::GR16_ABCDRegClass) { 2130 Opc = X86::MOV16rm; 2131 } else if (RC == &X86::GR8_ABCD_LRegClass) { 2132 Opc = X86::MOV8rm; 2133 } else if (RC == &X86::GR8_ABCD_HRegClass) { 2134 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2135 Opc = X86::MOV8rm_NOREX; 2136 else 2137 Opc = X86::MOV8rm; 2138 } else if (RC == &X86::GR64_NOREXRegClass || 2139 RC == &X86::GR64_NOREX_NOSPRegClass) { 2140 Opc = X86::MOV64rm; 2141 } else if (RC == &X86::GR32_NOREXRegClass) { 2142 Opc = X86::MOV32rm; 2143 } else if (RC == &X86::GR16_NOREXRegClass) { 2144 Opc = X86::MOV16rm; 2145 } else if (RC == &X86::GR8_NOREXRegClass) { 2146 Opc = X86::MOV8rm; 2147 } else if (RC == &X86::GR64_TCRegClass) { 2148 Opc = X86::MOV64rm_TC; 2149 } else if (RC == &X86::GR32_TCRegClass) { 2150 Opc = X86::MOV32rm_TC; 2151 } else if (RC == &X86::RFP80RegClass) { 2152 Opc = X86::LD_Fp80m; 2153 } else if (RC == &X86::RFP64RegClass) { 2154 Opc = X86::LD_Fp64m; 2155 } else if (RC == &X86::RFP32RegClass) { 2156 Opc = X86::LD_Fp32m; 2157 } else if (RC == &X86::FR32RegClass) { 2158 Opc = X86::MOVSSrm; 2159 } else if (RC == &X86::FR64RegClass) { 2160 Opc = X86::MOVSDrm; 2161 } else if (RC == &X86::VR128RegClass) { 2162 // If stack is realigned we can use aligned loads. 2163 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm; 2164 } else if (RC == &X86::VR64RegClass) { 2165 Opc = X86::MMX_MOVQ64rm; 2166 } else { 2167 llvm_unreachable("Unknown regclass"); 2168 } 2169 2170 return Opc; 2171} 2172 2173void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 2174 MachineBasicBlock::iterator MI, 2175 unsigned DestReg, int FrameIdx, 2176 const TargetRegisterClass *RC) const{ 2177 const MachineFunction &MF = *MBB.getParent(); 2178 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF); 2179 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2180 DebugLoc DL = MBB.findDebugLoc(MI); 2181 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 2182} 2183 2184void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 2185 SmallVectorImpl<MachineOperand> &Addr, 2186 const TargetRegisterClass *RC, 2187 MachineInstr::mmo_iterator MMOBegin, 2188 MachineInstr::mmo_iterator MMOEnd, 2189 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2190 bool isAligned = (*MMOBegin)->getAlignment() >= 16; 2191 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2192 DebugLoc DL = DebugLoc::getUnknownLoc(); 2193 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 2194 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2195 MIB.addOperand(Addr[i]); 2196 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2197 NewMIs.push_back(MIB); 2198} 2199 2200bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 2201 MachineBasicBlock::iterator MI, 2202 const std::vector<CalleeSavedInfo> &CSI) const { 2203 if (CSI.empty()) 2204 return false; 2205 2206 DebugLoc DL = MBB.findDebugLoc(MI); 2207 2208 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 2209 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64(); 2210 unsigned SlotSize = is64Bit ? 8 : 4; 2211 2212 MachineFunction &MF = *MBB.getParent(); 2213 unsigned FPReg = RI.getFrameRegister(MF); 2214 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 2215 unsigned CalleeFrameSize = 0; 2216 2217 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r; 2218 for (unsigned i = CSI.size(); i != 0; --i) { 2219 unsigned Reg = CSI[i-1].getReg(); 2220 const TargetRegisterClass *RegClass = CSI[i-1].getRegClass(); 2221 // Add the callee-saved register as live-in. It's killed at the spill. 2222 MBB.addLiveIn(Reg); 2223 if (Reg == FPReg) 2224 // X86RegisterInfo::emitPrologue will handle spilling of frame register. 2225 continue; 2226 if (RegClass != &X86::VR128RegClass && !isWin64) { 2227 CalleeFrameSize += SlotSize; 2228 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill); 2229 } else { 2230 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass); 2231 } 2232 } 2233 2234 X86FI->setCalleeSavedFrameSize(CalleeFrameSize); 2235 return true; 2236} 2237 2238bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 2239 MachineBasicBlock::iterator MI, 2240 const std::vector<CalleeSavedInfo> &CSI) const { 2241 if (CSI.empty()) 2242 return false; 2243 2244 DebugLoc DL = MBB.findDebugLoc(MI); 2245 2246 MachineFunction &MF = *MBB.getParent(); 2247 unsigned FPReg = RI.getFrameRegister(MF); 2248 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 2249 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64(); 2250 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r; 2251 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 2252 unsigned Reg = CSI[i].getReg(); 2253 if (Reg == FPReg) 2254 // X86RegisterInfo::emitEpilogue will handle restoring of frame register. 2255 continue; 2256 const TargetRegisterClass *RegClass = CSI[i].getRegClass(); 2257 if (RegClass != &X86::VR128RegClass && !isWin64) { 2258 BuildMI(MBB, MI, DL, get(Opc), Reg); 2259 } else { 2260 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass); 2261 } 2262 } 2263 return true; 2264} 2265 2266static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 2267 const SmallVectorImpl<MachineOperand> &MOs, 2268 MachineInstr *MI, 2269 const TargetInstrInfo &TII) { 2270 // Create the base instruction with the memory operand as the first part. 2271 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 2272 MI->getDebugLoc(), true); 2273 MachineInstrBuilder MIB(NewMI); 2274 unsigned NumAddrOps = MOs.size(); 2275 for (unsigned i = 0; i != NumAddrOps; ++i) 2276 MIB.addOperand(MOs[i]); 2277 if (NumAddrOps < 4) // FrameIndex only 2278 addOffset(MIB, 0); 2279 2280 // Loop over the rest of the ri operands, converting them over. 2281 unsigned NumOps = MI->getDesc().getNumOperands()-2; 2282 for (unsigned i = 0; i != NumOps; ++i) { 2283 MachineOperand &MO = MI->getOperand(i+2); 2284 MIB.addOperand(MO); 2285 } 2286 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 2287 MachineOperand &MO = MI->getOperand(i); 2288 MIB.addOperand(MO); 2289 } 2290 return MIB; 2291} 2292 2293static MachineInstr *FuseInst(MachineFunction &MF, 2294 unsigned Opcode, unsigned OpNo, 2295 const SmallVectorImpl<MachineOperand> &MOs, 2296 MachineInstr *MI, const TargetInstrInfo &TII) { 2297 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 2298 MI->getDebugLoc(), true); 2299 MachineInstrBuilder MIB(NewMI); 2300 2301 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2302 MachineOperand &MO = MI->getOperand(i); 2303 if (i == OpNo) { 2304 assert(MO.isReg() && "Expected to fold into reg operand!"); 2305 unsigned NumAddrOps = MOs.size(); 2306 for (unsigned i = 0; i != NumAddrOps; ++i) 2307 MIB.addOperand(MOs[i]); 2308 if (NumAddrOps < 4) // FrameIndex only 2309 addOffset(MIB, 0); 2310 } else { 2311 MIB.addOperand(MO); 2312 } 2313 } 2314 return MIB; 2315} 2316 2317static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 2318 const SmallVectorImpl<MachineOperand> &MOs, 2319 MachineInstr *MI) { 2320 MachineFunction &MF = *MI->getParent()->getParent(); 2321 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 2322 2323 unsigned NumAddrOps = MOs.size(); 2324 for (unsigned i = 0; i != NumAddrOps; ++i) 2325 MIB.addOperand(MOs[i]); 2326 if (NumAddrOps < 4) // FrameIndex only 2327 addOffset(MIB, 0); 2328 return MIB.addImm(0); 2329} 2330 2331MachineInstr* 2332X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2333 MachineInstr *MI, unsigned i, 2334 const SmallVectorImpl<MachineOperand> &MOs, 2335 unsigned Size, unsigned Align) const { 2336 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL; 2337 bool isTwoAddrFold = false; 2338 unsigned NumOps = MI->getDesc().getNumOperands(); 2339 bool isTwoAddr = NumOps > 1 && 2340 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2341 2342 MachineInstr *NewMI = NULL; 2343 // Folding a memory location into the two-address part of a two-address 2344 // instruction is different than folding it other places. It requires 2345 // replacing the *two* registers with the memory location. 2346 if (isTwoAddr && NumOps >= 2 && i < 2 && 2347 MI->getOperand(0).isReg() && 2348 MI->getOperand(1).isReg() && 2349 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 2350 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2351 isTwoAddrFold = true; 2352 } else if (i == 0) { // If operand 0 2353 if (MI->getOpcode() == X86::MOV64r0) 2354 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI); 2355 else if (MI->getOpcode() == X86::MOV32r0) 2356 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); 2357 else if (MI->getOpcode() == X86::MOV16r0) 2358 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI); 2359 else if (MI->getOpcode() == X86::MOV8r0) 2360 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI); 2361 if (NewMI) 2362 return NewMI; 2363 2364 OpcodeTablePtr = &RegOp2MemOpTable0; 2365 } else if (i == 1) { 2366 OpcodeTablePtr = &RegOp2MemOpTable1; 2367 } else if (i == 2) { 2368 OpcodeTablePtr = &RegOp2MemOpTable2; 2369 } 2370 2371 // If table selected... 2372 if (OpcodeTablePtr) { 2373 // Find the Opcode to fuse 2374 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2375 OpcodeTablePtr->find((unsigned*)MI->getOpcode()); 2376 if (I != OpcodeTablePtr->end()) { 2377 unsigned Opcode = I->second.first; 2378 unsigned MinAlign = I->second.second; 2379 if (Align < MinAlign) 2380 return NULL; 2381 bool NarrowToMOV32rm = false; 2382 if (Size) { 2383 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize(); 2384 if (Size < RCSize) { 2385 // Check if it's safe to fold the load. If the size of the object is 2386 // narrower than the load width, then it's not. 2387 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 2388 return NULL; 2389 // If this is a 64-bit load, but the spill slot is 32, then we can do 2390 // a 32-bit load which is implicitly zero-extended. This likely is due 2391 // to liveintervalanalysis remat'ing a load from stack slot. 2392 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 2393 return NULL; 2394 Opcode = X86::MOV32rm; 2395 NarrowToMOV32rm = true; 2396 } 2397 } 2398 2399 if (isTwoAddrFold) 2400 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 2401 else 2402 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 2403 2404 if (NarrowToMOV32rm) { 2405 // If this is the special case where we use a MOV32rm to load a 32-bit 2406 // value and zero-extend the top bits. Change the destination register 2407 // to a 32-bit one. 2408 unsigned DstReg = NewMI->getOperand(0).getReg(); 2409 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 2410 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, 2411 4/*x86_subreg_32bit*/)); 2412 else 2413 NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/); 2414 } 2415 return NewMI; 2416 } 2417 } 2418 2419 // No fusion 2420 if (PrintFailedFusing) 2421 dbgs() << "We failed to fuse operand " << i << " in " << *MI; 2422 return NULL; 2423} 2424 2425 2426MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2427 MachineInstr *MI, 2428 const SmallVectorImpl<unsigned> &Ops, 2429 int FrameIndex) const { 2430 // Check switch flag 2431 if (NoFusing) return NULL; 2432 2433 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2434 switch (MI->getOpcode()) { 2435 case X86::CVTSD2SSrr: 2436 case X86::Int_CVTSD2SSrr: 2437 case X86::CVTSS2SDrr: 2438 case X86::Int_CVTSS2SDrr: 2439 case X86::RCPSSr: 2440 case X86::RCPSSr_Int: 2441 case X86::ROUNDSDr_Int: 2442 case X86::ROUNDSSr_Int: 2443 case X86::RSQRTSSr: 2444 case X86::RSQRTSSr_Int: 2445 case X86::SQRTSSr: 2446 case X86::SQRTSSr_Int: 2447 return 0; 2448 } 2449 2450 const MachineFrameInfo *MFI = MF.getFrameInfo(); 2451 unsigned Size = MFI->getObjectSize(FrameIndex); 2452 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 2453 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2454 unsigned NewOpc = 0; 2455 unsigned RCSize = 0; 2456 switch (MI->getOpcode()) { 2457 default: return NULL; 2458 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 2459 case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break; 2460 case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break; 2461 case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break; 2462 } 2463 // Check if it's safe to fold the load. If the size of the object is 2464 // narrower than the load width, then it's not. 2465 if (Size < RCSize) 2466 return NULL; 2467 // Change to CMPXXri r, 0 first. 2468 MI->setDesc(get(NewOpc)); 2469 MI->getOperand(1).ChangeToImmediate(0); 2470 } else if (Ops.size() != 1) 2471 return NULL; 2472 2473 SmallVector<MachineOperand,4> MOs; 2474 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 2475 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment); 2476} 2477 2478MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2479 MachineInstr *MI, 2480 const SmallVectorImpl<unsigned> &Ops, 2481 MachineInstr *LoadMI) const { 2482 // Check switch flag 2483 if (NoFusing) return NULL; 2484 2485 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2486 switch (MI->getOpcode()) { 2487 case X86::CVTSD2SSrr: 2488 case X86::Int_CVTSD2SSrr: 2489 case X86::CVTSS2SDrr: 2490 case X86::Int_CVTSS2SDrr: 2491 case X86::RCPSSr: 2492 case X86::RCPSSr_Int: 2493 case X86::ROUNDSDr_Int: 2494 case X86::ROUNDSSr_Int: 2495 case X86::RSQRTSSr: 2496 case X86::RSQRTSSr_Int: 2497 case X86::SQRTSSr: 2498 case X86::SQRTSSr_Int: 2499 return 0; 2500 } 2501 2502 // Determine the alignment of the load. 2503 unsigned Alignment = 0; 2504 if (LoadMI->hasOneMemOperand()) 2505 Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 2506 else 2507 switch (LoadMI->getOpcode()) { 2508 case X86::V_SET0: 2509 case X86::V_SETALLONES: 2510 Alignment = 16; 2511 break; 2512 case X86::FsFLD0SD: 2513 Alignment = 8; 2514 break; 2515 case X86::FsFLD0SS: 2516 Alignment = 4; 2517 break; 2518 default: 2519 llvm_unreachable("Don't know how to fold this instruction!"); 2520 } 2521 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2522 unsigned NewOpc = 0; 2523 switch (MI->getOpcode()) { 2524 default: return NULL; 2525 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 2526 case X86::TEST16rr: NewOpc = X86::CMP16ri; break; 2527 case X86::TEST32rr: NewOpc = X86::CMP32ri; break; 2528 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; 2529 } 2530 // Change to CMPXXri r, 0 first. 2531 MI->setDesc(get(NewOpc)); 2532 MI->getOperand(1).ChangeToImmediate(0); 2533 } else if (Ops.size() != 1) 2534 return NULL; 2535 2536 SmallVector<MachineOperand,X86AddrNumOperands> MOs; 2537 switch (LoadMI->getOpcode()) { 2538 case X86::V_SET0: 2539 case X86::V_SETALLONES: 2540 case X86::FsFLD0SD: 2541 case X86::FsFLD0SS: { 2542 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 2543 // Create a constant-pool entry and operands to load from it. 2544 2545 // Medium and large mode can't fold loads this way. 2546 if (TM.getCodeModel() != CodeModel::Small && 2547 TM.getCodeModel() != CodeModel::Kernel) 2548 return NULL; 2549 2550 // x86-32 PIC requires a PIC base register for constant pools. 2551 unsigned PICBase = 0; 2552 if (TM.getRelocationModel() == Reloc::PIC_) { 2553 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2554 PICBase = X86::RIP; 2555 else 2556 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF); 2557 // This doesn't work for several reasons. 2558 // 1. GlobalBaseReg may have been spilled. 2559 // 2. It may not be live at MI. 2560 return NULL; 2561 } 2562 2563 // Create a constant-pool entry. 2564 MachineConstantPool &MCP = *MF.getConstantPool(); 2565 const Type *Ty; 2566 if (LoadMI->getOpcode() == X86::FsFLD0SS) 2567 Ty = Type::getFloatTy(MF.getFunction()->getContext()); 2568 else if (LoadMI->getOpcode() == X86::FsFLD0SD) 2569 Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 2570 else 2571 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 2572 Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ? 2573 Constant::getAllOnesValue(Ty) : 2574 Constant::getNullValue(Ty); 2575 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 2576 2577 // Create operands to load from the constant pool entry. 2578 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 2579 MOs.push_back(MachineOperand::CreateImm(1)); 2580 MOs.push_back(MachineOperand::CreateReg(0, false)); 2581 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 2582 MOs.push_back(MachineOperand::CreateReg(0, false)); 2583 break; 2584 } 2585 default: { 2586 // Folding a normal load. Just copy the load's address operands. 2587 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 2588 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i) 2589 MOs.push_back(LoadMI->getOperand(i)); 2590 break; 2591 } 2592 } 2593 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment); 2594} 2595 2596 2597bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 2598 const SmallVectorImpl<unsigned> &Ops) const { 2599 // Check switch flag 2600 if (NoFusing) return 0; 2601 2602 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2603 switch (MI->getOpcode()) { 2604 default: return false; 2605 case X86::TEST8rr: 2606 case X86::TEST16rr: 2607 case X86::TEST32rr: 2608 case X86::TEST64rr: 2609 return true; 2610 } 2611 } 2612 2613 if (Ops.size() != 1) 2614 return false; 2615 2616 unsigned OpNum = Ops[0]; 2617 unsigned Opc = MI->getOpcode(); 2618 unsigned NumOps = MI->getDesc().getNumOperands(); 2619 bool isTwoAddr = NumOps > 1 && 2620 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2621 2622 // Folding a memory location into the two-address part of a two-address 2623 // instruction is different than folding it other places. It requires 2624 // replacing the *two* registers with the memory location. 2625 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL; 2626 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 2627 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2628 } else if (OpNum == 0) { // If operand 0 2629 switch (Opc) { 2630 case X86::MOV8r0: 2631 case X86::MOV16r0: 2632 case X86::MOV32r0: 2633 case X86::MOV64r0: 2634 return true; 2635 default: break; 2636 } 2637 OpcodeTablePtr = &RegOp2MemOpTable0; 2638 } else if (OpNum == 1) { 2639 OpcodeTablePtr = &RegOp2MemOpTable1; 2640 } else if (OpNum == 2) { 2641 OpcodeTablePtr = &RegOp2MemOpTable2; 2642 } 2643 2644 if (OpcodeTablePtr) { 2645 // Find the Opcode to fuse 2646 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2647 OpcodeTablePtr->find((unsigned*)Opc); 2648 if (I != OpcodeTablePtr->end()) 2649 return true; 2650 } 2651 return false; 2652} 2653 2654bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 2655 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 2656 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2657 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2658 MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); 2659 if (I == MemOp2RegOpTable.end()) 2660 return false; 2661 unsigned Opc = I->second.first; 2662 unsigned Index = I->second.second & 0xf; 2663 bool FoldedLoad = I->second.second & (1 << 4); 2664 bool FoldedStore = I->second.second & (1 << 5); 2665 if (UnfoldLoad && !FoldedLoad) 2666 return false; 2667 UnfoldLoad &= FoldedLoad; 2668 if (UnfoldStore && !FoldedStore) 2669 return false; 2670 UnfoldStore &= FoldedStore; 2671 2672 const TargetInstrDesc &TID = get(Opc); 2673 const TargetOperandInfo &TOI = TID.OpInfo[Index]; 2674 const TargetRegisterClass *RC = TOI.getRegClass(&RI); 2675 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps; 2676 SmallVector<MachineOperand,2> BeforeOps; 2677 SmallVector<MachineOperand,2> AfterOps; 2678 SmallVector<MachineOperand,4> ImpOps; 2679 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2680 MachineOperand &Op = MI->getOperand(i); 2681 if (i >= Index && i < Index + X86AddrNumOperands) 2682 AddrOps.push_back(Op); 2683 else if (Op.isReg() && Op.isImplicit()) 2684 ImpOps.push_back(Op); 2685 else if (i < Index) 2686 BeforeOps.push_back(Op); 2687 else if (i > Index) 2688 AfterOps.push_back(Op); 2689 } 2690 2691 // Emit the load instruction. 2692 if (UnfoldLoad) { 2693 std::pair<MachineInstr::mmo_iterator, 2694 MachineInstr::mmo_iterator> MMOs = 2695 MF.extractLoadMemRefs(MI->memoperands_begin(), 2696 MI->memoperands_end()); 2697 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 2698 if (UnfoldStore) { 2699 // Address operands cannot be marked isKill. 2700 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) { 2701 MachineOperand &MO = NewMIs[0]->getOperand(i); 2702 if (MO.isReg()) 2703 MO.setIsKill(false); 2704 } 2705 } 2706 } 2707 2708 // Emit the data processing instruction. 2709 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true); 2710 MachineInstrBuilder MIB(DataMI); 2711 2712 if (FoldedStore) 2713 MIB.addReg(Reg, RegState::Define); 2714 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 2715 MIB.addOperand(BeforeOps[i]); 2716 if (FoldedLoad) 2717 MIB.addReg(Reg); 2718 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 2719 MIB.addOperand(AfterOps[i]); 2720 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 2721 MachineOperand &MO = ImpOps[i]; 2722 MIB.addReg(MO.getReg(), 2723 getDefRegState(MO.isDef()) | 2724 RegState::Implicit | 2725 getKillRegState(MO.isKill()) | 2726 getDeadRegState(MO.isDead()) | 2727 getUndefRegState(MO.isUndef())); 2728 } 2729 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 2730 unsigned NewOpc = 0; 2731 switch (DataMI->getOpcode()) { 2732 default: break; 2733 case X86::CMP64ri32: 2734 case X86::CMP32ri: 2735 case X86::CMP16ri: 2736 case X86::CMP8ri: { 2737 MachineOperand &MO0 = DataMI->getOperand(0); 2738 MachineOperand &MO1 = DataMI->getOperand(1); 2739 if (MO1.getImm() == 0) { 2740 switch (DataMI->getOpcode()) { 2741 default: break; 2742 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 2743 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 2744 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 2745 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 2746 } 2747 DataMI->setDesc(get(NewOpc)); 2748 MO1.ChangeToRegister(MO0.getReg(), false); 2749 } 2750 } 2751 } 2752 NewMIs.push_back(DataMI); 2753 2754 // Emit the store instruction. 2755 if (UnfoldStore) { 2756 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI); 2757 std::pair<MachineInstr::mmo_iterator, 2758 MachineInstr::mmo_iterator> MMOs = 2759 MF.extractStoreMemRefs(MI->memoperands_begin(), 2760 MI->memoperands_end()); 2761 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 2762 } 2763 2764 return true; 2765} 2766 2767bool 2768X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 2769 SmallVectorImpl<SDNode*> &NewNodes) const { 2770 if (!N->isMachineOpcode()) 2771 return false; 2772 2773 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2774 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode()); 2775 if (I == MemOp2RegOpTable.end()) 2776 return false; 2777 unsigned Opc = I->second.first; 2778 unsigned Index = I->second.second & 0xf; 2779 bool FoldedLoad = I->second.second & (1 << 4); 2780 bool FoldedStore = I->second.second & (1 << 5); 2781 const TargetInstrDesc &TID = get(Opc); 2782 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI); 2783 unsigned NumDefs = TID.NumDefs; 2784 std::vector<SDValue> AddrOps; 2785 std::vector<SDValue> BeforeOps; 2786 std::vector<SDValue> AfterOps; 2787 DebugLoc dl = N->getDebugLoc(); 2788 unsigned NumOps = N->getNumOperands(); 2789 for (unsigned i = 0; i != NumOps-1; ++i) { 2790 SDValue Op = N->getOperand(i); 2791 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands) 2792 AddrOps.push_back(Op); 2793 else if (i < Index-NumDefs) 2794 BeforeOps.push_back(Op); 2795 else if (i > Index-NumDefs) 2796 AfterOps.push_back(Op); 2797 } 2798 SDValue Chain = N->getOperand(NumOps-1); 2799 AddrOps.push_back(Chain); 2800 2801 // Emit the load instruction. 2802 SDNode *Load = 0; 2803 MachineFunction &MF = DAG.getMachineFunction(); 2804 if (FoldedLoad) { 2805 EVT VT = *RC->vt_begin(); 2806 std::pair<MachineInstr::mmo_iterator, 2807 MachineInstr::mmo_iterator> MMOs = 2808 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 2809 cast<MachineSDNode>(N)->memoperands_end()); 2810 bool isAligned = (*MMOs.first)->getAlignment() >= 16; 2811 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, 2812 VT, MVT::Other, &AddrOps[0], AddrOps.size()); 2813 NewNodes.push_back(Load); 2814 2815 // Preserve memory reference information. 2816 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 2817 } 2818 2819 // Emit the data processing instruction. 2820 std::vector<EVT> VTs; 2821 const TargetRegisterClass *DstRC = 0; 2822 if (TID.getNumDefs() > 0) { 2823 DstRC = TID.OpInfo[0].getRegClass(&RI); 2824 VTs.push_back(*DstRC->vt_begin()); 2825 } 2826 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 2827 EVT VT = N->getValueType(i); 2828 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) 2829 VTs.push_back(VT); 2830 } 2831 if (Load) 2832 BeforeOps.push_back(SDValue(Load, 0)); 2833 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 2834 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0], 2835 BeforeOps.size()); 2836 NewNodes.push_back(NewNode); 2837 2838 // Emit the store instruction. 2839 if (FoldedStore) { 2840 AddrOps.pop_back(); 2841 AddrOps.push_back(SDValue(NewNode, 0)); 2842 AddrOps.push_back(Chain); 2843 std::pair<MachineInstr::mmo_iterator, 2844 MachineInstr::mmo_iterator> MMOs = 2845 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 2846 cast<MachineSDNode>(N)->memoperands_end()); 2847 bool isAligned = (*MMOs.first)->getAlignment() >= 16; 2848 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, 2849 isAligned, TM), 2850 dl, MVT::Other, 2851 &AddrOps[0], AddrOps.size()); 2852 NewNodes.push_back(Store); 2853 2854 // Preserve memory reference information. 2855 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 2856 } 2857 2858 return true; 2859} 2860 2861unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 2862 bool UnfoldLoad, bool UnfoldStore, 2863 unsigned *LoadRegIndex) const { 2864 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2865 MemOp2RegOpTable.find((unsigned*)Opc); 2866 if (I == MemOp2RegOpTable.end()) 2867 return 0; 2868 bool FoldedLoad = I->second.second & (1 << 4); 2869 bool FoldedStore = I->second.second & (1 << 5); 2870 if (UnfoldLoad && !FoldedLoad) 2871 return 0; 2872 if (UnfoldStore && !FoldedStore) 2873 return 0; 2874 if (LoadRegIndex) 2875 *LoadRegIndex = I->second.second & 0xf; 2876 return I->second.first; 2877} 2878 2879bool 2880X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 2881 int64_t &Offset1, int64_t &Offset2) const { 2882 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 2883 return false; 2884 unsigned Opc1 = Load1->getMachineOpcode(); 2885 unsigned Opc2 = Load2->getMachineOpcode(); 2886 switch (Opc1) { 2887 default: return false; 2888 case X86::MOV8rm: 2889 case X86::MOV16rm: 2890 case X86::MOV32rm: 2891 case X86::MOV64rm: 2892 case X86::LD_Fp32m: 2893 case X86::LD_Fp64m: 2894 case X86::LD_Fp80m: 2895 case X86::MOVSSrm: 2896 case X86::MOVSDrm: 2897 case X86::MMX_MOVD64rm: 2898 case X86::MMX_MOVQ64rm: 2899 case X86::FsMOVAPSrm: 2900 case X86::FsMOVAPDrm: 2901 case X86::MOVAPSrm: 2902 case X86::MOVUPSrm: 2903 case X86::MOVUPSrm_Int: 2904 case X86::MOVAPDrm: 2905 case X86::MOVDQArm: 2906 case X86::MOVDQUrm: 2907 case X86::MOVDQUrm_Int: 2908 break; 2909 } 2910 switch (Opc2) { 2911 default: return false; 2912 case X86::MOV8rm: 2913 case X86::MOV16rm: 2914 case X86::MOV32rm: 2915 case X86::MOV64rm: 2916 case X86::LD_Fp32m: 2917 case X86::LD_Fp64m: 2918 case X86::LD_Fp80m: 2919 case X86::MOVSSrm: 2920 case X86::MOVSDrm: 2921 case X86::MMX_MOVD64rm: 2922 case X86::MMX_MOVQ64rm: 2923 case X86::FsMOVAPSrm: 2924 case X86::FsMOVAPDrm: 2925 case X86::MOVAPSrm: 2926 case X86::MOVUPSrm: 2927 case X86::MOVUPSrm_Int: 2928 case X86::MOVAPDrm: 2929 case X86::MOVDQArm: 2930 case X86::MOVDQUrm: 2931 case X86::MOVDQUrm_Int: 2932 break; 2933 } 2934 2935 // Check if chain operands and base addresses match. 2936 if (Load1->getOperand(0) != Load2->getOperand(0) || 2937 Load1->getOperand(5) != Load2->getOperand(5)) 2938 return false; 2939 // Segment operands should match as well. 2940 if (Load1->getOperand(4) != Load2->getOperand(4)) 2941 return false; 2942 // Scale should be 1, Index should be Reg0. 2943 if (Load1->getOperand(1) == Load2->getOperand(1) && 2944 Load1->getOperand(2) == Load2->getOperand(2)) { 2945 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 2946 return false; 2947 SDValue Op2 = Load1->getOperand(2); 2948 if (!isa<RegisterSDNode>(Op2) || 2949 cast<RegisterSDNode>(Op2)->getReg() != 0) 2950 return 0; 2951 2952 // Now let's examine the displacements. 2953 if (isa<ConstantSDNode>(Load1->getOperand(3)) && 2954 isa<ConstantSDNode>(Load2->getOperand(3))) { 2955 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 2956 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 2957 return true; 2958 } 2959 } 2960 return false; 2961} 2962 2963bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 2964 int64_t Offset1, int64_t Offset2, 2965 unsigned NumLoads) const { 2966 assert(Offset2 > Offset1); 2967 if ((Offset2 - Offset1) / 8 > 64) 2968 return false; 2969 2970 unsigned Opc1 = Load1->getMachineOpcode(); 2971 unsigned Opc2 = Load2->getMachineOpcode(); 2972 if (Opc1 != Opc2) 2973 return false; // FIXME: overly conservative? 2974 2975 switch (Opc1) { 2976 default: break; 2977 case X86::LD_Fp32m: 2978 case X86::LD_Fp64m: 2979 case X86::LD_Fp80m: 2980 case X86::MMX_MOVD64rm: 2981 case X86::MMX_MOVQ64rm: 2982 return false; 2983 } 2984 2985 EVT VT = Load1->getValueType(0); 2986 switch (VT.getSimpleVT().SimpleTy) { 2987 default: { 2988 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 2989 // have 16 of them to play with. 2990 if (TM.getSubtargetImpl()->is64Bit()) { 2991 if (NumLoads >= 3) 2992 return false; 2993 } else if (NumLoads) 2994 return false; 2995 break; 2996 } 2997 case MVT::i8: 2998 case MVT::i16: 2999 case MVT::i32: 3000 case MVT::i64: 3001 case MVT::f32: 3002 case MVT::f64: 3003 if (NumLoads) 3004 return false; 3005 } 3006 3007 return true; 3008} 3009 3010 3011bool X86InstrInfo:: 3012ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 3013 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 3014 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 3015 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 3016 return true; 3017 Cond[0].setImm(GetOppositeBranchCondition(CC)); 3018 return false; 3019} 3020 3021bool X86InstrInfo:: 3022isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 3023 // FIXME: Return false for x87 stack register classes for now. We can't 3024 // allow any loads of these registers before FpGet_ST0_80. 3025 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 3026 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 3027} 3028 3029 3030/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) 3031/// register? e.g. r8, xmm8, xmm13, etc. 3032bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) { 3033 switch (RegNo) { 3034 default: break; 3035 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 3036 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 3037 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 3038 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 3039 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 3040 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 3041 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 3042 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 3043 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 3044 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 3045 return true; 3046 } 3047 return false; 3048} 3049 3050 3051/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64 3052/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 3053/// size, and 3) use of X86-64 extended registers. 3054unsigned X86InstrInfo::determineREX(const MachineInstr &MI) { 3055 unsigned REX = 0; 3056 const TargetInstrDesc &Desc = MI.getDesc(); 3057 3058 // Pseudo instructions do not need REX prefix byte. 3059 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) 3060 return 0; 3061 if (Desc.TSFlags & X86II::REX_W) 3062 REX |= 1 << 3; 3063 3064 unsigned NumOps = Desc.getNumOperands(); 3065 if (NumOps) { 3066 bool isTwoAddr = NumOps > 1 && 3067 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1; 3068 3069 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 3070 unsigned i = isTwoAddr ? 1 : 0; 3071 for (unsigned e = NumOps; i != e; ++i) { 3072 const MachineOperand& MO = MI.getOperand(i); 3073 if (MO.isReg()) { 3074 unsigned Reg = MO.getReg(); 3075 if (isX86_64NonExtLowByteReg(Reg)) 3076 REX |= 0x40; 3077 } 3078 } 3079 3080 switch (Desc.TSFlags & X86II::FormMask) { 3081 case X86II::MRMInitReg: 3082 if (isX86_64ExtendedReg(MI.getOperand(0))) 3083 REX |= (1 << 0) | (1 << 2); 3084 break; 3085 case X86II::MRMSrcReg: { 3086 if (isX86_64ExtendedReg(MI.getOperand(0))) 3087 REX |= 1 << 2; 3088 i = isTwoAddr ? 2 : 1; 3089 for (unsigned e = NumOps; i != e; ++i) { 3090 const MachineOperand& MO = MI.getOperand(i); 3091 if (isX86_64ExtendedReg(MO)) 3092 REX |= 1 << 0; 3093 } 3094 break; 3095 } 3096 case X86II::MRMSrcMem: { 3097 if (isX86_64ExtendedReg(MI.getOperand(0))) 3098 REX |= 1 << 2; 3099 unsigned Bit = 0; 3100 i = isTwoAddr ? 2 : 1; 3101 for (; i != NumOps; ++i) { 3102 const MachineOperand& MO = MI.getOperand(i); 3103 if (MO.isReg()) { 3104 if (isX86_64ExtendedReg(MO)) 3105 REX |= 1 << Bit; 3106 Bit++; 3107 } 3108 } 3109 break; 3110 } 3111 case X86II::MRM0m: case X86II::MRM1m: 3112 case X86II::MRM2m: case X86II::MRM3m: 3113 case X86II::MRM4m: case X86II::MRM5m: 3114 case X86II::MRM6m: case X86II::MRM7m: 3115 case X86II::MRMDestMem: { 3116 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands); 3117 i = isTwoAddr ? 1 : 0; 3118 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e))) 3119 REX |= 1 << 2; 3120 unsigned Bit = 0; 3121 for (; i != e; ++i) { 3122 const MachineOperand& MO = MI.getOperand(i); 3123 if (MO.isReg()) { 3124 if (isX86_64ExtendedReg(MO)) 3125 REX |= 1 << Bit; 3126 Bit++; 3127 } 3128 } 3129 break; 3130 } 3131 default: { 3132 if (isX86_64ExtendedReg(MI.getOperand(0))) 3133 REX |= 1 << 0; 3134 i = isTwoAddr ? 2 : 1; 3135 for (unsigned e = NumOps; i != e; ++i) { 3136 const MachineOperand& MO = MI.getOperand(i); 3137 if (isX86_64ExtendedReg(MO)) 3138 REX |= 1 << 2; 3139 } 3140 break; 3141 } 3142 } 3143 } 3144 return REX; 3145} 3146 3147/// sizePCRelativeBlockAddress - This method returns the size of a PC 3148/// relative block address instruction 3149/// 3150static unsigned sizePCRelativeBlockAddress() { 3151 return 4; 3152} 3153 3154/// sizeGlobalAddress - Give the size of the emission of this global address 3155/// 3156static unsigned sizeGlobalAddress(bool dword) { 3157 return dword ? 8 : 4; 3158} 3159 3160/// sizeConstPoolAddress - Give the size of the emission of this constant 3161/// pool address 3162/// 3163static unsigned sizeConstPoolAddress(bool dword) { 3164 return dword ? 8 : 4; 3165} 3166 3167/// sizeExternalSymbolAddress - Give the size of the emission of this external 3168/// symbol 3169/// 3170static unsigned sizeExternalSymbolAddress(bool dword) { 3171 return dword ? 8 : 4; 3172} 3173 3174/// sizeJumpTableAddress - Give the size of the emission of this jump 3175/// table address 3176/// 3177static unsigned sizeJumpTableAddress(bool dword) { 3178 return dword ? 8 : 4; 3179} 3180 3181static unsigned sizeConstant(unsigned Size) { 3182 return Size; 3183} 3184 3185static unsigned sizeRegModRMByte(){ 3186 return 1; 3187} 3188 3189static unsigned sizeSIBByte(){ 3190 return 1; 3191} 3192 3193static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) { 3194 unsigned FinalSize = 0; 3195 // If this is a simple integer displacement that doesn't require a relocation. 3196 if (!RelocOp) { 3197 FinalSize += sizeConstant(4); 3198 return FinalSize; 3199 } 3200 3201 // Otherwise, this is something that requires a relocation. 3202 if (RelocOp->isGlobal()) { 3203 FinalSize += sizeGlobalAddress(false); 3204 } else if (RelocOp->isCPI()) { 3205 FinalSize += sizeConstPoolAddress(false); 3206 } else if (RelocOp->isJTI()) { 3207 FinalSize += sizeJumpTableAddress(false); 3208 } else { 3209 llvm_unreachable("Unknown value to relocate!"); 3210 } 3211 return FinalSize; 3212} 3213 3214static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op, 3215 bool IsPIC, bool Is64BitMode) { 3216 const MachineOperand &Op3 = MI.getOperand(Op+3); 3217 int DispVal = 0; 3218 const MachineOperand *DispForReloc = 0; 3219 unsigned FinalSize = 0; 3220 3221 // Figure out what sort of displacement we have to handle here. 3222 if (Op3.isGlobal()) { 3223 DispForReloc = &Op3; 3224 } else if (Op3.isCPI()) { 3225 if (Is64BitMode || IsPIC) { 3226 DispForReloc = &Op3; 3227 } else { 3228 DispVal = 1; 3229 } 3230 } else if (Op3.isJTI()) { 3231 if (Is64BitMode || IsPIC) { 3232 DispForReloc = &Op3; 3233 } else { 3234 DispVal = 1; 3235 } 3236 } else { 3237 DispVal = 1; 3238 } 3239 3240 const MachineOperand &Base = MI.getOperand(Op); 3241 const MachineOperand &IndexReg = MI.getOperand(Op+2); 3242 3243 unsigned BaseReg = Base.getReg(); 3244 3245 // Is a SIB byte needed? 3246 if ((!Is64BitMode || DispForReloc || BaseReg != 0) && 3247 IndexReg.getReg() == 0 && 3248 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) { 3249 if (BaseReg == 0) { // Just a displacement? 3250 // Emit special case [disp32] encoding 3251 ++FinalSize; 3252 FinalSize += getDisplacementFieldSize(DispForReloc); 3253 } else { 3254 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg); 3255 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { 3256 // Emit simple indirect register encoding... [EAX] f.e. 3257 ++FinalSize; 3258 // Be pessimistic and assume it's a disp32, not a disp8 3259 } else { 3260 // Emit the most general non-SIB encoding: [REG+disp32] 3261 ++FinalSize; 3262 FinalSize += getDisplacementFieldSize(DispForReloc); 3263 } 3264 } 3265 3266 } else { // We need a SIB byte, so start by outputting the ModR/M byte first 3267 assert(IndexReg.getReg() != X86::ESP && 3268 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 3269 3270 bool ForceDisp32 = false; 3271 if (BaseReg == 0 || DispForReloc) { 3272 // Emit the normal disp32 encoding. 3273 ++FinalSize; 3274 ForceDisp32 = true; 3275 } else { 3276 ++FinalSize; 3277 } 3278 3279 FinalSize += sizeSIBByte(); 3280 3281 // Do we need to output a displacement? 3282 if (DispVal != 0 || ForceDisp32) { 3283 FinalSize += getDisplacementFieldSize(DispForReloc); 3284 } 3285 } 3286 return FinalSize; 3287} 3288 3289 3290static unsigned GetInstSizeWithDesc(const MachineInstr &MI, 3291 const TargetInstrDesc *Desc, 3292 bool IsPIC, bool Is64BitMode) { 3293 3294 unsigned Opcode = Desc->Opcode; 3295 unsigned FinalSize = 0; 3296 3297 // Emit the lock opcode prefix as needed. 3298 if (Desc->TSFlags & X86II::LOCK) ++FinalSize; 3299 3300 // Emit segment override opcode prefix as needed. 3301 switch (Desc->TSFlags & X86II::SegOvrMask) { 3302 case X86II::FS: 3303 case X86II::GS: 3304 ++FinalSize; 3305 break; 3306 default: llvm_unreachable("Invalid segment!"); 3307 case 0: break; // No segment override! 3308 } 3309 3310 // Emit the repeat opcode prefix as needed. 3311 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize; 3312 3313 // Emit the operand size opcode prefix as needed. 3314 if (Desc->TSFlags & X86II::OpSize) ++FinalSize; 3315 3316 // Emit the address size opcode prefix as needed. 3317 if (Desc->TSFlags & X86II::AdSize) ++FinalSize; 3318 3319 bool Need0FPrefix = false; 3320 switch (Desc->TSFlags & X86II::Op0Mask) { 3321 case X86II::TB: // Two-byte opcode prefix 3322 case X86II::T8: // 0F 38 3323 case X86II::TA: // 0F 3A 3324 Need0FPrefix = true; 3325 break; 3326 case X86II::TF: // F2 0F 38 3327 ++FinalSize; 3328 Need0FPrefix = true; 3329 break; 3330 case X86II::REP: break; // already handled. 3331 case X86II::XS: // F3 0F 3332 ++FinalSize; 3333 Need0FPrefix = true; 3334 break; 3335 case X86II::XD: // F2 0F 3336 ++FinalSize; 3337 Need0FPrefix = true; 3338 break; 3339 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: 3340 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: 3341 ++FinalSize; 3342 break; // Two-byte opcode prefix 3343 default: llvm_unreachable("Invalid prefix!"); 3344 case 0: break; // No prefix! 3345 } 3346 3347 if (Is64BitMode) { 3348 // REX prefix 3349 unsigned REX = X86InstrInfo::determineREX(MI); 3350 if (REX) 3351 ++FinalSize; 3352 } 3353 3354 // 0x0F escape code must be emitted just before the opcode. 3355 if (Need0FPrefix) 3356 ++FinalSize; 3357 3358 switch (Desc->TSFlags & X86II::Op0Mask) { 3359 case X86II::T8: // 0F 38 3360 ++FinalSize; 3361 break; 3362 case X86II::TA: // 0F 3A 3363 ++FinalSize; 3364 break; 3365 case X86II::TF: // F2 0F 38 3366 ++FinalSize; 3367 break; 3368 } 3369 3370 // If this is a two-address instruction, skip one of the register operands. 3371 unsigned NumOps = Desc->getNumOperands(); 3372 unsigned CurOp = 0; 3373 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1) 3374 CurOp++; 3375 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0) 3376 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 3377 --NumOps; 3378 3379 switch (Desc->TSFlags & X86II::FormMask) { 3380 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!"); 3381 case X86II::Pseudo: 3382 // Remember the current PC offset, this is the PIC relocation 3383 // base address. 3384 switch (Opcode) { 3385 default: 3386 break; 3387 case TargetOpcode::INLINEASM: { 3388 const MachineFunction *MF = MI.getParent()->getParent(); 3389 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 3390 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(), 3391 *MF->getTarget().getMCAsmInfo()); 3392 break; 3393 } 3394 case TargetOpcode::DBG_LABEL: 3395 case TargetOpcode::EH_LABEL: 3396 break; 3397 case TargetOpcode::IMPLICIT_DEF: 3398 case TargetOpcode::KILL: 3399 case X86::FP_REG_KILL: 3400 break; 3401 case X86::MOVPC32r: { 3402 // This emits the "call" portion of this pseudo instruction. 3403 ++FinalSize; 3404 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3405 break; 3406 } 3407 } 3408 CurOp = NumOps; 3409 break; 3410 case X86II::RawFrm: 3411 ++FinalSize; 3412 3413 if (CurOp != NumOps) { 3414 const MachineOperand &MO = MI.getOperand(CurOp++); 3415 if (MO.isMBB()) { 3416 FinalSize += sizePCRelativeBlockAddress(); 3417 } else if (MO.isGlobal()) { 3418 FinalSize += sizeGlobalAddress(false); 3419 } else if (MO.isSymbol()) { 3420 FinalSize += sizeExternalSymbolAddress(false); 3421 } else if (MO.isImm()) { 3422 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3423 } else { 3424 llvm_unreachable("Unknown RawFrm operand!"); 3425 } 3426 } 3427 break; 3428 3429 case X86II::AddRegFrm: 3430 ++FinalSize; 3431 ++CurOp; 3432 3433 if (CurOp != NumOps) { 3434 const MachineOperand &MO1 = MI.getOperand(CurOp++); 3435 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 3436 if (MO1.isImm()) 3437 FinalSize += sizeConstant(Size); 3438 else { 3439 bool dword = false; 3440 if (Opcode == X86::MOV64ri) 3441 dword = true; 3442 if (MO1.isGlobal()) { 3443 FinalSize += sizeGlobalAddress(dword); 3444 } else if (MO1.isSymbol()) 3445 FinalSize += sizeExternalSymbolAddress(dword); 3446 else if (MO1.isCPI()) 3447 FinalSize += sizeConstPoolAddress(dword); 3448 else if (MO1.isJTI()) 3449 FinalSize += sizeJumpTableAddress(dword); 3450 } 3451 } 3452 break; 3453 3454 case X86II::MRMDestReg: { 3455 ++FinalSize; 3456 FinalSize += sizeRegModRMByte(); 3457 CurOp += 2; 3458 if (CurOp != NumOps) { 3459 ++CurOp; 3460 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3461 } 3462 break; 3463 } 3464 case X86II::MRMDestMem: { 3465 ++FinalSize; 3466 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 3467 CurOp += X86AddrNumOperands + 1; 3468 if (CurOp != NumOps) { 3469 ++CurOp; 3470 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3471 } 3472 break; 3473 } 3474 3475 case X86II::MRMSrcReg: 3476 ++FinalSize; 3477 FinalSize += sizeRegModRMByte(); 3478 CurOp += 2; 3479 if (CurOp != NumOps) { 3480 ++CurOp; 3481 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3482 } 3483 break; 3484 3485 case X86II::MRMSrcMem: { 3486 int AddrOperands; 3487 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || 3488 Opcode == X86::LEA16r || Opcode == X86::LEA32r) 3489 AddrOperands = X86AddrNumOperands - 1; // No segment register 3490 else 3491 AddrOperands = X86AddrNumOperands; 3492 3493 ++FinalSize; 3494 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode); 3495 CurOp += AddrOperands + 1; 3496 if (CurOp != NumOps) { 3497 ++CurOp; 3498 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3499 } 3500 break; 3501 } 3502 3503 case X86II::MRM0r: case X86II::MRM1r: 3504 case X86II::MRM2r: case X86II::MRM3r: 3505 case X86II::MRM4r: case X86II::MRM5r: 3506 case X86II::MRM6r: case X86II::MRM7r: 3507 ++FinalSize; 3508 if (Desc->getOpcode() == X86::LFENCE || 3509 Desc->getOpcode() == X86::MFENCE) { 3510 // Special handling of lfence and mfence; 3511 FinalSize += sizeRegModRMByte(); 3512 } else if (Desc->getOpcode() == X86::MONITOR || 3513 Desc->getOpcode() == X86::MWAIT) { 3514 // Special handling of monitor and mwait. 3515 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode. 3516 } else { 3517 ++CurOp; 3518 FinalSize += sizeRegModRMByte(); 3519 } 3520 3521 if (CurOp != NumOps) { 3522 const MachineOperand &MO1 = MI.getOperand(CurOp++); 3523 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 3524 if (MO1.isImm()) 3525 FinalSize += sizeConstant(Size); 3526 else { 3527 bool dword = false; 3528 if (Opcode == X86::MOV64ri32) 3529 dword = true; 3530 if (MO1.isGlobal()) { 3531 FinalSize += sizeGlobalAddress(dword); 3532 } else if (MO1.isSymbol()) 3533 FinalSize += sizeExternalSymbolAddress(dword); 3534 else if (MO1.isCPI()) 3535 FinalSize += sizeConstPoolAddress(dword); 3536 else if (MO1.isJTI()) 3537 FinalSize += sizeJumpTableAddress(dword); 3538 } 3539 } 3540 break; 3541 3542 case X86II::MRM0m: case X86II::MRM1m: 3543 case X86II::MRM2m: case X86II::MRM3m: 3544 case X86II::MRM4m: case X86II::MRM5m: 3545 case X86II::MRM6m: case X86II::MRM7m: { 3546 3547 ++FinalSize; 3548 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 3549 CurOp += X86AddrNumOperands; 3550 3551 if (CurOp != NumOps) { 3552 const MachineOperand &MO = MI.getOperand(CurOp++); 3553 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 3554 if (MO.isImm()) 3555 FinalSize += sizeConstant(Size); 3556 else { 3557 bool dword = false; 3558 if (Opcode == X86::MOV64mi32) 3559 dword = true; 3560 if (MO.isGlobal()) { 3561 FinalSize += sizeGlobalAddress(dword); 3562 } else if (MO.isSymbol()) 3563 FinalSize += sizeExternalSymbolAddress(dword); 3564 else if (MO.isCPI()) 3565 FinalSize += sizeConstPoolAddress(dword); 3566 else if (MO.isJTI()) 3567 FinalSize += sizeJumpTableAddress(dword); 3568 } 3569 } 3570 break; 3571 3572 case X86II::MRM_C1: 3573 case X86II::MRM_C8: 3574 case X86II::MRM_C9: 3575 case X86II::MRM_E8: 3576 case X86II::MRM_F0: 3577 FinalSize += 2; 3578 break; 3579 } 3580 3581 case X86II::MRMInitReg: 3582 ++FinalSize; 3583 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg). 3584 FinalSize += sizeRegModRMByte(); 3585 ++CurOp; 3586 break; 3587 } 3588 3589 if (!Desc->isVariadic() && CurOp != NumOps) { 3590 std::string msg; 3591 raw_string_ostream Msg(msg); 3592 Msg << "Cannot determine size: " << MI; 3593 llvm_report_error(Msg.str()); 3594 } 3595 3596 3597 return FinalSize; 3598} 3599 3600 3601unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 3602 const TargetInstrDesc &Desc = MI->getDesc(); 3603 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_; 3604 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit(); 3605 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode); 3606 if (Desc.getOpcode() == X86::MOVPC32r) 3607 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode); 3608 return Size; 3609} 3610 3611/// getGlobalBaseReg - Return a virtual register initialized with the 3612/// the global base register value. Output instructions required to 3613/// initialize the register in the function entry block, if necessary. 3614/// 3615unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 3616 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 3617 "X86-64 PIC uses RIP relative addressing"); 3618 3619 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 3620 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 3621 if (GlobalBaseReg != 0) 3622 return GlobalBaseReg; 3623 3624 // Insert the set of GlobalBaseReg into the first MBB of the function 3625 MachineBasicBlock &FirstMBB = MF->front(); 3626 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 3627 DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 3628 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 3629 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3630 3631 const TargetInstrInfo *TII = TM.getInstrInfo(); 3632 // Operand of MovePCtoStack is completely ignored by asm printer. It's 3633 // only used in JIT code emission as displacement to pc. 3634 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 3635 3636 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 3637 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 3638 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) { 3639 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3640 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 3641 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 3642 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 3643 X86II::MO_GOT_ABSOLUTE_ADDRESS); 3644 } else { 3645 GlobalBaseReg = PC; 3646 } 3647 3648 X86FI->setGlobalBaseReg(GlobalBaseReg); 3649 return GlobalBaseReg; 3650} 3651