X86InstrInfo.cpp revision 202878
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86InstrInfo.h" 15#include "X86.h" 16#include "X86GenInstrInfo.inc" 17#include "X86InstrBuilder.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86Subtarget.h" 20#include "X86TargetMachine.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/ADT/STLExtras.h" 24#include "llvm/CodeGen/MachineConstantPool.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/LiveVariables.h" 29#include "llvm/CodeGen/PseudoSourceValue.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/MC/MCAsmInfo.h" 36 37#include <limits> 38 39using namespace llvm; 40 41static cl::opt<bool> 42NoFusing("disable-spill-fusing", 43 cl::desc("Disable fusing of spill code into instructions")); 44static cl::opt<bool> 45PrintFailedFusing("print-failed-fuse-candidates", 46 cl::desc("Print instructions that the allocator wants to" 47 " fuse, but the X86 backend currently can't"), 48 cl::Hidden); 49static cl::opt<bool> 50ReMatPICStubLoad("remat-pic-stub-load", 51 cl::desc("Re-materialize load from stub in PIC mode"), 52 cl::init(false), cl::Hidden); 53 54X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 55 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)), 56 TM(tm), RI(tm, *this) { 57 SmallVector<unsigned,16> AmbEntries; 58 static const unsigned OpTbl2Addr[][2] = { 59 { X86::ADC32ri, X86::ADC32mi }, 60 { X86::ADC32ri8, X86::ADC32mi8 }, 61 { X86::ADC32rr, X86::ADC32mr }, 62 { X86::ADC64ri32, X86::ADC64mi32 }, 63 { X86::ADC64ri8, X86::ADC64mi8 }, 64 { X86::ADC64rr, X86::ADC64mr }, 65 { X86::ADD16ri, X86::ADD16mi }, 66 { X86::ADD16ri8, X86::ADD16mi8 }, 67 { X86::ADD16rr, X86::ADD16mr }, 68 { X86::ADD32ri, X86::ADD32mi }, 69 { X86::ADD32ri8, X86::ADD32mi8 }, 70 { X86::ADD32rr, X86::ADD32mr }, 71 { X86::ADD64ri32, X86::ADD64mi32 }, 72 { X86::ADD64ri8, X86::ADD64mi8 }, 73 { X86::ADD64rr, X86::ADD64mr }, 74 { X86::ADD8ri, X86::ADD8mi }, 75 { X86::ADD8rr, X86::ADD8mr }, 76 { X86::AND16ri, X86::AND16mi }, 77 { X86::AND16ri8, X86::AND16mi8 }, 78 { X86::AND16rr, X86::AND16mr }, 79 { X86::AND32ri, X86::AND32mi }, 80 { X86::AND32ri8, X86::AND32mi8 }, 81 { X86::AND32rr, X86::AND32mr }, 82 { X86::AND64ri32, X86::AND64mi32 }, 83 { X86::AND64ri8, X86::AND64mi8 }, 84 { X86::AND64rr, X86::AND64mr }, 85 { X86::AND8ri, X86::AND8mi }, 86 { X86::AND8rr, X86::AND8mr }, 87 { X86::DEC16r, X86::DEC16m }, 88 { X86::DEC32r, X86::DEC32m }, 89 { X86::DEC64_16r, X86::DEC64_16m }, 90 { X86::DEC64_32r, X86::DEC64_32m }, 91 { X86::DEC64r, X86::DEC64m }, 92 { X86::DEC8r, X86::DEC8m }, 93 { X86::INC16r, X86::INC16m }, 94 { X86::INC32r, X86::INC32m }, 95 { X86::INC64_16r, X86::INC64_16m }, 96 { X86::INC64_32r, X86::INC64_32m }, 97 { X86::INC64r, X86::INC64m }, 98 { X86::INC8r, X86::INC8m }, 99 { X86::NEG16r, X86::NEG16m }, 100 { X86::NEG32r, X86::NEG32m }, 101 { X86::NEG64r, X86::NEG64m }, 102 { X86::NEG8r, X86::NEG8m }, 103 { X86::NOT16r, X86::NOT16m }, 104 { X86::NOT32r, X86::NOT32m }, 105 { X86::NOT64r, X86::NOT64m }, 106 { X86::NOT8r, X86::NOT8m }, 107 { X86::OR16ri, X86::OR16mi }, 108 { X86::OR16ri8, X86::OR16mi8 }, 109 { X86::OR16rr, X86::OR16mr }, 110 { X86::OR32ri, X86::OR32mi }, 111 { X86::OR32ri8, X86::OR32mi8 }, 112 { X86::OR32rr, X86::OR32mr }, 113 { X86::OR64ri32, X86::OR64mi32 }, 114 { X86::OR64ri8, X86::OR64mi8 }, 115 { X86::OR64rr, X86::OR64mr }, 116 { X86::OR8ri, X86::OR8mi }, 117 { X86::OR8rr, X86::OR8mr }, 118 { X86::ROL16r1, X86::ROL16m1 }, 119 { X86::ROL16rCL, X86::ROL16mCL }, 120 { X86::ROL16ri, X86::ROL16mi }, 121 { X86::ROL32r1, X86::ROL32m1 }, 122 { X86::ROL32rCL, X86::ROL32mCL }, 123 { X86::ROL32ri, X86::ROL32mi }, 124 { X86::ROL64r1, X86::ROL64m1 }, 125 { X86::ROL64rCL, X86::ROL64mCL }, 126 { X86::ROL64ri, X86::ROL64mi }, 127 { X86::ROL8r1, X86::ROL8m1 }, 128 { X86::ROL8rCL, X86::ROL8mCL }, 129 { X86::ROL8ri, X86::ROL8mi }, 130 { X86::ROR16r1, X86::ROR16m1 }, 131 { X86::ROR16rCL, X86::ROR16mCL }, 132 { X86::ROR16ri, X86::ROR16mi }, 133 { X86::ROR32r1, X86::ROR32m1 }, 134 { X86::ROR32rCL, X86::ROR32mCL }, 135 { X86::ROR32ri, X86::ROR32mi }, 136 { X86::ROR64r1, X86::ROR64m1 }, 137 { X86::ROR64rCL, X86::ROR64mCL }, 138 { X86::ROR64ri, X86::ROR64mi }, 139 { X86::ROR8r1, X86::ROR8m1 }, 140 { X86::ROR8rCL, X86::ROR8mCL }, 141 { X86::ROR8ri, X86::ROR8mi }, 142 { X86::SAR16r1, X86::SAR16m1 }, 143 { X86::SAR16rCL, X86::SAR16mCL }, 144 { X86::SAR16ri, X86::SAR16mi }, 145 { X86::SAR32r1, X86::SAR32m1 }, 146 { X86::SAR32rCL, X86::SAR32mCL }, 147 { X86::SAR32ri, X86::SAR32mi }, 148 { X86::SAR64r1, X86::SAR64m1 }, 149 { X86::SAR64rCL, X86::SAR64mCL }, 150 { X86::SAR64ri, X86::SAR64mi }, 151 { X86::SAR8r1, X86::SAR8m1 }, 152 { X86::SAR8rCL, X86::SAR8mCL }, 153 { X86::SAR8ri, X86::SAR8mi }, 154 { X86::SBB32ri, X86::SBB32mi }, 155 { X86::SBB32ri8, X86::SBB32mi8 }, 156 { X86::SBB32rr, X86::SBB32mr }, 157 { X86::SBB64ri32, X86::SBB64mi32 }, 158 { X86::SBB64ri8, X86::SBB64mi8 }, 159 { X86::SBB64rr, X86::SBB64mr }, 160 { X86::SHL16rCL, X86::SHL16mCL }, 161 { X86::SHL16ri, X86::SHL16mi }, 162 { X86::SHL32rCL, X86::SHL32mCL }, 163 { X86::SHL32ri, X86::SHL32mi }, 164 { X86::SHL64rCL, X86::SHL64mCL }, 165 { X86::SHL64ri, X86::SHL64mi }, 166 { X86::SHL8rCL, X86::SHL8mCL }, 167 { X86::SHL8ri, X86::SHL8mi }, 168 { X86::SHLD16rrCL, X86::SHLD16mrCL }, 169 { X86::SHLD16rri8, X86::SHLD16mri8 }, 170 { X86::SHLD32rrCL, X86::SHLD32mrCL }, 171 { X86::SHLD32rri8, X86::SHLD32mri8 }, 172 { X86::SHLD64rrCL, X86::SHLD64mrCL }, 173 { X86::SHLD64rri8, X86::SHLD64mri8 }, 174 { X86::SHR16r1, X86::SHR16m1 }, 175 { X86::SHR16rCL, X86::SHR16mCL }, 176 { X86::SHR16ri, X86::SHR16mi }, 177 { X86::SHR32r1, X86::SHR32m1 }, 178 { X86::SHR32rCL, X86::SHR32mCL }, 179 { X86::SHR32ri, X86::SHR32mi }, 180 { X86::SHR64r1, X86::SHR64m1 }, 181 { X86::SHR64rCL, X86::SHR64mCL }, 182 { X86::SHR64ri, X86::SHR64mi }, 183 { X86::SHR8r1, X86::SHR8m1 }, 184 { X86::SHR8rCL, X86::SHR8mCL }, 185 { X86::SHR8ri, X86::SHR8mi }, 186 { X86::SHRD16rrCL, X86::SHRD16mrCL }, 187 { X86::SHRD16rri8, X86::SHRD16mri8 }, 188 { X86::SHRD32rrCL, X86::SHRD32mrCL }, 189 { X86::SHRD32rri8, X86::SHRD32mri8 }, 190 { X86::SHRD64rrCL, X86::SHRD64mrCL }, 191 { X86::SHRD64rri8, X86::SHRD64mri8 }, 192 { X86::SUB16ri, X86::SUB16mi }, 193 { X86::SUB16ri8, X86::SUB16mi8 }, 194 { X86::SUB16rr, X86::SUB16mr }, 195 { X86::SUB32ri, X86::SUB32mi }, 196 { X86::SUB32ri8, X86::SUB32mi8 }, 197 { X86::SUB32rr, X86::SUB32mr }, 198 { X86::SUB64ri32, X86::SUB64mi32 }, 199 { X86::SUB64ri8, X86::SUB64mi8 }, 200 { X86::SUB64rr, X86::SUB64mr }, 201 { X86::SUB8ri, X86::SUB8mi }, 202 { X86::SUB8rr, X86::SUB8mr }, 203 { X86::XOR16ri, X86::XOR16mi }, 204 { X86::XOR16ri8, X86::XOR16mi8 }, 205 { X86::XOR16rr, X86::XOR16mr }, 206 { X86::XOR32ri, X86::XOR32mi }, 207 { X86::XOR32ri8, X86::XOR32mi8 }, 208 { X86::XOR32rr, X86::XOR32mr }, 209 { X86::XOR64ri32, X86::XOR64mi32 }, 210 { X86::XOR64ri8, X86::XOR64mi8 }, 211 { X86::XOR64rr, X86::XOR64mr }, 212 { X86::XOR8ri, X86::XOR8mi }, 213 { X86::XOR8rr, X86::XOR8mr } 214 }; 215 216 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 217 unsigned RegOp = OpTbl2Addr[i][0]; 218 unsigned MemOp = OpTbl2Addr[i][1]; 219 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, 220 std::make_pair(MemOp,0))).second) 221 assert(false && "Duplicated entries?"); 222 // Index 0, folded load and store, no alignment requirement. 223 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); 224 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 225 std::make_pair(RegOp, 226 AuxInfo))).second) 227 AmbEntries.push_back(MemOp); 228 } 229 230 // If the third value is 1, then it's folding either a load or a store. 231 static const unsigned OpTbl0[][4] = { 232 { X86::BT16ri8, X86::BT16mi8, 1, 0 }, 233 { X86::BT32ri8, X86::BT32mi8, 1, 0 }, 234 { X86::BT64ri8, X86::BT64mi8, 1, 0 }, 235 { X86::CALL32r, X86::CALL32m, 1, 0 }, 236 { X86::CALL64r, X86::CALL64m, 1, 0 }, 237 { X86::CMP16ri, X86::CMP16mi, 1, 0 }, 238 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 }, 239 { X86::CMP16rr, X86::CMP16mr, 1, 0 }, 240 { X86::CMP32ri, X86::CMP32mi, 1, 0 }, 241 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 }, 242 { X86::CMP32rr, X86::CMP32mr, 1, 0 }, 243 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 }, 244 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 }, 245 { X86::CMP64rr, X86::CMP64mr, 1, 0 }, 246 { X86::CMP8ri, X86::CMP8mi, 1, 0 }, 247 { X86::CMP8rr, X86::CMP8mr, 1, 0 }, 248 { X86::DIV16r, X86::DIV16m, 1, 0 }, 249 { X86::DIV32r, X86::DIV32m, 1, 0 }, 250 { X86::DIV64r, X86::DIV64m, 1, 0 }, 251 { X86::DIV8r, X86::DIV8m, 1, 0 }, 252 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 }, 253 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 }, 254 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 }, 255 { X86::IDIV16r, X86::IDIV16m, 1, 0 }, 256 { X86::IDIV32r, X86::IDIV32m, 1, 0 }, 257 { X86::IDIV64r, X86::IDIV64m, 1, 0 }, 258 { X86::IDIV8r, X86::IDIV8m, 1, 0 }, 259 { X86::IMUL16r, X86::IMUL16m, 1, 0 }, 260 { X86::IMUL32r, X86::IMUL32m, 1, 0 }, 261 { X86::IMUL64r, X86::IMUL64m, 1, 0 }, 262 { X86::IMUL8r, X86::IMUL8m, 1, 0 }, 263 { X86::JMP32r, X86::JMP32m, 1, 0 }, 264 { X86::JMP64r, X86::JMP64m, 1, 0 }, 265 { X86::MOV16ri, X86::MOV16mi, 0, 0 }, 266 { X86::MOV16rr, X86::MOV16mr, 0, 0 }, 267 { X86::MOV32ri, X86::MOV32mi, 0, 0 }, 268 { X86::MOV32rr, X86::MOV32mr, 0, 0 }, 269 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 }, 270 { X86::MOV64rr, X86::MOV64mr, 0, 0 }, 271 { X86::MOV8ri, X86::MOV8mi, 0, 0 }, 272 { X86::MOV8rr, X86::MOV8mr, 0, 0 }, 273 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 }, 274 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 }, 275 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 }, 276 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 }, 277 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 }, 278 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 }, 279 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0, 0 }, 280 { X86::MOVSDrr, X86::MOVSDmr, 0, 0 }, 281 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 }, 282 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 }, 283 { X86::MOVSSrr, X86::MOVSSmr, 0, 0 }, 284 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 }, 285 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 }, 286 { X86::MUL16r, X86::MUL16m, 1, 0 }, 287 { X86::MUL32r, X86::MUL32m, 1, 0 }, 288 { X86::MUL64r, X86::MUL64m, 1, 0 }, 289 { X86::MUL8r, X86::MUL8m, 1, 0 }, 290 { X86::SETAEr, X86::SETAEm, 0, 0 }, 291 { X86::SETAr, X86::SETAm, 0, 0 }, 292 { X86::SETBEr, X86::SETBEm, 0, 0 }, 293 { X86::SETBr, X86::SETBm, 0, 0 }, 294 { X86::SETEr, X86::SETEm, 0, 0 }, 295 { X86::SETGEr, X86::SETGEm, 0, 0 }, 296 { X86::SETGr, X86::SETGm, 0, 0 }, 297 { X86::SETLEr, X86::SETLEm, 0, 0 }, 298 { X86::SETLr, X86::SETLm, 0, 0 }, 299 { X86::SETNEr, X86::SETNEm, 0, 0 }, 300 { X86::SETNOr, X86::SETNOm, 0, 0 }, 301 { X86::SETNPr, X86::SETNPm, 0, 0 }, 302 { X86::SETNSr, X86::SETNSm, 0, 0 }, 303 { X86::SETOr, X86::SETOm, 0, 0 }, 304 { X86::SETPr, X86::SETPm, 0, 0 }, 305 { X86::SETSr, X86::SETSm, 0, 0 }, 306 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 }, 307 { X86::TEST16ri, X86::TEST16mi, 1, 0 }, 308 { X86::TEST32ri, X86::TEST32mi, 1, 0 }, 309 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 }, 310 { X86::TEST8ri, X86::TEST8mi, 1, 0 } 311 }; 312 313 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 314 unsigned RegOp = OpTbl0[i][0]; 315 unsigned MemOp = OpTbl0[i][1]; 316 unsigned Align = OpTbl0[i][3]; 317 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, 318 std::make_pair(MemOp,Align))).second) 319 assert(false && "Duplicated entries?"); 320 unsigned FoldedLoad = OpTbl0[i][2]; 321 // Index 0, folded load or store. 322 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); 323 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 324 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 325 std::make_pair(RegOp, AuxInfo))).second) 326 AmbEntries.push_back(MemOp); 327 } 328 329 static const unsigned OpTbl1[][3] = { 330 { X86::CMP16rr, X86::CMP16rm, 0 }, 331 { X86::CMP32rr, X86::CMP32rm, 0 }, 332 { X86::CMP64rr, X86::CMP64rm, 0 }, 333 { X86::CMP8rr, X86::CMP8rm, 0 }, 334 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 335 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 336 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 337 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 338 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 339 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 340 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 341 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 342 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 343 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 344 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 }, 345 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 }, 346 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 347 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 348 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 349 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 350 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 351 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 352 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 353 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 354 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 355 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 356 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 }, 357 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 }, 358 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 }, 359 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 }, 360 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 }, 361 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 }, 362 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 }, 363 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 }, 364 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 365 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 366 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 367 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 368 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 369 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 370 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 }, 371 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 }, 372 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 }, 373 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 }, 374 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 375 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 376 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 377 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 378 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 379 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 380 { X86::MOV16rr, X86::MOV16rm, 0 }, 381 { X86::MOV32rr, X86::MOV32rm, 0 }, 382 { X86::MOV64rr, X86::MOV64rm, 0 }, 383 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 384 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 385 { X86::MOV8rr, X86::MOV8rm, 0 }, 386 { X86::MOVAPDrr, X86::MOVAPDrm, 16 }, 387 { X86::MOVAPSrr, X86::MOVAPSrm, 16 }, 388 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 389 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 390 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 391 { X86::MOVDQArr, X86::MOVDQArm, 16 }, 392 { X86::MOVSD2PDrr, X86::MOVSD2PDrm, 0 }, 393 { X86::MOVSDrr, X86::MOVSDrm, 0 }, 394 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 }, 395 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 }, 396 { X86::MOVSS2PSrr, X86::MOVSS2PSrm, 0 }, 397 { X86::MOVSSrr, X86::MOVSSrm, 0 }, 398 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 399 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 400 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 401 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 402 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 403 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 404 { X86::MOVUPDrr, X86::MOVUPDrm, 16 }, 405 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 406 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 }, 407 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 408 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 }, 409 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 410 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 411 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 412 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 413 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 }, 414 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 }, 415 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 }, 416 { X86::PSHUFDri, X86::PSHUFDmi, 16 }, 417 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 }, 418 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 }, 419 { X86::RCPPSr, X86::RCPPSm, 16 }, 420 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 }, 421 { X86::RSQRTPSr, X86::RSQRTPSm, 16 }, 422 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 }, 423 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 424 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 425 { X86::SQRTPDr, X86::SQRTPDm, 16 }, 426 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 }, 427 { X86::SQRTPSr, X86::SQRTPSm, 16 }, 428 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 }, 429 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 430 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 431 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 432 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 433 { X86::TEST16rr, X86::TEST16rm, 0 }, 434 { X86::TEST32rr, X86::TEST32rm, 0 }, 435 { X86::TEST64rr, X86::TEST64rm, 0 }, 436 { X86::TEST8rr, X86::TEST8rm, 0 }, 437 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 438 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 439 { X86::UCOMISSrr, X86::UCOMISSrm, 0 } 440 }; 441 442 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 443 unsigned RegOp = OpTbl1[i][0]; 444 unsigned MemOp = OpTbl1[i][1]; 445 unsigned Align = OpTbl1[i][2]; 446 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, 447 std::make_pair(MemOp,Align))).second) 448 assert(false && "Duplicated entries?"); 449 // Index 1, folded load 450 unsigned AuxInfo = 1 | (1 << 4); 451 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 452 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 453 std::make_pair(RegOp, AuxInfo))).second) 454 AmbEntries.push_back(MemOp); 455 } 456 457 static const unsigned OpTbl2[][3] = { 458 { X86::ADC32rr, X86::ADC32rm, 0 }, 459 { X86::ADC64rr, X86::ADC64rm, 0 }, 460 { X86::ADD16rr, X86::ADD16rm, 0 }, 461 { X86::ADD32rr, X86::ADD32rm, 0 }, 462 { X86::ADD64rr, X86::ADD64rm, 0 }, 463 { X86::ADD8rr, X86::ADD8rm, 0 }, 464 { X86::ADDPDrr, X86::ADDPDrm, 16 }, 465 { X86::ADDPSrr, X86::ADDPSrm, 16 }, 466 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 467 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 468 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 }, 469 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 }, 470 { X86::AND16rr, X86::AND16rm, 0 }, 471 { X86::AND32rr, X86::AND32rm, 0 }, 472 { X86::AND64rr, X86::AND64rm, 0 }, 473 { X86::AND8rr, X86::AND8rm, 0 }, 474 { X86::ANDNPDrr, X86::ANDNPDrm, 16 }, 475 { X86::ANDNPSrr, X86::ANDNPSrm, 16 }, 476 { X86::ANDPDrr, X86::ANDPDrm, 16 }, 477 { X86::ANDPSrr, X86::ANDPSrm, 16 }, 478 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 479 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 480 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 481 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 482 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 483 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 484 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 485 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 486 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 487 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 488 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 489 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 490 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 491 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 492 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 493 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 494 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 495 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 496 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 497 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 498 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 499 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 500 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 501 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 502 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 503 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 504 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 505 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 506 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 507 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 508 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 509 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 510 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 511 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 512 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 513 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 514 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 515 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 516 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 517 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 518 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 519 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 520 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 521 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 522 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 523 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 524 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 525 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 526 { X86::CMPPDrri, X86::CMPPDrmi, 16 }, 527 { X86::CMPPSrri, X86::CMPPSrmi, 16 }, 528 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 529 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 530 { X86::DIVPDrr, X86::DIVPDrm, 16 }, 531 { X86::DIVPSrr, X86::DIVPSrm, 16 }, 532 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 533 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 534 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 }, 535 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 }, 536 { X86::FsANDPDrr, X86::FsANDPDrm, 16 }, 537 { X86::FsANDPSrr, X86::FsANDPSrm, 16 }, 538 { X86::FsORPDrr, X86::FsORPDrm, 16 }, 539 { X86::FsORPSrr, X86::FsORPSrm, 16 }, 540 { X86::FsXORPDrr, X86::FsXORPDrm, 16 }, 541 { X86::FsXORPSrr, X86::FsXORPSrm, 16 }, 542 { X86::HADDPDrr, X86::HADDPDrm, 16 }, 543 { X86::HADDPSrr, X86::HADDPSrm, 16 }, 544 { X86::HSUBPDrr, X86::HSUBPDrm, 16 }, 545 { X86::HSUBPSrr, X86::HSUBPSrm, 16 }, 546 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 547 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 548 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 549 { X86::MAXPDrr, X86::MAXPDrm, 16 }, 550 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 }, 551 { X86::MAXPSrr, X86::MAXPSrm, 16 }, 552 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 }, 553 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 554 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 }, 555 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 556 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 }, 557 { X86::MINPDrr, X86::MINPDrm, 16 }, 558 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 }, 559 { X86::MINPSrr, X86::MINPSrm, 16 }, 560 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 }, 561 { X86::MINSDrr, X86::MINSDrm, 0 }, 562 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 }, 563 { X86::MINSSrr, X86::MINSSrm, 0 }, 564 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 }, 565 { X86::MULPDrr, X86::MULPDrm, 16 }, 566 { X86::MULPSrr, X86::MULPSrm, 16 }, 567 { X86::MULSDrr, X86::MULSDrm, 0 }, 568 { X86::MULSSrr, X86::MULSSrm, 0 }, 569 { X86::OR16rr, X86::OR16rm, 0 }, 570 { X86::OR32rr, X86::OR32rm, 0 }, 571 { X86::OR64rr, X86::OR64rm, 0 }, 572 { X86::OR8rr, X86::OR8rm, 0 }, 573 { X86::ORPDrr, X86::ORPDrm, 16 }, 574 { X86::ORPSrr, X86::ORPSrm, 16 }, 575 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 }, 576 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 }, 577 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 }, 578 { X86::PADDBrr, X86::PADDBrm, 16 }, 579 { X86::PADDDrr, X86::PADDDrm, 16 }, 580 { X86::PADDQrr, X86::PADDQrm, 16 }, 581 { X86::PADDSBrr, X86::PADDSBrm, 16 }, 582 { X86::PADDSWrr, X86::PADDSWrm, 16 }, 583 { X86::PADDWrr, X86::PADDWrm, 16 }, 584 { X86::PANDNrr, X86::PANDNrm, 16 }, 585 { X86::PANDrr, X86::PANDrm, 16 }, 586 { X86::PAVGBrr, X86::PAVGBrm, 16 }, 587 { X86::PAVGWrr, X86::PAVGWrm, 16 }, 588 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 }, 589 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 }, 590 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 }, 591 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 }, 592 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 }, 593 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 }, 594 { X86::PINSRWrri, X86::PINSRWrmi, 16 }, 595 { X86::PMADDWDrr, X86::PMADDWDrm, 16 }, 596 { X86::PMAXSWrr, X86::PMAXSWrm, 16 }, 597 { X86::PMAXUBrr, X86::PMAXUBrm, 16 }, 598 { X86::PMINSWrr, X86::PMINSWrm, 16 }, 599 { X86::PMINUBrr, X86::PMINUBrm, 16 }, 600 { X86::PMULDQrr, X86::PMULDQrm, 16 }, 601 { X86::PMULHUWrr, X86::PMULHUWrm, 16 }, 602 { X86::PMULHWrr, X86::PMULHWrm, 16 }, 603 { X86::PMULLDrr, X86::PMULLDrm, 16 }, 604 { X86::PMULLDrr_int, X86::PMULLDrm_int, 16 }, 605 { X86::PMULLWrr, X86::PMULLWrm, 16 }, 606 { X86::PMULUDQrr, X86::PMULUDQrm, 16 }, 607 { X86::PORrr, X86::PORrm, 16 }, 608 { X86::PSADBWrr, X86::PSADBWrm, 16 }, 609 { X86::PSLLDrr, X86::PSLLDrm, 16 }, 610 { X86::PSLLQrr, X86::PSLLQrm, 16 }, 611 { X86::PSLLWrr, X86::PSLLWrm, 16 }, 612 { X86::PSRADrr, X86::PSRADrm, 16 }, 613 { X86::PSRAWrr, X86::PSRAWrm, 16 }, 614 { X86::PSRLDrr, X86::PSRLDrm, 16 }, 615 { X86::PSRLQrr, X86::PSRLQrm, 16 }, 616 { X86::PSRLWrr, X86::PSRLWrm, 16 }, 617 { X86::PSUBBrr, X86::PSUBBrm, 16 }, 618 { X86::PSUBDrr, X86::PSUBDrm, 16 }, 619 { X86::PSUBSBrr, X86::PSUBSBrm, 16 }, 620 { X86::PSUBSWrr, X86::PSUBSWrm, 16 }, 621 { X86::PSUBWrr, X86::PSUBWrm, 16 }, 622 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 }, 623 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 }, 624 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 }, 625 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 }, 626 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 }, 627 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 }, 628 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 }, 629 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 }, 630 { X86::PXORrr, X86::PXORrm, 16 }, 631 { X86::SBB32rr, X86::SBB32rm, 0 }, 632 { X86::SBB64rr, X86::SBB64rm, 0 }, 633 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 }, 634 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 }, 635 { X86::SUB16rr, X86::SUB16rm, 0 }, 636 { X86::SUB32rr, X86::SUB32rm, 0 }, 637 { X86::SUB64rr, X86::SUB64rm, 0 }, 638 { X86::SUB8rr, X86::SUB8rm, 0 }, 639 { X86::SUBPDrr, X86::SUBPDrm, 16 }, 640 { X86::SUBPSrr, X86::SUBPSrm, 16 }, 641 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 642 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 643 // FIXME: TEST*rr -> swapped operand of TEST*mr. 644 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 }, 645 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 }, 646 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 }, 647 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 }, 648 { X86::XOR16rr, X86::XOR16rm, 0 }, 649 { X86::XOR32rr, X86::XOR32rm, 0 }, 650 { X86::XOR64rr, X86::XOR64rm, 0 }, 651 { X86::XOR8rr, X86::XOR8rm, 0 }, 652 { X86::XORPDrr, X86::XORPDrm, 16 }, 653 { X86::XORPSrr, X86::XORPSrm, 16 } 654 }; 655 656 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 657 unsigned RegOp = OpTbl2[i][0]; 658 unsigned MemOp = OpTbl2[i][1]; 659 unsigned Align = OpTbl2[i][2]; 660 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, 661 std::make_pair(MemOp,Align))).second) 662 assert(false && "Duplicated entries?"); 663 // Index 2, folded load 664 unsigned AuxInfo = 2 | (1 << 4); 665 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 666 std::make_pair(RegOp, AuxInfo))).second) 667 AmbEntries.push_back(MemOp); 668 } 669 670 // Remove ambiguous entries. 671 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?"); 672} 673 674bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, 675 unsigned &SrcReg, unsigned &DstReg, 676 unsigned &SrcSubIdx, unsigned &DstSubIdx) const { 677 switch (MI.getOpcode()) { 678 default: 679 return false; 680 case X86::MOV8rr: 681 case X86::MOV8rr_NOREX: 682 case X86::MOV16rr: 683 case X86::MOV32rr: 684 case X86::MOV64rr: 685 case X86::MOVSSrr: 686 case X86::MOVSDrr: 687 688 // FP Stack register class copies 689 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080: 690 case X86::MOV_Fp3264: case X86::MOV_Fp3280: 691 case X86::MOV_Fp6432: case X86::MOV_Fp8032: 692 693 case X86::FsMOVAPSrr: 694 case X86::FsMOVAPDrr: 695 case X86::MOVAPSrr: 696 case X86::MOVAPDrr: 697 case X86::MOVDQArr: 698 case X86::MOVSS2PSrr: 699 case X86::MOVSD2PDrr: 700 case X86::MOVPS2SSrr: 701 case X86::MOVPD2SDrr: 702 case X86::MMX_MOVQ64rr: 703 assert(MI.getNumOperands() >= 2 && 704 MI.getOperand(0).isReg() && 705 MI.getOperand(1).isReg() && 706 "invalid register-register move instruction"); 707 SrcReg = MI.getOperand(1).getReg(); 708 DstReg = MI.getOperand(0).getReg(); 709 SrcSubIdx = MI.getOperand(1).getSubReg(); 710 DstSubIdx = MI.getOperand(0).getSubReg(); 711 return true; 712 } 713} 714 715bool 716X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 717 unsigned &SrcReg, unsigned &DstReg, 718 unsigned &SubIdx) const { 719 switch (MI.getOpcode()) { 720 default: break; 721 case X86::MOVSX16rr8: 722 case X86::MOVZX16rr8: 723 case X86::MOVSX32rr8: 724 case X86::MOVZX32rr8: 725 case X86::MOVSX64rr8: 726 case X86::MOVZX64rr8: 727 if (!TM.getSubtarget<X86Subtarget>().is64Bit()) 728 // It's not always legal to reference the low 8-bit of the larger 729 // register in 32-bit mode. 730 return false; 731 case X86::MOVSX32rr16: 732 case X86::MOVZX32rr16: 733 case X86::MOVSX64rr16: 734 case X86::MOVZX64rr16: 735 case X86::MOVSX64rr32: 736 case X86::MOVZX64rr32: { 737 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 738 // Be conservative. 739 return false; 740 SrcReg = MI.getOperand(1).getReg(); 741 DstReg = MI.getOperand(0).getReg(); 742 switch (MI.getOpcode()) { 743 default: 744 llvm_unreachable(0); 745 break; 746 case X86::MOVSX16rr8: 747 case X86::MOVZX16rr8: 748 case X86::MOVSX32rr8: 749 case X86::MOVZX32rr8: 750 case X86::MOVSX64rr8: 751 case X86::MOVZX64rr8: 752 SubIdx = 1; 753 break; 754 case X86::MOVSX32rr16: 755 case X86::MOVZX32rr16: 756 case X86::MOVSX64rr16: 757 case X86::MOVZX64rr16: 758 SubIdx = 3; 759 break; 760 case X86::MOVSX64rr32: 761 case X86::MOVZX64rr32: 762 SubIdx = 4; 763 break; 764 } 765 return true; 766 } 767 } 768 return false; 769} 770 771/// isFrameOperand - Return true and the FrameIndex if the specified 772/// operand and follow operands form a reference to the stack frame. 773bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 774 int &FrameIndex) const { 775 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() && 776 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() && 777 MI->getOperand(Op+1).getImm() == 1 && 778 MI->getOperand(Op+2).getReg() == 0 && 779 MI->getOperand(Op+3).getImm() == 0) { 780 FrameIndex = MI->getOperand(Op).getIndex(); 781 return true; 782 } 783 return false; 784} 785 786static bool isFrameLoadOpcode(int Opcode) { 787 switch (Opcode) { 788 default: break; 789 case X86::MOV8rm: 790 case X86::MOV16rm: 791 case X86::MOV32rm: 792 case X86::MOV64rm: 793 case X86::LD_Fp64m: 794 case X86::MOVSSrm: 795 case X86::MOVSDrm: 796 case X86::MOVAPSrm: 797 case X86::MOVAPDrm: 798 case X86::MOVDQArm: 799 case X86::MMX_MOVD64rm: 800 case X86::MMX_MOVQ64rm: 801 return true; 802 break; 803 } 804 return false; 805} 806 807static bool isFrameStoreOpcode(int Opcode) { 808 switch (Opcode) { 809 default: break; 810 case X86::MOV8mr: 811 case X86::MOV16mr: 812 case X86::MOV32mr: 813 case X86::MOV64mr: 814 case X86::ST_FpP64m: 815 case X86::MOVSSmr: 816 case X86::MOVSDmr: 817 case X86::MOVAPSmr: 818 case X86::MOVAPDmr: 819 case X86::MOVDQAmr: 820 case X86::MMX_MOVD64mr: 821 case X86::MMX_MOVQ64mr: 822 case X86::MMX_MOVNTQmr: 823 return true; 824 } 825 return false; 826} 827 828unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 829 int &FrameIndex) const { 830 if (isFrameLoadOpcode(MI->getOpcode())) 831 if (isFrameOperand(MI, 1, FrameIndex)) 832 return MI->getOperand(0).getReg(); 833 return 0; 834} 835 836unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 837 int &FrameIndex) const { 838 if (isFrameLoadOpcode(MI->getOpcode())) { 839 unsigned Reg; 840 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 841 return Reg; 842 // Check for post-frame index elimination operations 843 const MachineMemOperand *Dummy; 844 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 845 } 846 return 0; 847} 848 849bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, 850 const MachineMemOperand *&MMO, 851 int &FrameIndex) const { 852 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 853 oe = MI->memoperands_end(); 854 o != oe; 855 ++o) { 856 if ((*o)->isLoad() && (*o)->getValue()) 857 if (const FixedStackPseudoSourceValue *Value = 858 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 859 FrameIndex = Value->getFrameIndex(); 860 MMO = *o; 861 return true; 862 } 863 } 864 return false; 865} 866 867unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 868 int &FrameIndex) const { 869 if (isFrameStoreOpcode(MI->getOpcode())) 870 if (isFrameOperand(MI, 0, FrameIndex)) 871 return MI->getOperand(X86AddrNumOperands).getReg(); 872 return 0; 873} 874 875unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 876 int &FrameIndex) const { 877 if (isFrameStoreOpcode(MI->getOpcode())) { 878 unsigned Reg; 879 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 880 return Reg; 881 // Check for post-frame index elimination operations 882 const MachineMemOperand *Dummy; 883 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 884 } 885 return 0; 886} 887 888bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI, 889 const MachineMemOperand *&MMO, 890 int &FrameIndex) const { 891 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 892 oe = MI->memoperands_end(); 893 o != oe; 894 ++o) { 895 if ((*o)->isStore() && (*o)->getValue()) 896 if (const FixedStackPseudoSourceValue *Value = 897 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 898 FrameIndex = Value->getFrameIndex(); 899 MMO = *o; 900 return true; 901 } 902 } 903 return false; 904} 905 906/// regIsPICBase - Return true if register is PIC base (i.e.g defined by 907/// X86::MOVPC32r. 908static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 909 bool isPICBase = false; 910 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 911 E = MRI.def_end(); I != E; ++I) { 912 MachineInstr *DefMI = I.getOperand().getParent(); 913 if (DefMI->getOpcode() != X86::MOVPC32r) 914 return false; 915 assert(!isPICBase && "More than one PIC base?"); 916 isPICBase = true; 917 } 918 return isPICBase; 919} 920 921bool 922X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 923 AliasAnalysis *AA) const { 924 switch (MI->getOpcode()) { 925 default: break; 926 case X86::MOV8rm: 927 case X86::MOV16rm: 928 case X86::MOV32rm: 929 case X86::MOV64rm: 930 case X86::LD_Fp64m: 931 case X86::MOVSSrm: 932 case X86::MOVSDrm: 933 case X86::MOVAPSrm: 934 case X86::MOVUPSrm: 935 case X86::MOVUPSrm_Int: 936 case X86::MOVAPDrm: 937 case X86::MOVDQArm: 938 case X86::MMX_MOVD64rm: 939 case X86::MMX_MOVQ64rm: 940 case X86::FsMOVAPSrm: 941 case X86::FsMOVAPDrm: { 942 // Loads from constant pools are trivially rematerializable. 943 if (MI->getOperand(1).isReg() && 944 MI->getOperand(2).isImm() && 945 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 946 MI->isInvariantLoad(AA)) { 947 unsigned BaseReg = MI->getOperand(1).getReg(); 948 if (BaseReg == 0 || BaseReg == X86::RIP) 949 return true; 950 // Allow re-materialization of PIC load. 951 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 952 return false; 953 const MachineFunction &MF = *MI->getParent()->getParent(); 954 const MachineRegisterInfo &MRI = MF.getRegInfo(); 955 bool isPICBase = false; 956 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 957 E = MRI.def_end(); I != E; ++I) { 958 MachineInstr *DefMI = I.getOperand().getParent(); 959 if (DefMI->getOpcode() != X86::MOVPC32r) 960 return false; 961 assert(!isPICBase && "More than one PIC base?"); 962 isPICBase = true; 963 } 964 return isPICBase; 965 } 966 return false; 967 } 968 969 case X86::LEA32r: 970 case X86::LEA64r: { 971 if (MI->getOperand(2).isImm() && 972 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 973 !MI->getOperand(4).isReg()) { 974 // lea fi#, lea GV, etc. are all rematerializable. 975 if (!MI->getOperand(1).isReg()) 976 return true; 977 unsigned BaseReg = MI->getOperand(1).getReg(); 978 if (BaseReg == 0) 979 return true; 980 // Allow re-materialization of lea PICBase + x. 981 const MachineFunction &MF = *MI->getParent()->getParent(); 982 const MachineRegisterInfo &MRI = MF.getRegInfo(); 983 return regIsPICBase(BaseReg, MRI); 984 } 985 return false; 986 } 987 } 988 989 // All other instructions marked M_REMATERIALIZABLE are always trivially 990 // rematerializable. 991 return true; 992} 993 994/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 995/// would clobber the EFLAGS condition register. Note the result may be 996/// conservative. If it cannot definitely determine the safety after visiting 997/// a few instructions in each direction it assumes it's not safe. 998static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 999 MachineBasicBlock::iterator I) { 1000 // It's always safe to clobber EFLAGS at the end of a block. 1001 if (I == MBB.end()) 1002 return true; 1003 1004 // For compile time consideration, if we are not able to determine the 1005 // safety after visiting 4 instructions in each direction, we will assume 1006 // it's not safe. 1007 MachineBasicBlock::iterator Iter = I; 1008 for (unsigned i = 0; i < 4; ++i) { 1009 bool SeenDef = false; 1010 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1011 MachineOperand &MO = Iter->getOperand(j); 1012 if (!MO.isReg()) 1013 continue; 1014 if (MO.getReg() == X86::EFLAGS) { 1015 if (MO.isUse()) 1016 return false; 1017 SeenDef = true; 1018 } 1019 } 1020 1021 if (SeenDef) 1022 // This instruction defines EFLAGS, no need to look any further. 1023 return true; 1024 ++Iter; 1025 1026 // If we make it to the end of the block, it's safe to clobber EFLAGS. 1027 if (Iter == MBB.end()) 1028 return true; 1029 } 1030 1031 Iter = I; 1032 for (unsigned i = 0; i < 4; ++i) { 1033 // If we make it to the beginning of the block, it's safe to clobber 1034 // EFLAGS iff EFLAGS is not live-in. 1035 if (Iter == MBB.begin()) 1036 return !MBB.isLiveIn(X86::EFLAGS); 1037 1038 --Iter; 1039 bool SawKill = false; 1040 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1041 MachineOperand &MO = Iter->getOperand(j); 1042 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1043 if (MO.isDef()) return MO.isDead(); 1044 if (MO.isKill()) SawKill = true; 1045 } 1046 } 1047 1048 if (SawKill) 1049 // This instruction kills EFLAGS and doesn't redefine it, so 1050 // there's no need to look further. 1051 return true; 1052 } 1053 1054 // Conservative answer. 1055 return false; 1056} 1057 1058void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1059 MachineBasicBlock::iterator I, 1060 unsigned DestReg, unsigned SubIdx, 1061 const MachineInstr *Orig, 1062 const TargetRegisterInfo *TRI) const { 1063 DebugLoc DL = DebugLoc::getUnknownLoc(); 1064 if (I != MBB.end()) DL = I->getDebugLoc(); 1065 1066 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) { 1067 DestReg = TRI->getSubReg(DestReg, SubIdx); 1068 SubIdx = 0; 1069 } 1070 1071 // MOV32r0 etc. are implemented with xor which clobbers condition code. 1072 // Re-materialize them as movri instructions to avoid side effects. 1073 bool Clone = true; 1074 unsigned Opc = Orig->getOpcode(); 1075 switch (Opc) { 1076 default: break; 1077 case X86::MOV8r0: 1078 case X86::MOV16r0: 1079 case X86::MOV32r0: 1080 case X86::MOV64r0: { 1081 if (!isSafeToClobberEFLAGS(MBB, I)) { 1082 switch (Opc) { 1083 default: break; 1084 case X86::MOV8r0: Opc = X86::MOV8ri; break; 1085 case X86::MOV16r0: Opc = X86::MOV16ri; break; 1086 case X86::MOV32r0: Opc = X86::MOV32ri; break; 1087 case X86::MOV64r0: Opc = X86::MOV64ri; break; 1088 } 1089 Clone = false; 1090 } 1091 break; 1092 } 1093 } 1094 1095 if (Clone) { 1096 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1097 MI->getOperand(0).setReg(DestReg); 1098 MBB.insert(I, MI); 1099 } else { 1100 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0); 1101 } 1102 1103 MachineInstr *NewMI = prior(I); 1104 NewMI->getOperand(0).setSubReg(SubIdx); 1105} 1106 1107/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 1108/// is not marked dead. 1109static bool hasLiveCondCodeDef(MachineInstr *MI) { 1110 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1111 MachineOperand &MO = MI->getOperand(i); 1112 if (MO.isReg() && MO.isDef() && 1113 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 1114 return true; 1115 } 1116 } 1117 return false; 1118} 1119 1120/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 1121/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 1122/// to a 32-bit superregister and then truncating back down to a 16-bit 1123/// subregister. 1124MachineInstr * 1125X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 1126 MachineFunction::iterator &MFI, 1127 MachineBasicBlock::iterator &MBBI, 1128 LiveVariables *LV) const { 1129 MachineInstr *MI = MBBI; 1130 unsigned Dest = MI->getOperand(0).getReg(); 1131 unsigned Src = MI->getOperand(1).getReg(); 1132 bool isDead = MI->getOperand(0).isDead(); 1133 bool isKill = MI->getOperand(1).isKill(); 1134 1135 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1136 ? X86::LEA64_32r : X86::LEA32r; 1137 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1138 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1139 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1140 1141 // Build and insert into an implicit UNDEF value. This is OK because 1142 // well be shifting and then extracting the lower 16-bits. 1143 // This has the potential to cause partial register stall. e.g. 1144 // movw (%rbp,%rcx,2), %dx 1145 // leal -65(%rdx), %esi 1146 // But testing has shown this *does* help performance in 64-bit mode (at 1147 // least on modern x86 machines). 1148 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1149 MachineInstr *InsMI = 1150 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg) 1151 .addReg(leaInReg) 1152 .addReg(Src, getKillRegState(isKill)) 1153 .addImm(X86::SUBREG_16BIT); 1154 1155 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 1156 get(Opc), leaOutReg); 1157 switch (MIOpc) { 1158 default: 1159 llvm_unreachable(0); 1160 break; 1161 case X86::SHL16ri: { 1162 unsigned ShAmt = MI->getOperand(2).getImm(); 1163 MIB.addReg(0).addImm(1 << ShAmt) 1164 .addReg(leaInReg, RegState::Kill).addImm(0); 1165 break; 1166 } 1167 case X86::INC16r: 1168 case X86::INC64_16r: 1169 addLeaRegOffset(MIB, leaInReg, true, 1); 1170 break; 1171 case X86::DEC16r: 1172 case X86::DEC64_16r: 1173 addLeaRegOffset(MIB, leaInReg, true, -1); 1174 break; 1175 case X86::ADD16ri: 1176 case X86::ADD16ri8: 1177 addLeaRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1178 break; 1179 case X86::ADD16rr: { 1180 unsigned Src2 = MI->getOperand(2).getReg(); 1181 bool isKill2 = MI->getOperand(2).isKill(); 1182 unsigned leaInReg2 = 0; 1183 MachineInstr *InsMI2 = 0; 1184 if (Src == Src2) { 1185 // ADD16rr %reg1028<kill>, %reg1028 1186 // just a single insert_subreg. 1187 addRegReg(MIB, leaInReg, true, leaInReg, false); 1188 } else { 1189 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1190 // Build and insert into an implicit UNDEF value. This is OK because 1191 // well be shifting and then extracting the lower 16-bits. 1192 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2); 1193 InsMI2 = 1194 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg2) 1195 .addReg(leaInReg2) 1196 .addReg(Src2, getKillRegState(isKill2)) 1197 .addImm(X86::SUBREG_16BIT); 1198 addRegReg(MIB, leaInReg, true, leaInReg2, true); 1199 } 1200 if (LV && isKill2 && InsMI2) 1201 LV->replaceKillInstruction(Src2, MI, InsMI2); 1202 break; 1203 } 1204 } 1205 1206 MachineInstr *NewMI = MIB; 1207 MachineInstr *ExtMI = 1208 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG)) 1209 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1210 .addReg(leaOutReg, RegState::Kill) 1211 .addImm(X86::SUBREG_16BIT); 1212 1213 if (LV) { 1214 // Update live variables 1215 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1216 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1217 if (isKill) 1218 LV->replaceKillInstruction(Src, MI, InsMI); 1219 if (isDead) 1220 LV->replaceKillInstruction(Dest, MI, ExtMI); 1221 } 1222 1223 return ExtMI; 1224} 1225 1226/// convertToThreeAddress - This method must be implemented by targets that 1227/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1228/// may be able to convert a two-address instruction into a true 1229/// three-address instruction on demand. This allows the X86 target (for 1230/// example) to convert ADD and SHL instructions into LEA instructions if they 1231/// would require register copies due to two-addressness. 1232/// 1233/// This method returns a null pointer if the transformation cannot be 1234/// performed, otherwise it returns the new instruction. 1235/// 1236MachineInstr * 1237X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1238 MachineBasicBlock::iterator &MBBI, 1239 LiveVariables *LV) const { 1240 MachineInstr *MI = MBBI; 1241 MachineFunction &MF = *MI->getParent()->getParent(); 1242 // All instructions input are two-addr instructions. Get the known operands. 1243 unsigned Dest = MI->getOperand(0).getReg(); 1244 unsigned Src = MI->getOperand(1).getReg(); 1245 bool isDead = MI->getOperand(0).isDead(); 1246 bool isKill = MI->getOperand(1).isKill(); 1247 1248 MachineInstr *NewMI = NULL; 1249 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1250 // we have better subtarget support, enable the 16-bit LEA generation here. 1251 // 16-bit LEA is also slow on Core2. 1252 bool DisableLEA16 = true; 1253 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1254 1255 unsigned MIOpc = MI->getOpcode(); 1256 switch (MIOpc) { 1257 case X86::SHUFPSrri: { 1258 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1259 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1260 1261 unsigned B = MI->getOperand(1).getReg(); 1262 unsigned C = MI->getOperand(2).getReg(); 1263 if (B != C) return 0; 1264 unsigned A = MI->getOperand(0).getReg(); 1265 unsigned M = MI->getOperand(3).getImm(); 1266 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1267 .addReg(A, RegState::Define | getDeadRegState(isDead)) 1268 .addReg(B, getKillRegState(isKill)).addImm(M); 1269 break; 1270 } 1271 case X86::SHL64ri: { 1272 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1273 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1274 // the flags produced by a shift yet, so this is safe. 1275 unsigned ShAmt = MI->getOperand(2).getImm(); 1276 if (ShAmt == 0 || ShAmt >= 4) return 0; 1277 1278 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1279 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1280 .addReg(0).addImm(1 << ShAmt) 1281 .addReg(Src, getKillRegState(isKill)) 1282 .addImm(0); 1283 break; 1284 } 1285 case X86::SHL32ri: { 1286 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1287 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1288 // the flags produced by a shift yet, so this is safe. 1289 unsigned ShAmt = MI->getOperand(2).getImm(); 1290 if (ShAmt == 0 || ShAmt >= 4) return 0; 1291 1292 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1293 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1294 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1295 .addReg(0).addImm(1 << ShAmt) 1296 .addReg(Src, getKillRegState(isKill)).addImm(0); 1297 break; 1298 } 1299 case X86::SHL16ri: { 1300 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1301 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1302 // the flags produced by a shift yet, so this is safe. 1303 unsigned ShAmt = MI->getOperand(2).getImm(); 1304 if (ShAmt == 0 || ShAmt >= 4) return 0; 1305 1306 if (DisableLEA16) 1307 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1308 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1309 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1310 .addReg(0).addImm(1 << ShAmt) 1311 .addReg(Src, getKillRegState(isKill)) 1312 .addImm(0); 1313 break; 1314 } 1315 default: { 1316 // The following opcodes also sets the condition code register(s). Only 1317 // convert them to equivalent lea if the condition code register def's 1318 // are dead! 1319 if (hasLiveCondCodeDef(MI)) 1320 return 0; 1321 1322 switch (MIOpc) { 1323 default: return 0; 1324 case X86::INC64r: 1325 case X86::INC32r: 1326 case X86::INC64_32r: { 1327 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1328 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 1329 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1330 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1331 .addReg(Dest, RegState::Define | 1332 getDeadRegState(isDead)), 1333 Src, isKill, 1); 1334 break; 1335 } 1336 case X86::INC16r: 1337 case X86::INC64_16r: 1338 if (DisableLEA16) 1339 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1340 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1341 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1342 .addReg(Dest, RegState::Define | 1343 getDeadRegState(isDead)), 1344 Src, isKill, 1); 1345 break; 1346 case X86::DEC64r: 1347 case X86::DEC32r: 1348 case X86::DEC64_32r: { 1349 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1350 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 1351 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1352 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1353 .addReg(Dest, RegState::Define | 1354 getDeadRegState(isDead)), 1355 Src, isKill, -1); 1356 break; 1357 } 1358 case X86::DEC16r: 1359 case X86::DEC64_16r: 1360 if (DisableLEA16) 1361 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1362 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1363 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1364 .addReg(Dest, RegState::Define | 1365 getDeadRegState(isDead)), 1366 Src, isKill, -1); 1367 break; 1368 case X86::ADD64rr: 1369 case X86::ADD32rr: { 1370 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1371 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r 1372 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1373 unsigned Src2 = MI->getOperand(2).getReg(); 1374 bool isKill2 = MI->getOperand(2).isKill(); 1375 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1376 .addReg(Dest, RegState::Define | 1377 getDeadRegState(isDead)), 1378 Src, isKill, Src2, isKill2); 1379 if (LV && isKill2) 1380 LV->replaceKillInstruction(Src2, MI, NewMI); 1381 break; 1382 } 1383 case X86::ADD16rr: { 1384 if (DisableLEA16) 1385 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1386 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1387 unsigned Src2 = MI->getOperand(2).getReg(); 1388 bool isKill2 = MI->getOperand(2).isKill(); 1389 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1390 .addReg(Dest, RegState::Define | 1391 getDeadRegState(isDead)), 1392 Src, isKill, Src2, isKill2); 1393 if (LV && isKill2) 1394 LV->replaceKillInstruction(Src2, MI, NewMI); 1395 break; 1396 } 1397 case X86::ADD64ri32: 1398 case X86::ADD64ri8: 1399 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1400 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1401 .addReg(Dest, RegState::Define | 1402 getDeadRegState(isDead)), 1403 Src, isKill, MI->getOperand(2).getImm()); 1404 break; 1405 case X86::ADD32ri: 1406 case X86::ADD32ri8: { 1407 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1408 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1409 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1410 .addReg(Dest, RegState::Define | 1411 getDeadRegState(isDead)), 1412 Src, isKill, MI->getOperand(2).getImm()); 1413 break; 1414 } 1415 case X86::ADD16ri: 1416 case X86::ADD16ri8: 1417 if (DisableLEA16) 1418 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1419 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1420 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1421 .addReg(Dest, RegState::Define | 1422 getDeadRegState(isDead)), 1423 Src, isKill, MI->getOperand(2).getImm()); 1424 break; 1425 } 1426 } 1427 } 1428 1429 if (!NewMI) return 0; 1430 1431 if (LV) { // Update live variables 1432 if (isKill) 1433 LV->replaceKillInstruction(Src, MI, NewMI); 1434 if (isDead) 1435 LV->replaceKillInstruction(Dest, MI, NewMI); 1436 } 1437 1438 MFI->insert(MBBI, NewMI); // Insert the new inst 1439 return NewMI; 1440} 1441 1442/// commuteInstruction - We have a few instructions that must be hacked on to 1443/// commute them. 1444/// 1445MachineInstr * 1446X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1447 switch (MI->getOpcode()) { 1448 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 1449 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 1450 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 1451 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 1452 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 1453 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 1454 unsigned Opc; 1455 unsigned Size; 1456 switch (MI->getOpcode()) { 1457 default: llvm_unreachable("Unreachable!"); 1458 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 1459 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 1460 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 1461 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 1462 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 1463 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 1464 } 1465 unsigned Amt = MI->getOperand(3).getImm(); 1466 if (NewMI) { 1467 MachineFunction &MF = *MI->getParent()->getParent(); 1468 MI = MF.CloneMachineInstr(MI); 1469 NewMI = false; 1470 } 1471 MI->setDesc(get(Opc)); 1472 MI->getOperand(3).setImm(Size-Amt); 1473 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1474 } 1475 case X86::CMOVB16rr: 1476 case X86::CMOVB32rr: 1477 case X86::CMOVB64rr: 1478 case X86::CMOVAE16rr: 1479 case X86::CMOVAE32rr: 1480 case X86::CMOVAE64rr: 1481 case X86::CMOVE16rr: 1482 case X86::CMOVE32rr: 1483 case X86::CMOVE64rr: 1484 case X86::CMOVNE16rr: 1485 case X86::CMOVNE32rr: 1486 case X86::CMOVNE64rr: 1487 case X86::CMOVBE16rr: 1488 case X86::CMOVBE32rr: 1489 case X86::CMOVBE64rr: 1490 case X86::CMOVA16rr: 1491 case X86::CMOVA32rr: 1492 case X86::CMOVA64rr: 1493 case X86::CMOVL16rr: 1494 case X86::CMOVL32rr: 1495 case X86::CMOVL64rr: 1496 case X86::CMOVGE16rr: 1497 case X86::CMOVGE32rr: 1498 case X86::CMOVGE64rr: 1499 case X86::CMOVLE16rr: 1500 case X86::CMOVLE32rr: 1501 case X86::CMOVLE64rr: 1502 case X86::CMOVG16rr: 1503 case X86::CMOVG32rr: 1504 case X86::CMOVG64rr: 1505 case X86::CMOVS16rr: 1506 case X86::CMOVS32rr: 1507 case X86::CMOVS64rr: 1508 case X86::CMOVNS16rr: 1509 case X86::CMOVNS32rr: 1510 case X86::CMOVNS64rr: 1511 case X86::CMOVP16rr: 1512 case X86::CMOVP32rr: 1513 case X86::CMOVP64rr: 1514 case X86::CMOVNP16rr: 1515 case X86::CMOVNP32rr: 1516 case X86::CMOVNP64rr: 1517 case X86::CMOVO16rr: 1518 case X86::CMOVO32rr: 1519 case X86::CMOVO64rr: 1520 case X86::CMOVNO16rr: 1521 case X86::CMOVNO32rr: 1522 case X86::CMOVNO64rr: { 1523 unsigned Opc = 0; 1524 switch (MI->getOpcode()) { 1525 default: break; 1526 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 1527 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 1528 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 1529 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 1530 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 1531 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 1532 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 1533 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 1534 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 1535 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 1536 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 1537 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 1538 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 1539 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 1540 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 1541 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 1542 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 1543 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 1544 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 1545 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 1546 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 1547 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 1548 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 1549 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 1550 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 1551 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 1552 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 1553 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 1554 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 1555 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 1556 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 1557 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 1558 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 1559 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 1560 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 1561 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 1562 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 1563 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 1564 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 1565 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 1566 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 1567 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 1568 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 1569 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 1570 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 1571 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 1572 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 1573 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 1574 } 1575 if (NewMI) { 1576 MachineFunction &MF = *MI->getParent()->getParent(); 1577 MI = MF.CloneMachineInstr(MI); 1578 NewMI = false; 1579 } 1580 MI->setDesc(get(Opc)); 1581 // Fallthrough intended. 1582 } 1583 default: 1584 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1585 } 1586} 1587 1588static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { 1589 switch (BrOpc) { 1590 default: return X86::COND_INVALID; 1591 case X86::JE: return X86::COND_E; 1592 case X86::JNE: return X86::COND_NE; 1593 case X86::JL: return X86::COND_L; 1594 case X86::JLE: return X86::COND_LE; 1595 case X86::JG: return X86::COND_G; 1596 case X86::JGE: return X86::COND_GE; 1597 case X86::JB: return X86::COND_B; 1598 case X86::JBE: return X86::COND_BE; 1599 case X86::JA: return X86::COND_A; 1600 case X86::JAE: return X86::COND_AE; 1601 case X86::JS: return X86::COND_S; 1602 case X86::JNS: return X86::COND_NS; 1603 case X86::JP: return X86::COND_P; 1604 case X86::JNP: return X86::COND_NP; 1605 case X86::JO: return X86::COND_O; 1606 case X86::JNO: return X86::COND_NO; 1607 } 1608} 1609 1610unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 1611 switch (CC) { 1612 default: llvm_unreachable("Illegal condition code!"); 1613 case X86::COND_E: return X86::JE; 1614 case X86::COND_NE: return X86::JNE; 1615 case X86::COND_L: return X86::JL; 1616 case X86::COND_LE: return X86::JLE; 1617 case X86::COND_G: return X86::JG; 1618 case X86::COND_GE: return X86::JGE; 1619 case X86::COND_B: return X86::JB; 1620 case X86::COND_BE: return X86::JBE; 1621 case X86::COND_A: return X86::JA; 1622 case X86::COND_AE: return X86::JAE; 1623 case X86::COND_S: return X86::JS; 1624 case X86::COND_NS: return X86::JNS; 1625 case X86::COND_P: return X86::JP; 1626 case X86::COND_NP: return X86::JNP; 1627 case X86::COND_O: return X86::JO; 1628 case X86::COND_NO: return X86::JNO; 1629 } 1630} 1631 1632/// GetOppositeBranchCondition - Return the inverse of the specified condition, 1633/// e.g. turning COND_E to COND_NE. 1634X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 1635 switch (CC) { 1636 default: llvm_unreachable("Illegal condition code!"); 1637 case X86::COND_E: return X86::COND_NE; 1638 case X86::COND_NE: return X86::COND_E; 1639 case X86::COND_L: return X86::COND_GE; 1640 case X86::COND_LE: return X86::COND_G; 1641 case X86::COND_G: return X86::COND_LE; 1642 case X86::COND_GE: return X86::COND_L; 1643 case X86::COND_B: return X86::COND_AE; 1644 case X86::COND_BE: return X86::COND_A; 1645 case X86::COND_A: return X86::COND_BE; 1646 case X86::COND_AE: return X86::COND_B; 1647 case X86::COND_S: return X86::COND_NS; 1648 case X86::COND_NS: return X86::COND_S; 1649 case X86::COND_P: return X86::COND_NP; 1650 case X86::COND_NP: return X86::COND_P; 1651 case X86::COND_O: return X86::COND_NO; 1652 case X86::COND_NO: return X86::COND_O; 1653 } 1654} 1655 1656bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 1657 const TargetInstrDesc &TID = MI->getDesc(); 1658 if (!TID.isTerminator()) return false; 1659 1660 // Conditional branch is a special case. 1661 if (TID.isBranch() && !TID.isBarrier()) 1662 return true; 1663 if (!TID.isPredicable()) 1664 return true; 1665 return !isPredicated(MI); 1666} 1667 1668// For purposes of branch analysis do not count FP_REG_KILL as a terminator. 1669static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI, 1670 const X86InstrInfo &TII) { 1671 if (MI->getOpcode() == X86::FP_REG_KILL) 1672 return false; 1673 return TII.isUnpredicatedTerminator(MI); 1674} 1675 1676bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 1677 MachineBasicBlock *&TBB, 1678 MachineBasicBlock *&FBB, 1679 SmallVectorImpl<MachineOperand> &Cond, 1680 bool AllowModify) const { 1681 // Start from the bottom of the block and work up, examining the 1682 // terminator instructions. 1683 MachineBasicBlock::iterator I = MBB.end(); 1684 while (I != MBB.begin()) { 1685 --I; 1686 1687 // Working from the bottom, when we see a non-terminator instruction, we're 1688 // done. 1689 if (!isBrAnalysisUnpredicatedTerminator(I, *this)) 1690 break; 1691 1692 // A terminator that isn't a branch can't easily be handled by this 1693 // analysis. 1694 if (!I->getDesc().isBranch()) 1695 return true; 1696 1697 // Handle unconditional branches. 1698 if (I->getOpcode() == X86::JMP) { 1699 if (!AllowModify) { 1700 TBB = I->getOperand(0).getMBB(); 1701 continue; 1702 } 1703 1704 // If the block has any instructions after a JMP, delete them. 1705 while (llvm::next(I) != MBB.end()) 1706 llvm::next(I)->eraseFromParent(); 1707 1708 Cond.clear(); 1709 FBB = 0; 1710 1711 // Delete the JMP if it's equivalent to a fall-through. 1712 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 1713 TBB = 0; 1714 I->eraseFromParent(); 1715 I = MBB.end(); 1716 continue; 1717 } 1718 1719 // TBB is used to indicate the unconditinal destination. 1720 TBB = I->getOperand(0).getMBB(); 1721 continue; 1722 } 1723 1724 // Handle conditional branches. 1725 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode()); 1726 if (BranchCode == X86::COND_INVALID) 1727 return true; // Can't handle indirect branch. 1728 1729 // Working from the bottom, handle the first conditional branch. 1730 if (Cond.empty()) { 1731 FBB = TBB; 1732 TBB = I->getOperand(0).getMBB(); 1733 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 1734 continue; 1735 } 1736 1737 // Handle subsequent conditional branches. Only handle the case where all 1738 // conditional branches branch to the same destination and their condition 1739 // opcodes fit one of the special multi-branch idioms. 1740 assert(Cond.size() == 1); 1741 assert(TBB); 1742 1743 // Only handle the case where all conditional branches branch to the same 1744 // destination. 1745 if (TBB != I->getOperand(0).getMBB()) 1746 return true; 1747 1748 // If the conditions are the same, we can leave them alone. 1749 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 1750 if (OldBranchCode == BranchCode) 1751 continue; 1752 1753 // If they differ, see if they fit one of the known patterns. Theoretically, 1754 // we could handle more patterns here, but we shouldn't expect to see them 1755 // if instruction selection has done a reasonable job. 1756 if ((OldBranchCode == X86::COND_NP && 1757 BranchCode == X86::COND_E) || 1758 (OldBranchCode == X86::COND_E && 1759 BranchCode == X86::COND_NP)) 1760 BranchCode = X86::COND_NP_OR_E; 1761 else if ((OldBranchCode == X86::COND_P && 1762 BranchCode == X86::COND_NE) || 1763 (OldBranchCode == X86::COND_NE && 1764 BranchCode == X86::COND_P)) 1765 BranchCode = X86::COND_NE_OR_P; 1766 else 1767 return true; 1768 1769 // Update the MachineOperand. 1770 Cond[0].setImm(BranchCode); 1771 } 1772 1773 return false; 1774} 1775 1776unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 1777 MachineBasicBlock::iterator I = MBB.end(); 1778 unsigned Count = 0; 1779 1780 while (I != MBB.begin()) { 1781 --I; 1782 if (I->getOpcode() != X86::JMP && 1783 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 1784 break; 1785 // Remove the branch. 1786 I->eraseFromParent(); 1787 I = MBB.end(); 1788 ++Count; 1789 } 1790 1791 return Count; 1792} 1793 1794unsigned 1795X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 1796 MachineBasicBlock *FBB, 1797 const SmallVectorImpl<MachineOperand> &Cond) const { 1798 // FIXME this should probably have a DebugLoc operand 1799 DebugLoc dl = DebugLoc::getUnknownLoc(); 1800 // Shouldn't be a fall through. 1801 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 1802 assert((Cond.size() == 1 || Cond.size() == 0) && 1803 "X86 branch conditions have one component!"); 1804 1805 if (Cond.empty()) { 1806 // Unconditional branch? 1807 assert(!FBB && "Unconditional branch with multiple successors!"); 1808 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB); 1809 return 1; 1810 } 1811 1812 // Conditional branch. 1813 unsigned Count = 0; 1814 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 1815 switch (CC) { 1816 case X86::COND_NP_OR_E: 1817 // Synthesize NP_OR_E with two branches. 1818 BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB); 1819 ++Count; 1820 BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB); 1821 ++Count; 1822 break; 1823 case X86::COND_NE_OR_P: 1824 // Synthesize NE_OR_P with two branches. 1825 BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB); 1826 ++Count; 1827 BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB); 1828 ++Count; 1829 break; 1830 default: { 1831 unsigned Opc = GetCondBranchFromCond(CC); 1832 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB); 1833 ++Count; 1834 } 1835 } 1836 if (FBB) { 1837 // Two-way Conditional branch. Insert the second branch. 1838 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB); 1839 ++Count; 1840 } 1841 return Count; 1842} 1843 1844/// isHReg - Test if the given register is a physical h register. 1845static bool isHReg(unsigned Reg) { 1846 return X86::GR8_ABCD_HRegClass.contains(Reg); 1847} 1848 1849bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, 1850 MachineBasicBlock::iterator MI, 1851 unsigned DestReg, unsigned SrcReg, 1852 const TargetRegisterClass *DestRC, 1853 const TargetRegisterClass *SrcRC) const { 1854 DebugLoc DL = DebugLoc::getUnknownLoc(); 1855 if (MI != MBB.end()) DL = MI->getDebugLoc(); 1856 1857 // Determine if DstRC and SrcRC have a common superclass in common. 1858 const TargetRegisterClass *CommonRC = DestRC; 1859 if (DestRC == SrcRC) 1860 /* Source and destination have the same register class. */; 1861 else if (CommonRC->hasSuperClass(SrcRC)) 1862 CommonRC = SrcRC; 1863 else if (!DestRC->hasSubClass(SrcRC)) { 1864 // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other, 1865 // but we want to copy then as GR64. Similarly, for GR32_NOREX and 1866 // GR32_NOSP, copy as GR32. 1867 if (SrcRC->hasSuperClass(&X86::GR64RegClass) && 1868 DestRC->hasSuperClass(&X86::GR64RegClass)) 1869 CommonRC = &X86::GR64RegClass; 1870 else if (SrcRC->hasSuperClass(&X86::GR32RegClass) && 1871 DestRC->hasSuperClass(&X86::GR32RegClass)) 1872 CommonRC = &X86::GR32RegClass; 1873 else 1874 CommonRC = 0; 1875 } 1876 1877 if (CommonRC) { 1878 unsigned Opc; 1879 if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) { 1880 Opc = X86::MOV64rr; 1881 } else if (CommonRC == &X86::GR32RegClass || 1882 CommonRC == &X86::GR32_NOSPRegClass) { 1883 Opc = X86::MOV32rr; 1884 } else if (CommonRC == &X86::GR16RegClass) { 1885 Opc = X86::MOV16rr; 1886 } else if (CommonRC == &X86::GR8RegClass) { 1887 // Copying to or from a physical H register on x86-64 requires a NOREX 1888 // move. Otherwise use a normal move. 1889 if ((isHReg(DestReg) || isHReg(SrcReg)) && 1890 TM.getSubtarget<X86Subtarget>().is64Bit()) 1891 Opc = X86::MOV8rr_NOREX; 1892 else 1893 Opc = X86::MOV8rr; 1894 } else if (CommonRC == &X86::GR64_ABCDRegClass) { 1895 Opc = X86::MOV64rr; 1896 } else if (CommonRC == &X86::GR32_ABCDRegClass) { 1897 Opc = X86::MOV32rr; 1898 } else if (CommonRC == &X86::GR16_ABCDRegClass) { 1899 Opc = X86::MOV16rr; 1900 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) { 1901 Opc = X86::MOV8rr; 1902 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) { 1903 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 1904 Opc = X86::MOV8rr_NOREX; 1905 else 1906 Opc = X86::MOV8rr; 1907 } else if (CommonRC == &X86::GR64_NOREXRegClass || 1908 CommonRC == &X86::GR64_NOREX_NOSPRegClass) { 1909 Opc = X86::MOV64rr; 1910 } else if (CommonRC == &X86::GR32_NOREXRegClass) { 1911 Opc = X86::MOV32rr; 1912 } else if (CommonRC == &X86::GR16_NOREXRegClass) { 1913 Opc = X86::MOV16rr; 1914 } else if (CommonRC == &X86::GR8_NOREXRegClass) { 1915 Opc = X86::MOV8rr; 1916 } else if (CommonRC == &X86::RFP32RegClass) { 1917 Opc = X86::MOV_Fp3232; 1918 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) { 1919 Opc = X86::MOV_Fp6464; 1920 } else if (CommonRC == &X86::RFP80RegClass) { 1921 Opc = X86::MOV_Fp8080; 1922 } else if (CommonRC == &X86::FR32RegClass) { 1923 Opc = X86::FsMOVAPSrr; 1924 } else if (CommonRC == &X86::FR64RegClass) { 1925 Opc = X86::FsMOVAPDrr; 1926 } else if (CommonRC == &X86::VR128RegClass) { 1927 Opc = X86::MOVAPSrr; 1928 } else if (CommonRC == &X86::VR64RegClass) { 1929 Opc = X86::MMX_MOVQ64rr; 1930 } else { 1931 return false; 1932 } 1933 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg); 1934 return true; 1935 } 1936 1937 // Moving EFLAGS to / from another register requires a push and a pop. 1938 if (SrcRC == &X86::CCRRegClass) { 1939 if (SrcReg != X86::EFLAGS) 1940 return false; 1941 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) { 1942 BuildMI(MBB, MI, DL, get(X86::PUSHFQ64)); 1943 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 1944 return true; 1945 } else if (DestRC == &X86::GR32RegClass || 1946 DestRC == &X86::GR32_NOSPRegClass) { 1947 BuildMI(MBB, MI, DL, get(X86::PUSHFD)); 1948 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 1949 return true; 1950 } 1951 } else if (DestRC == &X86::CCRRegClass) { 1952 if (DestReg != X86::EFLAGS) 1953 return false; 1954 if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) { 1955 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg); 1956 BuildMI(MBB, MI, DL, get(X86::POPFQ)); 1957 return true; 1958 } else if (SrcRC == &X86::GR32RegClass || 1959 DestRC == &X86::GR32_NOSPRegClass) { 1960 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg); 1961 BuildMI(MBB, MI, DL, get(X86::POPFD)); 1962 return true; 1963 } 1964 } 1965 1966 // Moving from ST(0) turns into FpGET_ST0_32 etc. 1967 if (SrcRC == &X86::RSTRegClass) { 1968 // Copying from ST(0)/ST(1). 1969 if (SrcReg != X86::ST0 && SrcReg != X86::ST1) 1970 // Can only copy from ST(0)/ST(1) right now 1971 return false; 1972 bool isST0 = SrcReg == X86::ST0; 1973 unsigned Opc; 1974 if (DestRC == &X86::RFP32RegClass) 1975 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32; 1976 else if (DestRC == &X86::RFP64RegClass) 1977 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64; 1978 else { 1979 if (DestRC != &X86::RFP80RegClass) 1980 return false; 1981 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80; 1982 } 1983 BuildMI(MBB, MI, DL, get(Opc), DestReg); 1984 return true; 1985 } 1986 1987 // Moving to ST(0) turns into FpSET_ST0_32 etc. 1988 if (DestRC == &X86::RSTRegClass) { 1989 // Copying to ST(0) / ST(1). 1990 if (DestReg != X86::ST0 && DestReg != X86::ST1) 1991 // Can only copy to TOS right now 1992 return false; 1993 bool isST0 = DestReg == X86::ST0; 1994 unsigned Opc; 1995 if (SrcRC == &X86::RFP32RegClass) 1996 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32; 1997 else if (SrcRC == &X86::RFP64RegClass) 1998 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64; 1999 else { 2000 if (SrcRC != &X86::RFP80RegClass) 2001 return false; 2002 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80; 2003 } 2004 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg); 2005 return true; 2006 } 2007 2008 // Not yet supported! 2009 return false; 2010} 2011 2012static unsigned getStoreRegOpcode(unsigned SrcReg, 2013 const TargetRegisterClass *RC, 2014 bool isStackAligned, 2015 TargetMachine &TM) { 2016 unsigned Opc = 0; 2017 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) { 2018 Opc = X86::MOV64mr; 2019 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) { 2020 Opc = X86::MOV32mr; 2021 } else if (RC == &X86::GR16RegClass) { 2022 Opc = X86::MOV16mr; 2023 } else if (RC == &X86::GR8RegClass) { 2024 // Copying to or from a physical H register on x86-64 requires a NOREX 2025 // move. Otherwise use a normal move. 2026 if (isHReg(SrcReg) && 2027 TM.getSubtarget<X86Subtarget>().is64Bit()) 2028 Opc = X86::MOV8mr_NOREX; 2029 else 2030 Opc = X86::MOV8mr; 2031 } else if (RC == &X86::GR64_ABCDRegClass) { 2032 Opc = X86::MOV64mr; 2033 } else if (RC == &X86::GR32_ABCDRegClass) { 2034 Opc = X86::MOV32mr; 2035 } else if (RC == &X86::GR16_ABCDRegClass) { 2036 Opc = X86::MOV16mr; 2037 } else if (RC == &X86::GR8_ABCD_LRegClass) { 2038 Opc = X86::MOV8mr; 2039 } else if (RC == &X86::GR8_ABCD_HRegClass) { 2040 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2041 Opc = X86::MOV8mr_NOREX; 2042 else 2043 Opc = X86::MOV8mr; 2044 } else if (RC == &X86::GR64_NOREXRegClass || 2045 RC == &X86::GR64_NOREX_NOSPRegClass) { 2046 Opc = X86::MOV64mr; 2047 } else if (RC == &X86::GR32_NOREXRegClass) { 2048 Opc = X86::MOV32mr; 2049 } else if (RC == &X86::GR16_NOREXRegClass) { 2050 Opc = X86::MOV16mr; 2051 } else if (RC == &X86::GR8_NOREXRegClass) { 2052 Opc = X86::MOV8mr; 2053 } else if (RC == &X86::RFP80RegClass) { 2054 Opc = X86::ST_FpP80m; // pops 2055 } else if (RC == &X86::RFP64RegClass) { 2056 Opc = X86::ST_Fp64m; 2057 } else if (RC == &X86::RFP32RegClass) { 2058 Opc = X86::ST_Fp32m; 2059 } else if (RC == &X86::FR32RegClass) { 2060 Opc = X86::MOVSSmr; 2061 } else if (RC == &X86::FR64RegClass) { 2062 Opc = X86::MOVSDmr; 2063 } else if (RC == &X86::VR128RegClass) { 2064 // If stack is realigned we can use aligned stores. 2065 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr; 2066 } else if (RC == &X86::VR64RegClass) { 2067 Opc = X86::MMX_MOVQ64mr; 2068 } else { 2069 llvm_unreachable("Unknown regclass"); 2070 } 2071 2072 return Opc; 2073} 2074 2075void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 2076 MachineBasicBlock::iterator MI, 2077 unsigned SrcReg, bool isKill, int FrameIdx, 2078 const TargetRegisterClass *RC) const { 2079 const MachineFunction &MF = *MBB.getParent(); 2080 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF); 2081 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2082 DebugLoc DL = DebugLoc::getUnknownLoc(); 2083 if (MI != MBB.end()) DL = MI->getDebugLoc(); 2084 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 2085 .addReg(SrcReg, getKillRegState(isKill)); 2086} 2087 2088void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 2089 bool isKill, 2090 SmallVectorImpl<MachineOperand> &Addr, 2091 const TargetRegisterClass *RC, 2092 MachineInstr::mmo_iterator MMOBegin, 2093 MachineInstr::mmo_iterator MMOEnd, 2094 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2095 bool isAligned = (*MMOBegin)->getAlignment() >= 16; 2096 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2097 DebugLoc DL = DebugLoc::getUnknownLoc(); 2098 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 2099 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2100 MIB.addOperand(Addr[i]); 2101 MIB.addReg(SrcReg, getKillRegState(isKill)); 2102 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2103 NewMIs.push_back(MIB); 2104} 2105 2106static unsigned getLoadRegOpcode(unsigned DestReg, 2107 const TargetRegisterClass *RC, 2108 bool isStackAligned, 2109 const TargetMachine &TM) { 2110 unsigned Opc = 0; 2111 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) { 2112 Opc = X86::MOV64rm; 2113 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) { 2114 Opc = X86::MOV32rm; 2115 } else if (RC == &X86::GR16RegClass) { 2116 Opc = X86::MOV16rm; 2117 } else if (RC == &X86::GR8RegClass) { 2118 // Copying to or from a physical H register on x86-64 requires a NOREX 2119 // move. Otherwise use a normal move. 2120 if (isHReg(DestReg) && 2121 TM.getSubtarget<X86Subtarget>().is64Bit()) 2122 Opc = X86::MOV8rm_NOREX; 2123 else 2124 Opc = X86::MOV8rm; 2125 } else if (RC == &X86::GR64_ABCDRegClass) { 2126 Opc = X86::MOV64rm; 2127 } else if (RC == &X86::GR32_ABCDRegClass) { 2128 Opc = X86::MOV32rm; 2129 } else if (RC == &X86::GR16_ABCDRegClass) { 2130 Opc = X86::MOV16rm; 2131 } else if (RC == &X86::GR8_ABCD_LRegClass) { 2132 Opc = X86::MOV8rm; 2133 } else if (RC == &X86::GR8_ABCD_HRegClass) { 2134 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2135 Opc = X86::MOV8rm_NOREX; 2136 else 2137 Opc = X86::MOV8rm; 2138 } else if (RC == &X86::GR64_NOREXRegClass || 2139 RC == &X86::GR64_NOREX_NOSPRegClass) { 2140 Opc = X86::MOV64rm; 2141 } else if (RC == &X86::GR32_NOREXRegClass) { 2142 Opc = X86::MOV32rm; 2143 } else if (RC == &X86::GR16_NOREXRegClass) { 2144 Opc = X86::MOV16rm; 2145 } else if (RC == &X86::GR8_NOREXRegClass) { 2146 Opc = X86::MOV8rm; 2147 } else if (RC == &X86::RFP80RegClass) { 2148 Opc = X86::LD_Fp80m; 2149 } else if (RC == &X86::RFP64RegClass) { 2150 Opc = X86::LD_Fp64m; 2151 } else if (RC == &X86::RFP32RegClass) { 2152 Opc = X86::LD_Fp32m; 2153 } else if (RC == &X86::FR32RegClass) { 2154 Opc = X86::MOVSSrm; 2155 } else if (RC == &X86::FR64RegClass) { 2156 Opc = X86::MOVSDrm; 2157 } else if (RC == &X86::VR128RegClass) { 2158 // If stack is realigned we can use aligned loads. 2159 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm; 2160 } else if (RC == &X86::VR64RegClass) { 2161 Opc = X86::MMX_MOVQ64rm; 2162 } else { 2163 llvm_unreachable("Unknown regclass"); 2164 } 2165 2166 return Opc; 2167} 2168 2169void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 2170 MachineBasicBlock::iterator MI, 2171 unsigned DestReg, int FrameIdx, 2172 const TargetRegisterClass *RC) const{ 2173 const MachineFunction &MF = *MBB.getParent(); 2174 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF); 2175 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2176 DebugLoc DL = DebugLoc::getUnknownLoc(); 2177 if (MI != MBB.end()) DL = MI->getDebugLoc(); 2178 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 2179} 2180 2181void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 2182 SmallVectorImpl<MachineOperand> &Addr, 2183 const TargetRegisterClass *RC, 2184 MachineInstr::mmo_iterator MMOBegin, 2185 MachineInstr::mmo_iterator MMOEnd, 2186 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2187 bool isAligned = (*MMOBegin)->getAlignment() >= 16; 2188 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2189 DebugLoc DL = DebugLoc::getUnknownLoc(); 2190 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 2191 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2192 MIB.addOperand(Addr[i]); 2193 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2194 NewMIs.push_back(MIB); 2195} 2196 2197bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 2198 MachineBasicBlock::iterator MI, 2199 const std::vector<CalleeSavedInfo> &CSI) const { 2200 if (CSI.empty()) 2201 return false; 2202 2203 DebugLoc DL = MBB.findDebugLoc(MI); 2204 2205 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 2206 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64(); 2207 unsigned SlotSize = is64Bit ? 8 : 4; 2208 2209 MachineFunction &MF = *MBB.getParent(); 2210 unsigned FPReg = RI.getFrameRegister(MF); 2211 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 2212 unsigned CalleeFrameSize = 0; 2213 2214 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r; 2215 for (unsigned i = CSI.size(); i != 0; --i) { 2216 unsigned Reg = CSI[i-1].getReg(); 2217 const TargetRegisterClass *RegClass = CSI[i-1].getRegClass(); 2218 // Add the callee-saved register as live-in. It's killed at the spill. 2219 MBB.addLiveIn(Reg); 2220 if (Reg == FPReg) 2221 // X86RegisterInfo::emitPrologue will handle spilling of frame register. 2222 continue; 2223 if (RegClass != &X86::VR128RegClass && !isWin64) { 2224 CalleeFrameSize += SlotSize; 2225 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill); 2226 } else { 2227 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass); 2228 } 2229 } 2230 2231 X86FI->setCalleeSavedFrameSize(CalleeFrameSize); 2232 return true; 2233} 2234 2235bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 2236 MachineBasicBlock::iterator MI, 2237 const std::vector<CalleeSavedInfo> &CSI) const { 2238 if (CSI.empty()) 2239 return false; 2240 2241 DebugLoc DL = MBB.findDebugLoc(MI); 2242 2243 MachineFunction &MF = *MBB.getParent(); 2244 unsigned FPReg = RI.getFrameRegister(MF); 2245 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 2246 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64(); 2247 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r; 2248 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 2249 unsigned Reg = CSI[i].getReg(); 2250 if (Reg == FPReg) 2251 // X86RegisterInfo::emitEpilogue will handle restoring of frame register. 2252 continue; 2253 const TargetRegisterClass *RegClass = CSI[i].getRegClass(); 2254 if (RegClass != &X86::VR128RegClass && !isWin64) { 2255 BuildMI(MBB, MI, DL, get(Opc), Reg); 2256 } else { 2257 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass); 2258 } 2259 } 2260 return true; 2261} 2262 2263static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 2264 const SmallVectorImpl<MachineOperand> &MOs, 2265 MachineInstr *MI, 2266 const TargetInstrInfo &TII) { 2267 // Create the base instruction with the memory operand as the first part. 2268 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 2269 MI->getDebugLoc(), true); 2270 MachineInstrBuilder MIB(NewMI); 2271 unsigned NumAddrOps = MOs.size(); 2272 for (unsigned i = 0; i != NumAddrOps; ++i) 2273 MIB.addOperand(MOs[i]); 2274 if (NumAddrOps < 4) // FrameIndex only 2275 addOffset(MIB, 0); 2276 2277 // Loop over the rest of the ri operands, converting them over. 2278 unsigned NumOps = MI->getDesc().getNumOperands()-2; 2279 for (unsigned i = 0; i != NumOps; ++i) { 2280 MachineOperand &MO = MI->getOperand(i+2); 2281 MIB.addOperand(MO); 2282 } 2283 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 2284 MachineOperand &MO = MI->getOperand(i); 2285 MIB.addOperand(MO); 2286 } 2287 return MIB; 2288} 2289 2290static MachineInstr *FuseInst(MachineFunction &MF, 2291 unsigned Opcode, unsigned OpNo, 2292 const SmallVectorImpl<MachineOperand> &MOs, 2293 MachineInstr *MI, const TargetInstrInfo &TII) { 2294 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 2295 MI->getDebugLoc(), true); 2296 MachineInstrBuilder MIB(NewMI); 2297 2298 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2299 MachineOperand &MO = MI->getOperand(i); 2300 if (i == OpNo) { 2301 assert(MO.isReg() && "Expected to fold into reg operand!"); 2302 unsigned NumAddrOps = MOs.size(); 2303 for (unsigned i = 0; i != NumAddrOps; ++i) 2304 MIB.addOperand(MOs[i]); 2305 if (NumAddrOps < 4) // FrameIndex only 2306 addOffset(MIB, 0); 2307 } else { 2308 MIB.addOperand(MO); 2309 } 2310 } 2311 return MIB; 2312} 2313 2314static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 2315 const SmallVectorImpl<MachineOperand> &MOs, 2316 MachineInstr *MI) { 2317 MachineFunction &MF = *MI->getParent()->getParent(); 2318 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 2319 2320 unsigned NumAddrOps = MOs.size(); 2321 for (unsigned i = 0; i != NumAddrOps; ++i) 2322 MIB.addOperand(MOs[i]); 2323 if (NumAddrOps < 4) // FrameIndex only 2324 addOffset(MIB, 0); 2325 return MIB.addImm(0); 2326} 2327 2328MachineInstr* 2329X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2330 MachineInstr *MI, unsigned i, 2331 const SmallVectorImpl<MachineOperand> &MOs, 2332 unsigned Size, unsigned Align) const { 2333 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL; 2334 bool isTwoAddrFold = false; 2335 unsigned NumOps = MI->getDesc().getNumOperands(); 2336 bool isTwoAddr = NumOps > 1 && 2337 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2338 2339 MachineInstr *NewMI = NULL; 2340 // Folding a memory location into the two-address part of a two-address 2341 // instruction is different than folding it other places. It requires 2342 // replacing the *two* registers with the memory location. 2343 if (isTwoAddr && NumOps >= 2 && i < 2 && 2344 MI->getOperand(0).isReg() && 2345 MI->getOperand(1).isReg() && 2346 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 2347 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2348 isTwoAddrFold = true; 2349 } else if (i == 0) { // If operand 0 2350 if (MI->getOpcode() == X86::MOV64r0) 2351 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI); 2352 else if (MI->getOpcode() == X86::MOV32r0) 2353 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); 2354 else if (MI->getOpcode() == X86::MOV16r0) 2355 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI); 2356 else if (MI->getOpcode() == X86::MOV8r0) 2357 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI); 2358 if (NewMI) 2359 return NewMI; 2360 2361 OpcodeTablePtr = &RegOp2MemOpTable0; 2362 } else if (i == 1) { 2363 OpcodeTablePtr = &RegOp2MemOpTable1; 2364 } else if (i == 2) { 2365 OpcodeTablePtr = &RegOp2MemOpTable2; 2366 } 2367 2368 // If table selected... 2369 if (OpcodeTablePtr) { 2370 // Find the Opcode to fuse 2371 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2372 OpcodeTablePtr->find((unsigned*)MI->getOpcode()); 2373 if (I != OpcodeTablePtr->end()) { 2374 unsigned Opcode = I->second.first; 2375 unsigned MinAlign = I->second.second; 2376 if (Align < MinAlign) 2377 return NULL; 2378 bool NarrowToMOV32rm = false; 2379 if (Size) { 2380 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize(); 2381 if (Size < RCSize) { 2382 // Check if it's safe to fold the load. If the size of the object is 2383 // narrower than the load width, then it's not. 2384 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 2385 return NULL; 2386 // If this is a 64-bit load, but the spill slot is 32, then we can do 2387 // a 32-bit load which is implicitly zero-extended. This likely is due 2388 // to liveintervalanalysis remat'ing a load from stack slot. 2389 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 2390 return NULL; 2391 Opcode = X86::MOV32rm; 2392 NarrowToMOV32rm = true; 2393 } 2394 } 2395 2396 if (isTwoAddrFold) 2397 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 2398 else 2399 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 2400 2401 if (NarrowToMOV32rm) { 2402 // If this is the special case where we use a MOV32rm to load a 32-bit 2403 // value and zero-extend the top bits. Change the destination register 2404 // to a 32-bit one. 2405 unsigned DstReg = NewMI->getOperand(0).getReg(); 2406 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 2407 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, 2408 4/*x86_subreg_32bit*/)); 2409 else 2410 NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/); 2411 } 2412 return NewMI; 2413 } 2414 } 2415 2416 // No fusion 2417 if (PrintFailedFusing) 2418 dbgs() << "We failed to fuse operand " << i << " in " << *MI; 2419 return NULL; 2420} 2421 2422 2423MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2424 MachineInstr *MI, 2425 const SmallVectorImpl<unsigned> &Ops, 2426 int FrameIndex) const { 2427 // Check switch flag 2428 if (NoFusing) return NULL; 2429 2430 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2431 switch (MI->getOpcode()) { 2432 case X86::CVTSD2SSrr: 2433 case X86::Int_CVTSD2SSrr: 2434 case X86::CVTSS2SDrr: 2435 case X86::Int_CVTSS2SDrr: 2436 case X86::RCPSSr: 2437 case X86::RCPSSr_Int: 2438 case X86::ROUNDSDr_Int: 2439 case X86::ROUNDSSr_Int: 2440 case X86::RSQRTSSr: 2441 case X86::RSQRTSSr_Int: 2442 case X86::SQRTSSr: 2443 case X86::SQRTSSr_Int: 2444 return 0; 2445 } 2446 2447 const MachineFrameInfo *MFI = MF.getFrameInfo(); 2448 unsigned Size = MFI->getObjectSize(FrameIndex); 2449 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 2450 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2451 unsigned NewOpc = 0; 2452 unsigned RCSize = 0; 2453 switch (MI->getOpcode()) { 2454 default: return NULL; 2455 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 2456 case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break; 2457 case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break; 2458 case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break; 2459 } 2460 // Check if it's safe to fold the load. If the size of the object is 2461 // narrower than the load width, then it's not. 2462 if (Size < RCSize) 2463 return NULL; 2464 // Change to CMPXXri r, 0 first. 2465 MI->setDesc(get(NewOpc)); 2466 MI->getOperand(1).ChangeToImmediate(0); 2467 } else if (Ops.size() != 1) 2468 return NULL; 2469 2470 SmallVector<MachineOperand,4> MOs; 2471 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 2472 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment); 2473} 2474 2475MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2476 MachineInstr *MI, 2477 const SmallVectorImpl<unsigned> &Ops, 2478 MachineInstr *LoadMI) const { 2479 // Check switch flag 2480 if (NoFusing) return NULL; 2481 2482 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2483 switch (MI->getOpcode()) { 2484 case X86::CVTSD2SSrr: 2485 case X86::Int_CVTSD2SSrr: 2486 case X86::CVTSS2SDrr: 2487 case X86::Int_CVTSS2SDrr: 2488 case X86::RCPSSr: 2489 case X86::RCPSSr_Int: 2490 case X86::ROUNDSDr_Int: 2491 case X86::ROUNDSSr_Int: 2492 case X86::RSQRTSSr: 2493 case X86::RSQRTSSr_Int: 2494 case X86::SQRTSSr: 2495 case X86::SQRTSSr_Int: 2496 return 0; 2497 } 2498 2499 // Determine the alignment of the load. 2500 unsigned Alignment = 0; 2501 if (LoadMI->hasOneMemOperand()) 2502 Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 2503 else 2504 switch (LoadMI->getOpcode()) { 2505 case X86::V_SET0: 2506 case X86::V_SETALLONES: 2507 Alignment = 16; 2508 break; 2509 case X86::FsFLD0SD: 2510 Alignment = 8; 2511 break; 2512 case X86::FsFLD0SS: 2513 Alignment = 4; 2514 break; 2515 default: 2516 llvm_unreachable("Don't know how to fold this instruction!"); 2517 } 2518 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2519 unsigned NewOpc = 0; 2520 switch (MI->getOpcode()) { 2521 default: return NULL; 2522 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 2523 case X86::TEST16rr: NewOpc = X86::CMP16ri; break; 2524 case X86::TEST32rr: NewOpc = X86::CMP32ri; break; 2525 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; 2526 } 2527 // Change to CMPXXri r, 0 first. 2528 MI->setDesc(get(NewOpc)); 2529 MI->getOperand(1).ChangeToImmediate(0); 2530 } else if (Ops.size() != 1) 2531 return NULL; 2532 2533 SmallVector<MachineOperand,X86AddrNumOperands> MOs; 2534 switch (LoadMI->getOpcode()) { 2535 case X86::V_SET0: 2536 case X86::V_SETALLONES: 2537 case X86::FsFLD0SD: 2538 case X86::FsFLD0SS: { 2539 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 2540 // Create a constant-pool entry and operands to load from it. 2541 2542 // x86-32 PIC requires a PIC base register for constant pools. 2543 unsigned PICBase = 0; 2544 if (TM.getRelocationModel() == Reloc::PIC_) { 2545 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2546 PICBase = X86::RIP; 2547 else 2548 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF); 2549 // This doesn't work for several reasons. 2550 // 1. GlobalBaseReg may have been spilled. 2551 // 2. It may not be live at MI. 2552 return NULL; 2553 } 2554 2555 // Create a constant-pool entry. 2556 MachineConstantPool &MCP = *MF.getConstantPool(); 2557 const Type *Ty; 2558 if (LoadMI->getOpcode() == X86::FsFLD0SS) 2559 Ty = Type::getFloatTy(MF.getFunction()->getContext()); 2560 else if (LoadMI->getOpcode() == X86::FsFLD0SD) 2561 Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 2562 else 2563 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 2564 Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ? 2565 Constant::getAllOnesValue(Ty) : 2566 Constant::getNullValue(Ty); 2567 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 2568 2569 // Create operands to load from the constant pool entry. 2570 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 2571 MOs.push_back(MachineOperand::CreateImm(1)); 2572 MOs.push_back(MachineOperand::CreateReg(0, false)); 2573 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 2574 MOs.push_back(MachineOperand::CreateReg(0, false)); 2575 break; 2576 } 2577 default: { 2578 // Folding a normal load. Just copy the load's address operands. 2579 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 2580 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i) 2581 MOs.push_back(LoadMI->getOperand(i)); 2582 break; 2583 } 2584 } 2585 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment); 2586} 2587 2588 2589bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 2590 const SmallVectorImpl<unsigned> &Ops) const { 2591 // Check switch flag 2592 if (NoFusing) return 0; 2593 2594 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2595 switch (MI->getOpcode()) { 2596 default: return false; 2597 case X86::TEST8rr: 2598 case X86::TEST16rr: 2599 case X86::TEST32rr: 2600 case X86::TEST64rr: 2601 return true; 2602 } 2603 } 2604 2605 if (Ops.size() != 1) 2606 return false; 2607 2608 unsigned OpNum = Ops[0]; 2609 unsigned Opc = MI->getOpcode(); 2610 unsigned NumOps = MI->getDesc().getNumOperands(); 2611 bool isTwoAddr = NumOps > 1 && 2612 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2613 2614 // Folding a memory location into the two-address part of a two-address 2615 // instruction is different than folding it other places. It requires 2616 // replacing the *two* registers with the memory location. 2617 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL; 2618 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 2619 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2620 } else if (OpNum == 0) { // If operand 0 2621 switch (Opc) { 2622 case X86::MOV8r0: 2623 case X86::MOV16r0: 2624 case X86::MOV32r0: 2625 case X86::MOV64r0: 2626 return true; 2627 default: break; 2628 } 2629 OpcodeTablePtr = &RegOp2MemOpTable0; 2630 } else if (OpNum == 1) { 2631 OpcodeTablePtr = &RegOp2MemOpTable1; 2632 } else if (OpNum == 2) { 2633 OpcodeTablePtr = &RegOp2MemOpTable2; 2634 } 2635 2636 if (OpcodeTablePtr) { 2637 // Find the Opcode to fuse 2638 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2639 OpcodeTablePtr->find((unsigned*)Opc); 2640 if (I != OpcodeTablePtr->end()) 2641 return true; 2642 } 2643 return false; 2644} 2645 2646bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 2647 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 2648 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2649 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2650 MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); 2651 if (I == MemOp2RegOpTable.end()) 2652 return false; 2653 unsigned Opc = I->second.first; 2654 unsigned Index = I->second.second & 0xf; 2655 bool FoldedLoad = I->second.second & (1 << 4); 2656 bool FoldedStore = I->second.second & (1 << 5); 2657 if (UnfoldLoad && !FoldedLoad) 2658 return false; 2659 UnfoldLoad &= FoldedLoad; 2660 if (UnfoldStore && !FoldedStore) 2661 return false; 2662 UnfoldStore &= FoldedStore; 2663 2664 const TargetInstrDesc &TID = get(Opc); 2665 const TargetOperandInfo &TOI = TID.OpInfo[Index]; 2666 const TargetRegisterClass *RC = TOI.getRegClass(&RI); 2667 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps; 2668 SmallVector<MachineOperand,2> BeforeOps; 2669 SmallVector<MachineOperand,2> AfterOps; 2670 SmallVector<MachineOperand,4> ImpOps; 2671 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2672 MachineOperand &Op = MI->getOperand(i); 2673 if (i >= Index && i < Index + X86AddrNumOperands) 2674 AddrOps.push_back(Op); 2675 else if (Op.isReg() && Op.isImplicit()) 2676 ImpOps.push_back(Op); 2677 else if (i < Index) 2678 BeforeOps.push_back(Op); 2679 else if (i > Index) 2680 AfterOps.push_back(Op); 2681 } 2682 2683 // Emit the load instruction. 2684 if (UnfoldLoad) { 2685 std::pair<MachineInstr::mmo_iterator, 2686 MachineInstr::mmo_iterator> MMOs = 2687 MF.extractLoadMemRefs(MI->memoperands_begin(), 2688 MI->memoperands_end()); 2689 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 2690 if (UnfoldStore) { 2691 // Address operands cannot be marked isKill. 2692 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) { 2693 MachineOperand &MO = NewMIs[0]->getOperand(i); 2694 if (MO.isReg()) 2695 MO.setIsKill(false); 2696 } 2697 } 2698 } 2699 2700 // Emit the data processing instruction. 2701 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true); 2702 MachineInstrBuilder MIB(DataMI); 2703 2704 if (FoldedStore) 2705 MIB.addReg(Reg, RegState::Define); 2706 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 2707 MIB.addOperand(BeforeOps[i]); 2708 if (FoldedLoad) 2709 MIB.addReg(Reg); 2710 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 2711 MIB.addOperand(AfterOps[i]); 2712 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 2713 MachineOperand &MO = ImpOps[i]; 2714 MIB.addReg(MO.getReg(), 2715 getDefRegState(MO.isDef()) | 2716 RegState::Implicit | 2717 getKillRegState(MO.isKill()) | 2718 getDeadRegState(MO.isDead()) | 2719 getUndefRegState(MO.isUndef())); 2720 } 2721 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 2722 unsigned NewOpc = 0; 2723 switch (DataMI->getOpcode()) { 2724 default: break; 2725 case X86::CMP64ri32: 2726 case X86::CMP32ri: 2727 case X86::CMP16ri: 2728 case X86::CMP8ri: { 2729 MachineOperand &MO0 = DataMI->getOperand(0); 2730 MachineOperand &MO1 = DataMI->getOperand(1); 2731 if (MO1.getImm() == 0) { 2732 switch (DataMI->getOpcode()) { 2733 default: break; 2734 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 2735 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 2736 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 2737 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 2738 } 2739 DataMI->setDesc(get(NewOpc)); 2740 MO1.ChangeToRegister(MO0.getReg(), false); 2741 } 2742 } 2743 } 2744 NewMIs.push_back(DataMI); 2745 2746 // Emit the store instruction. 2747 if (UnfoldStore) { 2748 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI); 2749 std::pair<MachineInstr::mmo_iterator, 2750 MachineInstr::mmo_iterator> MMOs = 2751 MF.extractStoreMemRefs(MI->memoperands_begin(), 2752 MI->memoperands_end()); 2753 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 2754 } 2755 2756 return true; 2757} 2758 2759bool 2760X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 2761 SmallVectorImpl<SDNode*> &NewNodes) const { 2762 if (!N->isMachineOpcode()) 2763 return false; 2764 2765 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2766 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode()); 2767 if (I == MemOp2RegOpTable.end()) 2768 return false; 2769 unsigned Opc = I->second.first; 2770 unsigned Index = I->second.second & 0xf; 2771 bool FoldedLoad = I->second.second & (1 << 4); 2772 bool FoldedStore = I->second.second & (1 << 5); 2773 const TargetInstrDesc &TID = get(Opc); 2774 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI); 2775 unsigned NumDefs = TID.NumDefs; 2776 std::vector<SDValue> AddrOps; 2777 std::vector<SDValue> BeforeOps; 2778 std::vector<SDValue> AfterOps; 2779 DebugLoc dl = N->getDebugLoc(); 2780 unsigned NumOps = N->getNumOperands(); 2781 for (unsigned i = 0; i != NumOps-1; ++i) { 2782 SDValue Op = N->getOperand(i); 2783 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands) 2784 AddrOps.push_back(Op); 2785 else if (i < Index-NumDefs) 2786 BeforeOps.push_back(Op); 2787 else if (i > Index-NumDefs) 2788 AfterOps.push_back(Op); 2789 } 2790 SDValue Chain = N->getOperand(NumOps-1); 2791 AddrOps.push_back(Chain); 2792 2793 // Emit the load instruction. 2794 SDNode *Load = 0; 2795 MachineFunction &MF = DAG.getMachineFunction(); 2796 if (FoldedLoad) { 2797 EVT VT = *RC->vt_begin(); 2798 std::pair<MachineInstr::mmo_iterator, 2799 MachineInstr::mmo_iterator> MMOs = 2800 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 2801 cast<MachineSDNode>(N)->memoperands_end()); 2802 bool isAligned = (*MMOs.first)->getAlignment() >= 16; 2803 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, 2804 VT, MVT::Other, &AddrOps[0], AddrOps.size()); 2805 NewNodes.push_back(Load); 2806 2807 // Preserve memory reference information. 2808 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 2809 } 2810 2811 // Emit the data processing instruction. 2812 std::vector<EVT> VTs; 2813 const TargetRegisterClass *DstRC = 0; 2814 if (TID.getNumDefs() > 0) { 2815 DstRC = TID.OpInfo[0].getRegClass(&RI); 2816 VTs.push_back(*DstRC->vt_begin()); 2817 } 2818 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 2819 EVT VT = N->getValueType(i); 2820 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) 2821 VTs.push_back(VT); 2822 } 2823 if (Load) 2824 BeforeOps.push_back(SDValue(Load, 0)); 2825 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 2826 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0], 2827 BeforeOps.size()); 2828 NewNodes.push_back(NewNode); 2829 2830 // Emit the store instruction. 2831 if (FoldedStore) { 2832 AddrOps.pop_back(); 2833 AddrOps.push_back(SDValue(NewNode, 0)); 2834 AddrOps.push_back(Chain); 2835 std::pair<MachineInstr::mmo_iterator, 2836 MachineInstr::mmo_iterator> MMOs = 2837 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 2838 cast<MachineSDNode>(N)->memoperands_end()); 2839 bool isAligned = (*MMOs.first)->getAlignment() >= 16; 2840 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, 2841 isAligned, TM), 2842 dl, MVT::Other, 2843 &AddrOps[0], AddrOps.size()); 2844 NewNodes.push_back(Store); 2845 2846 // Preserve memory reference information. 2847 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 2848 } 2849 2850 return true; 2851} 2852 2853unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 2854 bool UnfoldLoad, bool UnfoldStore, 2855 unsigned *LoadRegIndex) const { 2856 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2857 MemOp2RegOpTable.find((unsigned*)Opc); 2858 if (I == MemOp2RegOpTable.end()) 2859 return 0; 2860 bool FoldedLoad = I->second.second & (1 << 4); 2861 bool FoldedStore = I->second.second & (1 << 5); 2862 if (UnfoldLoad && !FoldedLoad) 2863 return 0; 2864 if (UnfoldStore && !FoldedStore) 2865 return 0; 2866 if (LoadRegIndex) 2867 *LoadRegIndex = I->second.second & 0xf; 2868 return I->second.first; 2869} 2870 2871bool 2872X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 2873 int64_t &Offset1, int64_t &Offset2) const { 2874 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 2875 return false; 2876 unsigned Opc1 = Load1->getMachineOpcode(); 2877 unsigned Opc2 = Load2->getMachineOpcode(); 2878 switch (Opc1) { 2879 default: return false; 2880 case X86::MOV8rm: 2881 case X86::MOV16rm: 2882 case X86::MOV32rm: 2883 case X86::MOV64rm: 2884 case X86::LD_Fp32m: 2885 case X86::LD_Fp64m: 2886 case X86::LD_Fp80m: 2887 case X86::MOVSSrm: 2888 case X86::MOVSDrm: 2889 case X86::MMX_MOVD64rm: 2890 case X86::MMX_MOVQ64rm: 2891 case X86::FsMOVAPSrm: 2892 case X86::FsMOVAPDrm: 2893 case X86::MOVAPSrm: 2894 case X86::MOVUPSrm: 2895 case X86::MOVUPSrm_Int: 2896 case X86::MOVAPDrm: 2897 case X86::MOVDQArm: 2898 case X86::MOVDQUrm: 2899 case X86::MOVDQUrm_Int: 2900 break; 2901 } 2902 switch (Opc2) { 2903 default: return false; 2904 case X86::MOV8rm: 2905 case X86::MOV16rm: 2906 case X86::MOV32rm: 2907 case X86::MOV64rm: 2908 case X86::LD_Fp32m: 2909 case X86::LD_Fp64m: 2910 case X86::LD_Fp80m: 2911 case X86::MOVSSrm: 2912 case X86::MOVSDrm: 2913 case X86::MMX_MOVD64rm: 2914 case X86::MMX_MOVQ64rm: 2915 case X86::FsMOVAPSrm: 2916 case X86::FsMOVAPDrm: 2917 case X86::MOVAPSrm: 2918 case X86::MOVUPSrm: 2919 case X86::MOVUPSrm_Int: 2920 case X86::MOVAPDrm: 2921 case X86::MOVDQArm: 2922 case X86::MOVDQUrm: 2923 case X86::MOVDQUrm_Int: 2924 break; 2925 } 2926 2927 // Check if chain operands and base addresses match. 2928 if (Load1->getOperand(0) != Load2->getOperand(0) || 2929 Load1->getOperand(5) != Load2->getOperand(5)) 2930 return false; 2931 // Segment operands should match as well. 2932 if (Load1->getOperand(4) != Load2->getOperand(4)) 2933 return false; 2934 // Scale should be 1, Index should be Reg0. 2935 if (Load1->getOperand(1) == Load2->getOperand(1) && 2936 Load1->getOperand(2) == Load2->getOperand(2)) { 2937 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 2938 return false; 2939 SDValue Op2 = Load1->getOperand(2); 2940 if (!isa<RegisterSDNode>(Op2) || 2941 cast<RegisterSDNode>(Op2)->getReg() != 0) 2942 return 0; 2943 2944 // Now let's examine the displacements. 2945 if (isa<ConstantSDNode>(Load1->getOperand(3)) && 2946 isa<ConstantSDNode>(Load2->getOperand(3))) { 2947 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 2948 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 2949 return true; 2950 } 2951 } 2952 return false; 2953} 2954 2955bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 2956 int64_t Offset1, int64_t Offset2, 2957 unsigned NumLoads) const { 2958 assert(Offset2 > Offset1); 2959 if ((Offset2 - Offset1) / 8 > 64) 2960 return false; 2961 2962 unsigned Opc1 = Load1->getMachineOpcode(); 2963 unsigned Opc2 = Load2->getMachineOpcode(); 2964 if (Opc1 != Opc2) 2965 return false; // FIXME: overly conservative? 2966 2967 switch (Opc1) { 2968 default: break; 2969 case X86::LD_Fp32m: 2970 case X86::LD_Fp64m: 2971 case X86::LD_Fp80m: 2972 case X86::MMX_MOVD64rm: 2973 case X86::MMX_MOVQ64rm: 2974 return false; 2975 } 2976 2977 EVT VT = Load1->getValueType(0); 2978 switch (VT.getSimpleVT().SimpleTy) { 2979 default: { 2980 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 2981 // have 16 of them to play with. 2982 if (TM.getSubtargetImpl()->is64Bit()) { 2983 if (NumLoads >= 3) 2984 return false; 2985 } else if (NumLoads) 2986 return false; 2987 break; 2988 } 2989 case MVT::i8: 2990 case MVT::i16: 2991 case MVT::i32: 2992 case MVT::i64: 2993 case MVT::f32: 2994 case MVT::f64: 2995 if (NumLoads) 2996 return false; 2997 } 2998 2999 return true; 3000} 3001 3002 3003bool X86InstrInfo:: 3004ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 3005 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 3006 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 3007 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 3008 return true; 3009 Cond[0].setImm(GetOppositeBranchCondition(CC)); 3010 return false; 3011} 3012 3013bool X86InstrInfo:: 3014isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 3015 // FIXME: Return false for x87 stack register classes for now. We can't 3016 // allow any loads of these registers before FpGet_ST0_80. 3017 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 3018 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 3019} 3020 3021unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) { 3022 switch (Desc->TSFlags & X86II::ImmMask) { 3023 case X86II::Imm8: return 1; 3024 case X86II::Imm16: return 2; 3025 case X86II::Imm32: return 4; 3026 case X86II::Imm64: return 8; 3027 default: llvm_unreachable("Immediate size not set!"); 3028 return 0; 3029 } 3030} 3031 3032/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register? 3033/// e.g. r8, xmm8, etc. 3034bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) { 3035 if (!MO.isReg()) return false; 3036 switch (MO.getReg()) { 3037 default: break; 3038 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 3039 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 3040 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 3041 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 3042 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 3043 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 3044 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 3045 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 3046 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 3047 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 3048 return true; 3049 } 3050 return false; 3051} 3052 3053 3054/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64 3055/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 3056/// size, and 3) use of X86-64 extended registers. 3057unsigned X86InstrInfo::determineREX(const MachineInstr &MI) { 3058 unsigned REX = 0; 3059 const TargetInstrDesc &Desc = MI.getDesc(); 3060 3061 // Pseudo instructions do not need REX prefix byte. 3062 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) 3063 return 0; 3064 if (Desc.TSFlags & X86II::REX_W) 3065 REX |= 1 << 3; 3066 3067 unsigned NumOps = Desc.getNumOperands(); 3068 if (NumOps) { 3069 bool isTwoAddr = NumOps > 1 && 3070 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1; 3071 3072 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 3073 unsigned i = isTwoAddr ? 1 : 0; 3074 for (unsigned e = NumOps; i != e; ++i) { 3075 const MachineOperand& MO = MI.getOperand(i); 3076 if (MO.isReg()) { 3077 unsigned Reg = MO.getReg(); 3078 if (isX86_64NonExtLowByteReg(Reg)) 3079 REX |= 0x40; 3080 } 3081 } 3082 3083 switch (Desc.TSFlags & X86II::FormMask) { 3084 case X86II::MRMInitReg: 3085 if (isX86_64ExtendedReg(MI.getOperand(0))) 3086 REX |= (1 << 0) | (1 << 2); 3087 break; 3088 case X86II::MRMSrcReg: { 3089 if (isX86_64ExtendedReg(MI.getOperand(0))) 3090 REX |= 1 << 2; 3091 i = isTwoAddr ? 2 : 1; 3092 for (unsigned e = NumOps; i != e; ++i) { 3093 const MachineOperand& MO = MI.getOperand(i); 3094 if (isX86_64ExtendedReg(MO)) 3095 REX |= 1 << 0; 3096 } 3097 break; 3098 } 3099 case X86II::MRMSrcMem: { 3100 if (isX86_64ExtendedReg(MI.getOperand(0))) 3101 REX |= 1 << 2; 3102 unsigned Bit = 0; 3103 i = isTwoAddr ? 2 : 1; 3104 for (; i != NumOps; ++i) { 3105 const MachineOperand& MO = MI.getOperand(i); 3106 if (MO.isReg()) { 3107 if (isX86_64ExtendedReg(MO)) 3108 REX |= 1 << Bit; 3109 Bit++; 3110 } 3111 } 3112 break; 3113 } 3114 case X86II::MRM0m: case X86II::MRM1m: 3115 case X86II::MRM2m: case X86II::MRM3m: 3116 case X86II::MRM4m: case X86II::MRM5m: 3117 case X86II::MRM6m: case X86II::MRM7m: 3118 case X86II::MRMDestMem: { 3119 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands); 3120 i = isTwoAddr ? 1 : 0; 3121 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e))) 3122 REX |= 1 << 2; 3123 unsigned Bit = 0; 3124 for (; i != e; ++i) { 3125 const MachineOperand& MO = MI.getOperand(i); 3126 if (MO.isReg()) { 3127 if (isX86_64ExtendedReg(MO)) 3128 REX |= 1 << Bit; 3129 Bit++; 3130 } 3131 } 3132 break; 3133 } 3134 default: { 3135 if (isX86_64ExtendedReg(MI.getOperand(0))) 3136 REX |= 1 << 0; 3137 i = isTwoAddr ? 2 : 1; 3138 for (unsigned e = NumOps; i != e; ++i) { 3139 const MachineOperand& MO = MI.getOperand(i); 3140 if (isX86_64ExtendedReg(MO)) 3141 REX |= 1 << 2; 3142 } 3143 break; 3144 } 3145 } 3146 } 3147 return REX; 3148} 3149 3150/// sizePCRelativeBlockAddress - This method returns the size of a PC 3151/// relative block address instruction 3152/// 3153static unsigned sizePCRelativeBlockAddress() { 3154 return 4; 3155} 3156 3157/// sizeGlobalAddress - Give the size of the emission of this global address 3158/// 3159static unsigned sizeGlobalAddress(bool dword) { 3160 return dword ? 8 : 4; 3161} 3162 3163/// sizeConstPoolAddress - Give the size of the emission of this constant 3164/// pool address 3165/// 3166static unsigned sizeConstPoolAddress(bool dword) { 3167 return dword ? 8 : 4; 3168} 3169 3170/// sizeExternalSymbolAddress - Give the size of the emission of this external 3171/// symbol 3172/// 3173static unsigned sizeExternalSymbolAddress(bool dword) { 3174 return dword ? 8 : 4; 3175} 3176 3177/// sizeJumpTableAddress - Give the size of the emission of this jump 3178/// table address 3179/// 3180static unsigned sizeJumpTableAddress(bool dword) { 3181 return dword ? 8 : 4; 3182} 3183 3184static unsigned sizeConstant(unsigned Size) { 3185 return Size; 3186} 3187 3188static unsigned sizeRegModRMByte(){ 3189 return 1; 3190} 3191 3192static unsigned sizeSIBByte(){ 3193 return 1; 3194} 3195 3196static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) { 3197 unsigned FinalSize = 0; 3198 // If this is a simple integer displacement that doesn't require a relocation. 3199 if (!RelocOp) { 3200 FinalSize += sizeConstant(4); 3201 return FinalSize; 3202 } 3203 3204 // Otherwise, this is something that requires a relocation. 3205 if (RelocOp->isGlobal()) { 3206 FinalSize += sizeGlobalAddress(false); 3207 } else if (RelocOp->isCPI()) { 3208 FinalSize += sizeConstPoolAddress(false); 3209 } else if (RelocOp->isJTI()) { 3210 FinalSize += sizeJumpTableAddress(false); 3211 } else { 3212 llvm_unreachable("Unknown value to relocate!"); 3213 } 3214 return FinalSize; 3215} 3216 3217static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op, 3218 bool IsPIC, bool Is64BitMode) { 3219 const MachineOperand &Op3 = MI.getOperand(Op+3); 3220 int DispVal = 0; 3221 const MachineOperand *DispForReloc = 0; 3222 unsigned FinalSize = 0; 3223 3224 // Figure out what sort of displacement we have to handle here. 3225 if (Op3.isGlobal()) { 3226 DispForReloc = &Op3; 3227 } else if (Op3.isCPI()) { 3228 if (Is64BitMode || IsPIC) { 3229 DispForReloc = &Op3; 3230 } else { 3231 DispVal = 1; 3232 } 3233 } else if (Op3.isJTI()) { 3234 if (Is64BitMode || IsPIC) { 3235 DispForReloc = &Op3; 3236 } else { 3237 DispVal = 1; 3238 } 3239 } else { 3240 DispVal = 1; 3241 } 3242 3243 const MachineOperand &Base = MI.getOperand(Op); 3244 const MachineOperand &IndexReg = MI.getOperand(Op+2); 3245 3246 unsigned BaseReg = Base.getReg(); 3247 3248 // Is a SIB byte needed? 3249 if ((!Is64BitMode || DispForReloc || BaseReg != 0) && 3250 IndexReg.getReg() == 0 && 3251 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) { 3252 if (BaseReg == 0) { // Just a displacement? 3253 // Emit special case [disp32] encoding 3254 ++FinalSize; 3255 FinalSize += getDisplacementFieldSize(DispForReloc); 3256 } else { 3257 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg); 3258 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { 3259 // Emit simple indirect register encoding... [EAX] f.e. 3260 ++FinalSize; 3261 // Be pessimistic and assume it's a disp32, not a disp8 3262 } else { 3263 // Emit the most general non-SIB encoding: [REG+disp32] 3264 ++FinalSize; 3265 FinalSize += getDisplacementFieldSize(DispForReloc); 3266 } 3267 } 3268 3269 } else { // We need a SIB byte, so start by outputting the ModR/M byte first 3270 assert(IndexReg.getReg() != X86::ESP && 3271 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 3272 3273 bool ForceDisp32 = false; 3274 if (BaseReg == 0 || DispForReloc) { 3275 // Emit the normal disp32 encoding. 3276 ++FinalSize; 3277 ForceDisp32 = true; 3278 } else { 3279 ++FinalSize; 3280 } 3281 3282 FinalSize += sizeSIBByte(); 3283 3284 // Do we need to output a displacement? 3285 if (DispVal != 0 || ForceDisp32) { 3286 FinalSize += getDisplacementFieldSize(DispForReloc); 3287 } 3288 } 3289 return FinalSize; 3290} 3291 3292 3293static unsigned GetInstSizeWithDesc(const MachineInstr &MI, 3294 const TargetInstrDesc *Desc, 3295 bool IsPIC, bool Is64BitMode) { 3296 3297 unsigned Opcode = Desc->Opcode; 3298 unsigned FinalSize = 0; 3299 3300 // Emit the lock opcode prefix as needed. 3301 if (Desc->TSFlags & X86II::LOCK) ++FinalSize; 3302 3303 // Emit segment override opcode prefix as needed. 3304 switch (Desc->TSFlags & X86II::SegOvrMask) { 3305 case X86II::FS: 3306 case X86II::GS: 3307 ++FinalSize; 3308 break; 3309 default: llvm_unreachable("Invalid segment!"); 3310 case 0: break; // No segment override! 3311 } 3312 3313 // Emit the repeat opcode prefix as needed. 3314 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize; 3315 3316 // Emit the operand size opcode prefix as needed. 3317 if (Desc->TSFlags & X86II::OpSize) ++FinalSize; 3318 3319 // Emit the address size opcode prefix as needed. 3320 if (Desc->TSFlags & X86II::AdSize) ++FinalSize; 3321 3322 bool Need0FPrefix = false; 3323 switch (Desc->TSFlags & X86II::Op0Mask) { 3324 case X86II::TB: // Two-byte opcode prefix 3325 case X86II::T8: // 0F 38 3326 case X86II::TA: // 0F 3A 3327 Need0FPrefix = true; 3328 break; 3329 case X86II::TF: // F2 0F 38 3330 ++FinalSize; 3331 Need0FPrefix = true; 3332 break; 3333 case X86II::REP: break; // already handled. 3334 case X86II::XS: // F3 0F 3335 ++FinalSize; 3336 Need0FPrefix = true; 3337 break; 3338 case X86II::XD: // F2 0F 3339 ++FinalSize; 3340 Need0FPrefix = true; 3341 break; 3342 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: 3343 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: 3344 ++FinalSize; 3345 break; // Two-byte opcode prefix 3346 default: llvm_unreachable("Invalid prefix!"); 3347 case 0: break; // No prefix! 3348 } 3349 3350 if (Is64BitMode) { 3351 // REX prefix 3352 unsigned REX = X86InstrInfo::determineREX(MI); 3353 if (REX) 3354 ++FinalSize; 3355 } 3356 3357 // 0x0F escape code must be emitted just before the opcode. 3358 if (Need0FPrefix) 3359 ++FinalSize; 3360 3361 switch (Desc->TSFlags & X86II::Op0Mask) { 3362 case X86II::T8: // 0F 38 3363 ++FinalSize; 3364 break; 3365 case X86II::TA: // 0F 3A 3366 ++FinalSize; 3367 break; 3368 case X86II::TF: // F2 0F 38 3369 ++FinalSize; 3370 break; 3371 } 3372 3373 // If this is a two-address instruction, skip one of the register operands. 3374 unsigned NumOps = Desc->getNumOperands(); 3375 unsigned CurOp = 0; 3376 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1) 3377 CurOp++; 3378 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0) 3379 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 3380 --NumOps; 3381 3382 switch (Desc->TSFlags & X86II::FormMask) { 3383 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!"); 3384 case X86II::Pseudo: 3385 // Remember the current PC offset, this is the PIC relocation 3386 // base address. 3387 switch (Opcode) { 3388 default: 3389 break; 3390 case TargetInstrInfo::INLINEASM: { 3391 const MachineFunction *MF = MI.getParent()->getParent(); 3392 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 3393 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(), 3394 *MF->getTarget().getMCAsmInfo()); 3395 break; 3396 } 3397 case TargetInstrInfo::DBG_LABEL: 3398 case TargetInstrInfo::EH_LABEL: 3399 break; 3400 case TargetInstrInfo::IMPLICIT_DEF: 3401 case TargetInstrInfo::KILL: 3402 case X86::FP_REG_KILL: 3403 break; 3404 case X86::MOVPC32r: { 3405 // This emits the "call" portion of this pseudo instruction. 3406 ++FinalSize; 3407 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 3408 break; 3409 } 3410 } 3411 CurOp = NumOps; 3412 break; 3413 case X86II::RawFrm: 3414 ++FinalSize; 3415 3416 if (CurOp != NumOps) { 3417 const MachineOperand &MO = MI.getOperand(CurOp++); 3418 if (MO.isMBB()) { 3419 FinalSize += sizePCRelativeBlockAddress(); 3420 } else if (MO.isGlobal()) { 3421 FinalSize += sizeGlobalAddress(false); 3422 } else if (MO.isSymbol()) { 3423 FinalSize += sizeExternalSymbolAddress(false); 3424 } else if (MO.isImm()) { 3425 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 3426 } else { 3427 llvm_unreachable("Unknown RawFrm operand!"); 3428 } 3429 } 3430 break; 3431 3432 case X86II::AddRegFrm: 3433 ++FinalSize; 3434 ++CurOp; 3435 3436 if (CurOp != NumOps) { 3437 const MachineOperand &MO1 = MI.getOperand(CurOp++); 3438 unsigned Size = X86InstrInfo::sizeOfImm(Desc); 3439 if (MO1.isImm()) 3440 FinalSize += sizeConstant(Size); 3441 else { 3442 bool dword = false; 3443 if (Opcode == X86::MOV64ri) 3444 dword = true; 3445 if (MO1.isGlobal()) { 3446 FinalSize += sizeGlobalAddress(dword); 3447 } else if (MO1.isSymbol()) 3448 FinalSize += sizeExternalSymbolAddress(dword); 3449 else if (MO1.isCPI()) 3450 FinalSize += sizeConstPoolAddress(dword); 3451 else if (MO1.isJTI()) 3452 FinalSize += sizeJumpTableAddress(dword); 3453 } 3454 } 3455 break; 3456 3457 case X86II::MRMDestReg: { 3458 ++FinalSize; 3459 FinalSize += sizeRegModRMByte(); 3460 CurOp += 2; 3461 if (CurOp != NumOps) { 3462 ++CurOp; 3463 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 3464 } 3465 break; 3466 } 3467 case X86II::MRMDestMem: { 3468 ++FinalSize; 3469 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 3470 CurOp += X86AddrNumOperands + 1; 3471 if (CurOp != NumOps) { 3472 ++CurOp; 3473 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 3474 } 3475 break; 3476 } 3477 3478 case X86II::MRMSrcReg: 3479 ++FinalSize; 3480 FinalSize += sizeRegModRMByte(); 3481 CurOp += 2; 3482 if (CurOp != NumOps) { 3483 ++CurOp; 3484 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 3485 } 3486 break; 3487 3488 case X86II::MRMSrcMem: { 3489 int AddrOperands; 3490 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || 3491 Opcode == X86::LEA16r || Opcode == X86::LEA32r) 3492 AddrOperands = X86AddrNumOperands - 1; // No segment register 3493 else 3494 AddrOperands = X86AddrNumOperands; 3495 3496 ++FinalSize; 3497 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode); 3498 CurOp += AddrOperands + 1; 3499 if (CurOp != NumOps) { 3500 ++CurOp; 3501 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 3502 } 3503 break; 3504 } 3505 3506 case X86II::MRM0r: case X86II::MRM1r: 3507 case X86II::MRM2r: case X86II::MRM3r: 3508 case X86II::MRM4r: case X86II::MRM5r: 3509 case X86II::MRM6r: case X86II::MRM7r: 3510 ++FinalSize; 3511 if (Desc->getOpcode() == X86::LFENCE || 3512 Desc->getOpcode() == X86::MFENCE) { 3513 // Special handling of lfence and mfence; 3514 FinalSize += sizeRegModRMByte(); 3515 } else if (Desc->getOpcode() == X86::MONITOR || 3516 Desc->getOpcode() == X86::MWAIT) { 3517 // Special handling of monitor and mwait. 3518 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode. 3519 } else { 3520 ++CurOp; 3521 FinalSize += sizeRegModRMByte(); 3522 } 3523 3524 if (CurOp != NumOps) { 3525 const MachineOperand &MO1 = MI.getOperand(CurOp++); 3526 unsigned Size = X86InstrInfo::sizeOfImm(Desc); 3527 if (MO1.isImm()) 3528 FinalSize += sizeConstant(Size); 3529 else { 3530 bool dword = false; 3531 if (Opcode == X86::MOV64ri32) 3532 dword = true; 3533 if (MO1.isGlobal()) { 3534 FinalSize += sizeGlobalAddress(dword); 3535 } else if (MO1.isSymbol()) 3536 FinalSize += sizeExternalSymbolAddress(dword); 3537 else if (MO1.isCPI()) 3538 FinalSize += sizeConstPoolAddress(dword); 3539 else if (MO1.isJTI()) 3540 FinalSize += sizeJumpTableAddress(dword); 3541 } 3542 } 3543 break; 3544 3545 case X86II::MRM0m: case X86II::MRM1m: 3546 case X86II::MRM2m: case X86II::MRM3m: 3547 case X86II::MRM4m: case X86II::MRM5m: 3548 case X86II::MRM6m: case X86II::MRM7m: { 3549 3550 ++FinalSize; 3551 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 3552 CurOp += X86AddrNumOperands; 3553 3554 if (CurOp != NumOps) { 3555 const MachineOperand &MO = MI.getOperand(CurOp++); 3556 unsigned Size = X86InstrInfo::sizeOfImm(Desc); 3557 if (MO.isImm()) 3558 FinalSize += sizeConstant(Size); 3559 else { 3560 bool dword = false; 3561 if (Opcode == X86::MOV64mi32) 3562 dword = true; 3563 if (MO.isGlobal()) { 3564 FinalSize += sizeGlobalAddress(dword); 3565 } else if (MO.isSymbol()) 3566 FinalSize += sizeExternalSymbolAddress(dword); 3567 else if (MO.isCPI()) 3568 FinalSize += sizeConstPoolAddress(dword); 3569 else if (MO.isJTI()) 3570 FinalSize += sizeJumpTableAddress(dword); 3571 } 3572 } 3573 break; 3574 } 3575 3576 case X86II::MRMInitReg: 3577 ++FinalSize; 3578 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg). 3579 FinalSize += sizeRegModRMByte(); 3580 ++CurOp; 3581 break; 3582 } 3583 3584 if (!Desc->isVariadic() && CurOp != NumOps) { 3585 std::string msg; 3586 raw_string_ostream Msg(msg); 3587 Msg << "Cannot determine size: " << MI; 3588 llvm_report_error(Msg.str()); 3589 } 3590 3591 3592 return FinalSize; 3593} 3594 3595 3596unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 3597 const TargetInstrDesc &Desc = MI->getDesc(); 3598 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_; 3599 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit(); 3600 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode); 3601 if (Desc.getOpcode() == X86::MOVPC32r) 3602 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode); 3603 return Size; 3604} 3605 3606/// getGlobalBaseReg - Return a virtual register initialized with the 3607/// the global base register value. Output instructions required to 3608/// initialize the register in the function entry block, if necessary. 3609/// 3610unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 3611 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 3612 "X86-64 PIC uses RIP relative addressing"); 3613 3614 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 3615 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 3616 if (GlobalBaseReg != 0) 3617 return GlobalBaseReg; 3618 3619 // Insert the set of GlobalBaseReg into the first MBB of the function 3620 MachineBasicBlock &FirstMBB = MF->front(); 3621 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 3622 DebugLoc DL = DebugLoc::getUnknownLoc(); 3623 if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc(); 3624 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 3625 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3626 3627 const TargetInstrInfo *TII = TM.getInstrInfo(); 3628 // Operand of MovePCtoStack is completely ignored by asm printer. It's 3629 // only used in JIT code emission as displacement to pc. 3630 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 3631 3632 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 3633 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 3634 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) { 3635 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3636 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 3637 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 3638 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 3639 X86II::MO_GOT_ABSOLUTE_ADDRESS); 3640 } else { 3641 GlobalBaseReg = PC; 3642 } 3643 3644 X86FI->setGlobalBaseReg(GlobalBaseReg); 3645 return GlobalBaseReg; 3646} 3647