X86ISelLowering.h revision 234353
1193323Sed//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines the interfaces that X86 uses to lower LLVM code into a 11193323Sed// selection DAG. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#ifndef X86ISELLOWERING_H 16193323Sed#define X86ISELLOWERING_H 17193323Sed 18193323Sed#include "X86Subtarget.h" 19193323Sed#include "X86RegisterInfo.h" 20193323Sed#include "X86MachineFunctionInfo.h" 21193323Sed#include "llvm/Target/TargetLowering.h" 22203954Srdivacky#include "llvm/Target/TargetOptions.h" 23193323Sed#include "llvm/CodeGen/FastISel.h" 24193323Sed#include "llvm/CodeGen/SelectionDAG.h" 25193323Sed#include "llvm/CodeGen/CallingConvLower.h" 26193323Sed 27193323Sednamespace llvm { 28193323Sed namespace X86ISD { 29193323Sed // X86 Specific DAG Nodes 30193323Sed enum NodeType { 31193323Sed // Start the numbering where the builtin ops leave off. 32193323Sed FIRST_NUMBER = ISD::BUILTIN_OP_END, 33193323Sed 34193323Sed /// BSF - Bit scan forward. 35193323Sed /// BSR - Bit scan reverse. 36193323Sed BSF, 37193323Sed BSR, 38193323Sed 39193323Sed /// SHLD, SHRD - Double shift instructions. These correspond to 40193323Sed /// X86::SHLDxx and X86::SHRDxx instructions. 41193323Sed SHLD, 42193323Sed SHRD, 43193323Sed 44193323Sed /// FAND - Bitwise logical AND of floating point values. This corresponds 45193323Sed /// to X86::ANDPS or X86::ANDPD. 46193323Sed FAND, 47193323Sed 48193323Sed /// FOR - Bitwise logical OR of floating point values. This corresponds 49193323Sed /// to X86::ORPS or X86::ORPD. 50193323Sed FOR, 51193323Sed 52193323Sed /// FXOR - Bitwise logical XOR of floating point values. This corresponds 53193323Sed /// to X86::XORPS or X86::XORPD. 54193323Sed FXOR, 55193323Sed 56193323Sed /// FSRL - Bitwise logical right shift of floating point values. These 57193323Sed /// corresponds to X86::PSRLDQ. 58193323Sed FSRL, 59193323Sed 60198090Srdivacky /// CALL - These operations represent an abstract X86 call 61193323Sed /// instruction, which includes a bunch of information. In particular the 62193323Sed /// operands of these node are: 63193323Sed /// 64193323Sed /// #0 - The incoming token chain 65193323Sed /// #1 - The callee 66193323Sed /// #2 - The number of arg bytes the caller pushes on the stack. 67193323Sed /// #3 - The number of arg bytes the callee pops off the stack. 68193323Sed /// #4 - The value to pass in AL/AX/EAX (optional) 69193323Sed /// #5 - The value to pass in DL/DX/EDX (optional) 70193323Sed /// 71193323Sed /// The result values of these nodes are: 72193323Sed /// 73193323Sed /// #0 - The outgoing token chain 74193323Sed /// #1 - The first register result value (optional) 75193323Sed /// #2 - The second register result value (optional) 76193323Sed /// 77193323Sed CALL, 78198090Srdivacky 79218893Sdim /// RDTSC_DAG - This operation implements the lowering for 80193323Sed /// readcyclecounter 81193323Sed RDTSC_DAG, 82193323Sed 83193323Sed /// X86 compare and logical compare instructions. 84193323Sed CMP, COMI, UCOMI, 85193323Sed 86193323Sed /// X86 bit-test instructions. 87193323Sed BT, 88193323Sed 89218893Sdim /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS 90218893Sdim /// operand, usually produced by a CMP instruction. 91193323Sed SETCC, 92193323Sed 93200581Srdivacky // Same as SETCC except it's materialized with a sbb and the value is all 94200581Srdivacky // one's or all zero's. 95218893Sdim SETCC_CARRY, // R = carry_bit ? ~0 : 0 96200581Srdivacky 97223017Sdim /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. 98223017Sdim /// Operands are two FP values to compare; result is a mask of 99223017Sdim /// 0s or 1s. Generally DTRT for C/C++ with NaNs. 100223017Sdim FSETCCss, FSETCCsd, 101223017Sdim 102223017Sdim /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, 103223017Sdim /// result in an integer GPR. Needs masking for scalar result. 104223017Sdim FGETSIGNx86, 105223017Sdim 106193323Sed /// X86 conditional moves. Operand 0 and operand 1 are the two values 107193323Sed /// to select from. Operand 2 is the condition code, and operand 3 is the 108193323Sed /// flag operand produced by a CMP or TEST instruction. It also writes a 109193323Sed /// flag result. 110193323Sed CMOV, 111193323Sed 112193323Sed /// X86 conditional branches. Operand 0 is the chain operand, operand 1 113193323Sed /// is the block to branch if condition is true, operand 2 is the 114193323Sed /// condition code, and operand 3 is the flag operand produced by a CMP 115193323Sed /// or TEST instruction. 116193323Sed BRCOND, 117193323Sed 118193323Sed /// Return with a flag operand. Operand 0 is the chain operand, operand 119193323Sed /// 1 is the number of bytes of stack to pop. 120193323Sed RET_FLAG, 121193323Sed 122193323Sed /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 123193323Sed REP_STOS, 124193323Sed 125193323Sed /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 126193323Sed REP_MOVS, 127193323Sed 128193323Sed /// GlobalBaseReg - On Darwin, this node represents the result of the popl 129193323Sed /// at function entry, used for PIC code. 130193323Sed GlobalBaseReg, 131193323Sed 132193323Sed /// Wrapper - A wrapper node for TargetConstantPool, 133193323Sed /// TargetExternalSymbol, and TargetGlobalAddress. 134193323Sed Wrapper, 135193323Sed 136193323Sed /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 137193323Sed /// relative displacements. 138193323Sed WrapperRIP, 139193323Sed 140218893Sdim /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word 141218893Sdim /// of an XMM vector, with the high word zero filled. 142203954Srdivacky MOVQ2DQ, 143203954Srdivacky 144218893Sdim /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector 145218893Sdim /// to an MMX vector. If you think this is too close to the previous 146218893Sdim /// mnemonic, so do I; blame Intel. 147218893Sdim MOVDQ2Q, 148218893Sdim 149193323Sed /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 150193323Sed /// i32, corresponds to X86::PEXTRB. 151193323Sed PEXTRB, 152193323Sed 153193323Sed /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 154193323Sed /// i32, corresponds to X86::PEXTRW. 155193323Sed PEXTRW, 156193323Sed 157193323Sed /// INSERTPS - Insert any element of a 4 x float vector into any element 158193323Sed /// of a destination 4 x floatvector. 159193323Sed INSERTPS, 160193323Sed 161193323Sed /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 162193323Sed /// corresponds to X86::PINSRB. 163193323Sed PINSRB, 164193323Sed 165193323Sed /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 166193323Sed /// corresponds to X86::PINSRW. 167204642Srdivacky PINSRW, MMX_PINSRW, 168193323Sed 169193323Sed /// PSHUFB - Shuffle 16 8-bit values within a vector. 170193323Sed PSHUFB, 171219077Sdim 172224145Sdim /// ANDNP - Bitwise Logical AND NOT of Packed FP values. 173224145Sdim ANDNP, 174219077Sdim 175234353Sdim /// PSIGN - Copy integer sign. 176234353Sdim PSIGN, 177219077Sdim 178234353Sdim /// BLENDV - Blend where the selector is an XMM. 179226633Sdim BLENDV, 180219077Sdim 181234353Sdim /// BLENDxx - Blend where the selector is an immediate. 182234353Sdim BLENDPW, 183234353Sdim BLENDPS, 184234353Sdim BLENDPD, 185234353Sdim 186234353Sdim /// HADD - Integer horizontal add. 187234353Sdim HADD, 188234353Sdim 189234353Sdim /// HSUB - Integer horizontal sub. 190234353Sdim HSUB, 191234353Sdim 192226633Sdim /// FHADD - Floating point horizontal add. 193226633Sdim FHADD, 194226633Sdim 195226633Sdim /// FHSUB - Floating point horizontal sub. 196226633Sdim FHSUB, 197226633Sdim 198193323Sed /// FMAX, FMIN - Floating point max and min. 199193323Sed /// 200193323Sed FMAX, FMIN, 201193323Sed 202193323Sed /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 203193323Sed /// approximation. Note that these typically require refinement 204193323Sed /// in order to obtain suitable precision. 205193323Sed FRSQRT, FRCP, 206193323Sed 207193323Sed // TLSADDR - Thread Local Storage. 208193323Sed TLSADDR, 209218893Sdim 210210299Sed // TLSCALL - Thread Local Storage. When calling to an OS provided 211210299Sed // thunk at the address from an earlier relocation. 212210299Sed TLSCALL, 213193323Sed 214193323Sed // EH_RETURN - Exception Handling helpers. 215193323Sed EH_RETURN, 216218893Sdim 217193323Sed /// TC_RETURN - Tail call return. 218193323Sed /// operand #0 chain 219193323Sed /// operand #1 callee (register or absolute) 220193323Sed /// operand #2 stack adjustment 221193323Sed /// operand #3 optional in flag 222193323Sed TC_RETURN, 223193323Sed 224193323Sed // VZEXT_MOVL - Vector move low and zero extend. 225193323Sed VZEXT_MOVL, 226193323Sed 227234353Sdim // VSEXT_MOVL - Vector move low and sign extend. 228234353Sdim VSEXT_MOVL, 229193323Sed 230234353Sdim // VSHL, VSRL - 128-bit vector logical left / right shift 231234353Sdim VSHLDQ, VSRLDQ, 232218893Sdim 233234353Sdim // VSHL, VSRL, VSRA - Vector shift elements 234234353Sdim VSHL, VSRL, VSRA, 235234353Sdim 236234353Sdim // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate 237234353Sdim VSHLI, VSRLI, VSRAI, 238234353Sdim 239234353Sdim // CMPP - Vector packed double/float comparison. 240234353Sdim CMPP, 241234353Sdim 242193323Sed // PCMP* - Vector integer comparisons. 243234353Sdim PCMPEQ, PCMPGT, 244193323Sed 245234353Sdim // VPCOM, VPCOMU - XOP Vector integer comparisons. 246234353Sdim VPCOM, VPCOMU, 247234353Sdim 248218893Sdim // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results. 249218893Sdim ADD, SUB, ADC, SBB, SMUL, 250198090Srdivacky INC, DEC, OR, XOR, AND, 251219077Sdim 252226633Sdim ANDN, // ANDN - Bitwise AND NOT with FLAGS results. 253226633Sdim 254234353Sdim BLSI, // BLSI - Extract lowest set isolated bit 255234353Sdim BLSMSK, // BLSMSK - Get mask up to lowest set bit 256234353Sdim BLSR, // BLSR - Reset lowest set bit 257234353Sdim 258218893Sdim UMUL, // LOW, HI, FLAGS = umul LHS, RHS 259193323Sed 260193323Sed // MUL_IMM - X86 specific multiply by immediate. 261198090Srdivacky MUL_IMM, 262218893Sdim 263198090Srdivacky // PTEST - Vector bitwise comparisons 264198090Srdivacky PTEST, 265198090Srdivacky 266212904Sdim // TESTP - Vector packed fp sign bitwise comparisons 267212904Sdim TESTP, 268212904Sdim 269212904Sdim // Several flavors of instructions with vector shuffle behaviors. 270212904Sdim PALIGN, 271212904Sdim PSHUFD, 272212904Sdim PSHUFHW, 273212904Sdim PSHUFLW, 274234353Sdim SHUFP, 275212904Sdim MOVDDUP, 276212904Sdim MOVSHDUP, 277212904Sdim MOVSLDUP, 278212904Sdim MOVLHPS, 279212904Sdim MOVLHPD, 280212904Sdim MOVHLPS, 281212904Sdim MOVLPS, 282212904Sdim MOVLPD, 283212904Sdim MOVSD, 284212904Sdim MOVSS, 285234353Sdim UNPCKL, 286234353Sdim UNPCKH, 287234353Sdim VPERMILP, 288234353Sdim VPERM2X128, 289226633Sdim VBROADCAST, 290212904Sdim 291234353Sdim // PMULUDQ - Vector multiply packed unsigned doubleword integers 292234353Sdim PMULUDQ, 293234353Sdim 294198090Srdivacky // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 295198090Srdivacky // according to %al. An operator is needed so that this can be expanded 296198090Srdivacky // with control flow. 297198090Srdivacky VASTART_SAVE_XMM_REGS, 298198090Srdivacky 299218893Sdim // WIN_ALLOCA - Windows's _chkstk call to do stack probing. 300218893Sdim WIN_ALLOCA, 301204961Srdivacky 302226633Sdim // SEG_ALLOCA - For allocating variable amounts of stack space when using 303226633Sdim // segmented stacks. Check if the current stacklet has enough space, and 304226633Sdim // falls back to heap allocation if not. 305226633Sdim SEG_ALLOCA, 306226633Sdim 307234353Sdim // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui. 308234353Sdim WIN_FTOL, 309234353Sdim 310218893Sdim // Memory barrier 311218893Sdim MEMBARRIER, 312218893Sdim MFENCE, 313218893Sdim SFENCE, 314218893Sdim LFENCE, 315218893Sdim 316218893Sdim // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 317218893Sdim // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 318198090Srdivacky // Atomic 64-bit binary operations. 319198090Srdivacky ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 320198090Srdivacky ATOMSUB64_DAG, 321198090Srdivacky ATOMOR64_DAG, 322198090Srdivacky ATOMXOR64_DAG, 323198090Srdivacky ATOMAND64_DAG, 324198090Srdivacky ATOMNAND64_DAG, 325212904Sdim ATOMSWAP64_DAG, 326204961Srdivacky 327226633Sdim // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap. 328218893Sdim LCMPXCHG_DAG, 329218893Sdim LCMPXCHG8_DAG, 330226633Sdim LCMPXCHG16_DAG, 331218893Sdim 332218893Sdim // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 333218893Sdim VZEXT_LOAD, 334218893Sdim 335218893Sdim // FNSTCW16m - Store FP control world into i16 memory. 336218893Sdim FNSTCW16m, 337218893Sdim 338218893Sdim /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 339218893Sdim /// integer destination in memory and a FP reg source. This corresponds 340218893Sdim /// to the X86::FIST*m instructions and the rounding mode change stuff. It 341218893Sdim /// has two inputs (token chain and address) and two outputs (int value 342218893Sdim /// and token chain). 343218893Sdim FP_TO_INT16_IN_MEM, 344218893Sdim FP_TO_INT32_IN_MEM, 345218893Sdim FP_TO_INT64_IN_MEM, 346218893Sdim 347218893Sdim /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 348218893Sdim /// integer source in memory and FP reg result. This corresponds to the 349218893Sdim /// X86::FILD*m instructions. It has three inputs (token chain, address, 350218893Sdim /// and source type) and two outputs (FP value and token chain). FILD_FLAG 351218893Sdim /// also produces a flag). 352218893Sdim FILD, 353218893Sdim FILD_FLAG, 354218893Sdim 355218893Sdim /// FLD - This instruction implements an extending load to FP stack slots. 356218893Sdim /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 357218893Sdim /// operand, ptr to load from, and a ValueType node indicating the type 358218893Sdim /// to load to. 359218893Sdim FLD, 360218893Sdim 361218893Sdim /// FST - This instruction implements a truncating store to FP stack 362218893Sdim /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 363218893Sdim /// chain operand, value to store, address, and a ValueType to store it 364218893Sdim /// as. 365218893Sdim FST, 366218893Sdim 367218893Sdim /// VAARG_64 - This instruction grabs the address of the next argument 368218893Sdim /// from a va_list. (reads and modifies the va_list in memory) 369218893Sdim VAARG_64 370218893Sdim 371204961Srdivacky // WARNING: Do not add anything in the end unless you want the node to 372204961Srdivacky // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be 373204961Srdivacky // thought as target memory ops! 374193323Sed }; 375193323Sed } 376193323Sed 377193323Sed /// Define some predicates that are used for node matching. 378193323Sed namespace X86 { 379218893Sdim /// isVEXTRACTF128Index - Return true if the specified 380218893Sdim /// EXTRACT_SUBVECTOR operand specifies a vector extract that is 381218893Sdim /// suitable for input to VEXTRACTF128. 382218893Sdim bool isVEXTRACTF128Index(SDNode *N); 383218893Sdim 384218893Sdim /// isVINSERTF128Index - Return true if the specified 385218893Sdim /// INSERT_SUBVECTOR operand specifies a subvector insert that is 386218893Sdim /// suitable for input to VINSERTF128. 387218893Sdim bool isVINSERTF128Index(SDNode *N); 388218893Sdim 389218893Sdim /// getExtractVEXTRACTF128Immediate - Return the appropriate 390218893Sdim /// immediate to extract the specified EXTRACT_SUBVECTOR index 391218893Sdim /// with VEXTRACTF128 instructions. 392218893Sdim unsigned getExtractVEXTRACTF128Immediate(SDNode *N); 393218893Sdim 394218893Sdim /// getInsertVINSERTF128Immediate - Return the appropriate 395218893Sdim /// immediate to insert at the specified INSERT_SUBVECTOR index 396218893Sdim /// with VINSERTF128 instructions. 397218893Sdim unsigned getInsertVINSERTF128Immediate(SDNode *N); 398218893Sdim 399198090Srdivacky /// isZeroNode - Returns true if Elt is a constant zero or a floating point 400198090Srdivacky /// constant +0.0. 401198090Srdivacky bool isZeroNode(SDValue Elt); 402198090Srdivacky 403198090Srdivacky /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 404198090Srdivacky /// fit into displacement field of the instruction. 405198090Srdivacky bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 406198090Srdivacky bool hasSymbolicDisplacement = true); 407224145Sdim 408224145Sdim 409224145Sdim /// isCalleePop - Determines whether the callee is required to pop its 410224145Sdim /// own arguments. Callee pop is necessary to support tail calls. 411224145Sdim bool isCalleePop(CallingConv::ID CallingConv, 412224145Sdim bool is64Bit, bool IsVarArg, bool TailCallOpt); 413193323Sed } 414193323Sed 415193323Sed //===--------------------------------------------------------------------===// 416193323Sed // X86TargetLowering - X86 Implementation of the TargetLowering interface 417193323Sed class X86TargetLowering : public TargetLowering { 418193323Sed public: 419193323Sed explicit X86TargetLowering(X86TargetMachine &TM); 420193323Sed 421203954Srdivacky virtual unsigned getJumpTableEncoding() const; 422203954Srdivacky 423219077Sdim virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; } 424219077Sdim 425203954Srdivacky virtual const MCExpr * 426203954Srdivacky LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 427203954Srdivacky const MachineBasicBlock *MBB, unsigned uid, 428203954Srdivacky MCContext &Ctx) const; 429218893Sdim 430193323Sed /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 431193323Sed /// jumptable. 432203954Srdivacky virtual SDValue getPICJumpTableRelocBase(SDValue Table, 433203954Srdivacky SelectionDAG &DAG) const; 434203954Srdivacky virtual const MCExpr * 435203954Srdivacky getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 436203954Srdivacky unsigned JTI, MCContext &Ctx) const; 437218893Sdim 438193323Sed /// getStackPtrReg - Return the stack pointer register we are using: either 439193323Sed /// ESP or RSP. 440193323Sed unsigned getStackPtrReg() const { return X86StackPtr; } 441193323Sed 442193323Sed /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 443193323Sed /// function arguments in the caller parameter area. For X86, aggregates 444193323Sed /// that contains are placed at 16-byte boundaries while the rest are at 445193323Sed /// 4-byte boundaries. 446226633Sdim virtual unsigned getByValTypeAlignment(Type *Ty) const; 447193323Sed 448193323Sed /// getOptimalMemOpType - Returns the target specific optimal type for load 449206124Srdivacky /// and store operations as a result of memset, memcpy, and memmove 450206124Srdivacky /// lowering. If DstAlign is zero that means it's safe to destination 451206124Srdivacky /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 452206124Srdivacky /// means there isn't a need to check it against alignment requirement, 453206124Srdivacky /// probably because the source does not need to be loaded. If 454234353Sdim /// 'IsZeroVal' is true, that means it's safe to return a 455206124Srdivacky /// non-scalar-integer type, e.g. empty string source, constant, or loaded 456207618Srdivacky /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 457207618Srdivacky /// constant so it does not need to be loaded. 458207618Srdivacky /// It returns EVT::Other if the type should be determined using generic 459207618Srdivacky /// target-independent logic. 460206124Srdivacky virtual EVT 461207618Srdivacky getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 462234353Sdim bool IsZeroVal, bool MemcpyStrSrc, 463207618Srdivacky MachineFunction &MF) const; 464195340Sed 465198090Srdivacky /// allowsUnalignedMemoryAccesses - Returns true if the target allows 466198090Srdivacky /// unaligned memory accesses. of the specified type. 467198090Srdivacky virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 468198090Srdivacky return true; 469198090Srdivacky } 470198090Srdivacky 471193323Sed /// LowerOperation - Provide custom lowering hooks for some operations. 472193323Sed /// 473207618Srdivacky virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 474193323Sed 475193323Sed /// ReplaceNodeResults - Replace the results of node with an illegal result 476193323Sed /// type with new values built out of custom code. 477193323Sed /// 478193323Sed virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 479207618Srdivacky SelectionDAG &DAG) const; 480193323Sed 481218893Sdim 482193323Sed virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 483193323Sed 484207618Srdivacky /// isTypeDesirableForOp - Return true if the target has native support for 485207618Srdivacky /// the specified value type and it is 'desirable' to use the type for the 486207618Srdivacky /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 487207618Srdivacky /// instruction encodings are longer and some i16 instructions are slow. 488207618Srdivacky virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const; 489193323Sed 490207618Srdivacky /// isTypeDesirable - Return true if the target has native support for the 491207618Srdivacky /// specified value type and it is 'desirable' to use the type. e.g. On x86 492207618Srdivacky /// i16 is legal, but undesirable since i16 instruction encodings are longer 493207618Srdivacky /// and some i16 instructions are slow. 494207618Srdivacky virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const; 495207618Srdivacky 496207618Srdivacky virtual MachineBasicBlock * 497207618Srdivacky EmitInstrWithCustomInserter(MachineInstr *MI, 498207618Srdivacky MachineBasicBlock *MBB) const; 499207618Srdivacky 500218893Sdim 501193323Sed /// getTargetNodeName - This method returns the name of a target specific 502193323Sed /// DAG node. 503193323Sed virtual const char *getTargetNodeName(unsigned Opcode) const; 504193323Sed 505226633Sdim /// getSetCCResultType - Return the value type to use for ISD::SETCC. 506226633Sdim virtual EVT getSetCCResultType(EVT VT) const; 507193323Sed 508218893Sdim /// computeMaskedBitsForTargetNode - Determine which of the bits specified 509218893Sdim /// in Mask are known to be either zero or one and return them in the 510193323Sed /// KnownZero/KnownOne bitsets. 511193323Sed virtual void computeMaskedBitsForTargetNode(const SDValue Op, 512218893Sdim APInt &KnownZero, 513193323Sed APInt &KnownOne, 514193323Sed const SelectionDAG &DAG, 515193323Sed unsigned Depth = 0) const; 516193323Sed 517218893Sdim // ComputeNumSignBitsForTargetNode - Determine the number of bits in the 518218893Sdim // operation that are sign bits. 519218893Sdim virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 520218893Sdim unsigned Depth) const; 521218893Sdim 522193323Sed virtual bool 523207618Srdivacky isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 524218893Sdim 525207618Srdivacky SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 526193323Sed 527198090Srdivacky virtual bool ExpandInlineAsm(CallInst *CI) const; 528218893Sdim 529193323Sed ConstraintType getConstraintType(const std::string &Constraint) const; 530218893Sdim 531218893Sdim /// Examine constraint string and operand type and determine a weight value. 532218893Sdim /// The operand object must already have been set up with the operand type. 533218893Sdim virtual ConstraintWeight getSingleConstraintMatchWeight( 534218893Sdim AsmOperandInfo &info, const char *constraint) const; 535218893Sdim 536198090Srdivacky virtual const char *LowerXConstraint(EVT ConstraintVT) const; 537193323Sed 538193323Sed /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 539193323Sed /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 540193323Sed /// true it means one of the asm constraint of the inline asm instruction 541193323Sed /// being processed is 'm'. 542193323Sed virtual void LowerAsmOperandForConstraint(SDValue Op, 543223017Sdim std::string &Constraint, 544193323Sed std::vector<SDValue> &Ops, 545193323Sed SelectionDAG &DAG) const; 546218893Sdim 547193323Sed /// getRegForInlineAsmConstraint - Given a physical register constraint 548193323Sed /// (e.g. {edx}), return the register number and the register class for the 549193323Sed /// register. This should only be used for C_Register constraints. On 550193323Sed /// error, this returns a register number of 0. 551218893Sdim std::pair<unsigned, const TargetRegisterClass*> 552193323Sed getRegForInlineAsmConstraint(const std::string &Constraint, 553198090Srdivacky EVT VT) const; 554218893Sdim 555193323Sed /// isLegalAddressingMode - Return true if the addressing mode represented 556193323Sed /// by AM is legal for this target, for a load/store of the specified type. 557226633Sdim virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 558193323Sed 559193323Sed /// isTruncateFree - Return true if it's free to truncate a value of 560193323Sed /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 561193323Sed /// register EAX to i16 by referencing its sub-register AX. 562226633Sdim virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; 563198090Srdivacky virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 564193323Sed 565193323Sed /// isZExtFree - Return true if any actual instruction that defines a 566193323Sed /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 567193323Sed /// register. This does not necessarily include registers defined in 568193323Sed /// unknown ways, such as incoming arguments, or copies from unknown 569193323Sed /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 570193323Sed /// does not necessarily apply to truncate instructions. e.g. on x86-64, 571193323Sed /// all instructions that define 32-bit values implicit zero-extend the 572193323Sed /// result out to 64 bits. 573226633Sdim virtual bool isZExtFree(Type *Ty1, Type *Ty2) const; 574198090Srdivacky virtual bool isZExtFree(EVT VT1, EVT VT2) const; 575193323Sed 576193323Sed /// isNarrowingProfitable - Return true if it's profitable to narrow 577193323Sed /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 578193323Sed /// from i32 to i8 but not from i32 to i16. 579198090Srdivacky virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 580193323Sed 581198892Srdivacky /// isFPImmLegal - Returns true if the target can instruction select the 582198892Srdivacky /// specified FP immediate natively. If false, the legalizer will 583198892Srdivacky /// materialize the FP immediate as a load from a constant pool. 584198892Srdivacky virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 585198892Srdivacky 586193323Sed /// isShuffleMaskLegal - Targets can use this to indicate that they only 587193323Sed /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 588193323Sed /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 589193323Sed /// values are assumed to be legal. 590193323Sed virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 591198090Srdivacky EVT VT) const; 592193323Sed 593193323Sed /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 594193323Sed /// used by Targets can use this to indicate if there is a suitable 595193323Sed /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 596193323Sed /// pool entry. 597193323Sed virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 598198090Srdivacky EVT VT) const; 599193323Sed 600193323Sed /// ShouldShrinkFPConstant - If true, then instruction selection should 601193323Sed /// seek to shrink the FP constant of the specified type to a smaller type 602193323Sed /// in order to save space and / or reduce runtime. 603198090Srdivacky virtual bool ShouldShrinkFPConstant(EVT VT) const { 604193323Sed // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 605193323Sed // expensive than a straight movsd. On the other hand, it's important to 606193323Sed // shrink long double fp constant since fldt is very slow. 607193323Sed return !X86ScalarSSEf64 || VT == MVT::f80; 608193323Sed } 609218893Sdim 610208599Srdivacky const X86Subtarget* getSubtarget() const { 611193323Sed return Subtarget; 612193323Sed } 613193323Sed 614193323Sed /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 615193323Sed /// computed in an SSE register, not on the X87 floating point stack. 616198090Srdivacky bool isScalarFPTypeInSSEReg(EVT VT) const { 617193323Sed return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 618193323Sed (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 619193323Sed } 620193323Sed 621234353Sdim /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine 622234353Sdim /// for fptoui. 623234353Sdim bool isTargetFTOL() const { 624234353Sdim return Subtarget->isTargetWindows() && !Subtarget->is64Bit(); 625234353Sdim } 626234353Sdim 627234353Sdim /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be 628234353Sdim /// used for fptoui to the given type. 629234353Sdim bool isIntegerTypeFTOL(EVT VT) const { 630234353Sdim return isTargetFTOL() && VT == MVT::i64; 631234353Sdim } 632234353Sdim 633193323Sed /// createFastISel - This method returns a target specific FastISel object, 634193323Sed /// or null if the target does not support "fast" ISel. 635210299Sed virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const; 636195340Sed 637210299Sed /// getStackCookieLocation - Return true if the target stores stack 638210299Sed /// protector cookies at a fixed offset in some non-standard address 639210299Sed /// space, and populates the address space and offset as 640210299Sed /// appropriate. 641210299Sed virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const; 642210299Sed 643223017Sdim SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 644223017Sdim SelectionDAG &DAG) const; 645223017Sdim 646212904Sdim protected: 647212904Sdim std::pair<const TargetRegisterClass*, uint8_t> 648212904Sdim findRepresentativeClass(EVT VT) const; 649212904Sdim 650193323Sed private: 651193323Sed /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 652193323Sed /// make the right decision when generating code for different targets. 653193323Sed const X86Subtarget *Subtarget; 654193323Sed const X86RegisterInfo *RegInfo; 655193323Sed const TargetData *TD; 656193323Sed 657193323Sed /// X86StackPtr - X86 physical register used as stack ptr. 658193323Sed unsigned X86StackPtr; 659218893Sdim 660218893Sdim /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 661193323Sed /// floating point ops. 662193323Sed /// When SSE is available, use it for f32 operations. 663193323Sed /// When SSE2 is available, use it for f64 operations. 664193323Sed bool X86ScalarSSEf32; 665193323Sed bool X86ScalarSSEf64; 666193323Sed 667198892Srdivacky /// LegalFPImmediates - A list of legal fp immediates. 668198892Srdivacky std::vector<APFloat> LegalFPImmediates; 669198892Srdivacky 670198892Srdivacky /// addLegalFPImmediate - Indicate that this x86 target can instruction 671198892Srdivacky /// select the specified FP immediate natively. 672198892Srdivacky void addLegalFPImmediate(const APFloat& Imm) { 673198892Srdivacky LegalFPImmediates.push_back(Imm); 674198892Srdivacky } 675198892Srdivacky 676198090Srdivacky SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 677198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 678198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 679198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 680207618Srdivacky SmallVectorImpl<SDValue> &InVals) const; 681198090Srdivacky SDValue LowerMemArgument(SDValue Chain, 682198090Srdivacky CallingConv::ID CallConv, 683198090Srdivacky const SmallVectorImpl<ISD::InputArg> &ArgInfo, 684198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 685198090Srdivacky const CCValAssign &VA, MachineFrameInfo *MFI, 686207618Srdivacky unsigned i) const; 687198090Srdivacky SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 688198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 689198090Srdivacky const CCValAssign &VA, 690207618Srdivacky ISD::ArgFlagsTy Flags) const; 691193323Sed 692193323Sed // Call lowering helpers. 693203954Srdivacky 694203954Srdivacky /// IsEligibleForTailCallOptimization - Check whether the call is eligible 695203954Srdivacky /// for tail call optimization. Targets which want to do tail call 696203954Srdivacky /// optimization should implement this function. 697203954Srdivacky bool IsEligibleForTailCallOptimization(SDValue Callee, 698203954Srdivacky CallingConv::ID CalleeCC, 699203954Srdivacky bool isVarArg, 700205218Srdivacky bool isCalleeStructRet, 701205218Srdivacky bool isCallerStructRet, 702203954Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 703210299Sed const SmallVectorImpl<SDValue> &OutVals, 704203954Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 705203954Srdivacky SelectionDAG& DAG) const; 706207618Srdivacky bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const; 707193323Sed SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 708193323Sed SDValue Chain, bool IsTailCall, bool Is64Bit, 709207618Srdivacky int FPDiff, DebugLoc dl) const; 710193323Sed 711207618Srdivacky unsigned GetAlignedArgumentStackSize(unsigned StackSize, 712207618Srdivacky SelectionDAG &DAG) const; 713193323Sed 714193323Sed std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 715234353Sdim bool isSigned, 716234353Sdim bool isReplace) const; 717200581Srdivacky 718200581Srdivacky SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 719207618Srdivacky SelectionDAG &DAG) const; 720207618Srdivacky SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 721207618Srdivacky SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 722207618Srdivacky SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 723207618Srdivacky SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 724207618Srdivacky SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 725207618Srdivacky SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 726207618Srdivacky SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 727207618Srdivacky SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 728218893Sdim SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 729218893Sdim SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 730207618Srdivacky SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 731207618Srdivacky SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 732193323Sed SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 733193323Sed int64_t Offset, SelectionDAG &DAG) const; 734207618Srdivacky SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 735207618Srdivacky SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 736207618Srdivacky SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 737223017Sdim SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const; 738218893Sdim SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const; 739207618Srdivacky SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 740207618Srdivacky SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 741207618Srdivacky SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const; 742207618Srdivacky SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const; 743207618Srdivacky SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 744207618Srdivacky SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const; 745207618Srdivacky SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; 746207618Srdivacky SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const; 747207618Srdivacky SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 748223017Sdim SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const; 749207618Srdivacky SDValue LowerToBT(SDValue And, ISD::CondCode CC, 750207618Srdivacky DebugLoc dl, SelectionDAG &DAG) const; 751207618Srdivacky SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 752207618Srdivacky SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; 753207618Srdivacky SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 754207618Srdivacky SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 755207618Srdivacky SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const; 756207618Srdivacky SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 757207618Srdivacky SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 758207618Srdivacky SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 759207618Srdivacky SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 760207618Srdivacky SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 761207618Srdivacky SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 762207618Srdivacky SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 763207618Srdivacky SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 764207618Srdivacky SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const; 765207618Srdivacky SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 766226633Sdim SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 767226633Sdim SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 768207618Srdivacky SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 769207618Srdivacky SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const; 770234353Sdim SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) const; 771207618Srdivacky SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const; 772226633Sdim SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const; 773226633Sdim SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const; 774226633Sdim SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const; 775223017Sdim SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const; 776207618Srdivacky SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const; 777193323Sed 778207618Srdivacky SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 779207618Srdivacky SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 780207618Srdivacky SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const; 781212904Sdim SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const; 782226633Sdim SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const; 783224145Sdim SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 784234353Sdim SDValue PerformTruncateCombine(SDNode* N, SelectionDAG &DAG, DAGCombinerInfo &DCI) const; 785193323Sed 786212904Sdim // Utility functions to help LowerVECTOR_SHUFFLE 787212904Sdim SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const; 788234353Sdim SDValue LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const; 789234353Sdim SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const; 790212904Sdim 791198090Srdivacky virtual SDValue 792198090Srdivacky LowerFormalArguments(SDValue Chain, 793198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 794198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 795198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 796207618Srdivacky SmallVectorImpl<SDValue> &InVals) const; 797198090Srdivacky virtual SDValue 798234353Sdim LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, 799234353Sdim bool isVarArg, bool doesNotRet, bool &isTailCall, 800198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 801210299Sed const SmallVectorImpl<SDValue> &OutVals, 802198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 803198090Srdivacky DebugLoc dl, SelectionDAG &DAG, 804207618Srdivacky SmallVectorImpl<SDValue> &InVals) const; 805198090Srdivacky 806198090Srdivacky virtual SDValue 807198090Srdivacky LowerReturn(SDValue Chain, 808198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 809198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 810210299Sed const SmallVectorImpl<SDValue> &OutVals, 811207618Srdivacky DebugLoc dl, SelectionDAG &DAG) const; 812198090Srdivacky 813234353Sdim virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const; 814218893Sdim 815221345Sdim virtual bool mayBeEmittedAsTailCall(CallInst *CI) const; 816221345Sdim 817221345Sdim virtual EVT 818221345Sdim getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 819221345Sdim ISD::NodeType ExtendKind) const; 820221345Sdim 821199481Srdivacky virtual bool 822223017Sdim CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 823223017Sdim bool isVarArg, 824223017Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 825223017Sdim LLVMContext &Context) const; 826199481Srdivacky 827193323Sed void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results, 828207618Srdivacky SelectionDAG &DAG, unsigned NewOp) const; 829193323Sed 830198090Srdivacky /// Utility function to emit string processing sse4.2 instructions 831198090Srdivacky /// that return in xmm0. 832198090Srdivacky /// This takes the instruction to expand, the associated machine basic 833198090Srdivacky /// block, the number of args, and whether or not the second arg is 834198090Srdivacky /// in memory or not. 835198090Srdivacky MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, 836206274Srdivacky unsigned argNum, bool inMem) const; 837198090Srdivacky 838218893Sdim /// Utility functions to emit monitor and mwait instructions. These 839218893Sdim /// need to make sure that the arguments to the intrinsic are in the 840218893Sdim /// correct registers. 841218893Sdim MachineBasicBlock *EmitMonitor(MachineInstr *MI, 842218893Sdim MachineBasicBlock *BB) const; 843218893Sdim MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const; 844218893Sdim 845193323Sed /// Utility function to emit atomic bitwise operations (and, or, xor). 846198090Srdivacky /// It takes the bitwise instruction to expand, the associated machine basic 847198090Srdivacky /// block, and the associated X86 opcodes for reg/reg and reg/imm. 848193323Sed MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter( 849193323Sed MachineInstr *BInstr, 850193323Sed MachineBasicBlock *BB, 851193323Sed unsigned regOpc, 852193323Sed unsigned immOpc, 853193323Sed unsigned loadOpc, 854193323Sed unsigned cxchgOpc, 855193323Sed unsigned notOpc, 856193323Sed unsigned EAXreg, 857234353Sdim const TargetRegisterClass *RC, 858193323Sed bool invSrc = false) const; 859193323Sed 860193323Sed MachineBasicBlock *EmitAtomicBit6432WithCustomInserter( 861193323Sed MachineInstr *BInstr, 862193323Sed MachineBasicBlock *BB, 863193323Sed unsigned regOpcL, 864193323Sed unsigned regOpcH, 865193323Sed unsigned immOpcL, 866193323Sed unsigned immOpcH, 867193323Sed bool invSrc = false) const; 868218893Sdim 869193323Sed /// Utility function to emit atomic min and max. It takes the min/max 870193323Sed /// instruction to expand, the associated basic block, and the associated 871193323Sed /// cmov opcode for moving the min or max value. 872193323Sed MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, 873193323Sed MachineBasicBlock *BB, 874193323Sed unsigned cmovOpc) const; 875193323Sed 876218893Sdim // Utility function to emit the low-level va_arg code for X86-64. 877218893Sdim MachineBasicBlock *EmitVAARG64WithCustomInserter( 878218893Sdim MachineInstr *MI, 879218893Sdim MachineBasicBlock *MBB) const; 880218893Sdim 881198090Srdivacky /// Utility function to emit the xmm reg save portion of va_start. 882198090Srdivacky MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 883198090Srdivacky MachineInstr *BInstr, 884198090Srdivacky MachineBasicBlock *BB) const; 885198090Srdivacky 886198090Srdivacky MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 887207618Srdivacky MachineBasicBlock *BB) const; 888204961Srdivacky 889218893Sdim MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI, 890207618Srdivacky MachineBasicBlock *BB) const; 891218893Sdim 892226633Sdim MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI, 893226633Sdim MachineBasicBlock *BB, 894226633Sdim bool Is64Bit) const; 895226633Sdim 896210299Sed MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, 897210299Sed MachineBasicBlock *BB) const; 898204961Srdivacky 899218893Sdim MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI, 900218893Sdim MachineBasicBlock *BB) const; 901218893Sdim 902193323Sed /// Emit nodes that will be selected as "test Op0,Op0", or something 903193323Sed /// equivalent, for use with the given x86 condition code. 904207618Srdivacky SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const; 905193323Sed 906193323Sed /// Emit nodes that will be selected as "cmp Op0,Op1", or something 907193323Sed /// equivalent, for use with the given x86 condition code. 908193323Sed SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 909207618Srdivacky SelectionDAG &DAG) const; 910193323Sed }; 911193323Sed 912193323Sed namespace X86 { 913210299Sed FastISel *createFastISel(FunctionLoweringInfo &funcInfo); 914193323Sed } 915193323Sed} 916193323Sed 917193323Sed#endif // X86ISELLOWERING_H 918