X86ISelLowering.h revision 218893
1//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef X86ISELLOWERING_H 16#define X86ISELLOWERING_H 17 18#include "X86Subtarget.h" 19#include "X86RegisterInfo.h" 20#include "X86MachineFunctionInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetOptions.h" 23#include "llvm/CodeGen/FastISel.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/CallingConvLower.h" 26 27namespace llvm { 28 namespace X86ISD { 29 // X86 Specific DAG Nodes 30 enum NodeType { 31 // Start the numbering where the builtin ops leave off. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 /// BSF - Bit scan forward. 35 /// BSR - Bit scan reverse. 36 BSF, 37 BSR, 38 39 /// SHLD, SHRD - Double shift instructions. These correspond to 40 /// X86::SHLDxx and X86::SHRDxx instructions. 41 SHLD, 42 SHRD, 43 44 /// FAND - Bitwise logical AND of floating point values. This corresponds 45 /// to X86::ANDPS or X86::ANDPD. 46 FAND, 47 48 /// FOR - Bitwise logical OR of floating point values. This corresponds 49 /// to X86::ORPS or X86::ORPD. 50 FOR, 51 52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds 53 /// to X86::XORPS or X86::XORPD. 54 FXOR, 55 56 /// FSRL - Bitwise logical right shift of floating point values. These 57 /// corresponds to X86::PSRLDQ. 58 FSRL, 59 60 /// CALL - These operations represent an abstract X86 call 61 /// instruction, which includes a bunch of information. In particular the 62 /// operands of these node are: 63 /// 64 /// #0 - The incoming token chain 65 /// #1 - The callee 66 /// #2 - The number of arg bytes the caller pushes on the stack. 67 /// #3 - The number of arg bytes the callee pops off the stack. 68 /// #4 - The value to pass in AL/AX/EAX (optional) 69 /// #5 - The value to pass in DL/DX/EDX (optional) 70 /// 71 /// The result values of these nodes are: 72 /// 73 /// #0 - The outgoing token chain 74 /// #1 - The first register result value (optional) 75 /// #2 - The second register result value (optional) 76 /// 77 CALL, 78 79 /// RDTSC_DAG - This operation implements the lowering for 80 /// readcyclecounter 81 RDTSC_DAG, 82 83 /// X86 compare and logical compare instructions. 84 CMP, COMI, UCOMI, 85 86 /// X86 bit-test instructions. 87 BT, 88 89 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS 90 /// operand, usually produced by a CMP instruction. 91 SETCC, 92 93 // Same as SETCC except it's materialized with a sbb and the value is all 94 // one's or all zero's. 95 SETCC_CARRY, // R = carry_bit ? ~0 : 0 96 97 /// X86 conditional moves. Operand 0 and operand 1 are the two values 98 /// to select from. Operand 2 is the condition code, and operand 3 is the 99 /// flag operand produced by a CMP or TEST instruction. It also writes a 100 /// flag result. 101 CMOV, 102 103 /// X86 conditional branches. Operand 0 is the chain operand, operand 1 104 /// is the block to branch if condition is true, operand 2 is the 105 /// condition code, and operand 3 is the flag operand produced by a CMP 106 /// or TEST instruction. 107 BRCOND, 108 109 /// Return with a flag operand. Operand 0 is the chain operand, operand 110 /// 1 is the number of bytes of stack to pop. 111 RET_FLAG, 112 113 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 114 REP_STOS, 115 116 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 117 REP_MOVS, 118 119 /// GlobalBaseReg - On Darwin, this node represents the result of the popl 120 /// at function entry, used for PIC code. 121 GlobalBaseReg, 122 123 /// Wrapper - A wrapper node for TargetConstantPool, 124 /// TargetExternalSymbol, and TargetGlobalAddress. 125 Wrapper, 126 127 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 128 /// relative displacements. 129 WrapperRIP, 130 131 /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word 132 /// of an XMM vector, with the high word zero filled. 133 MOVQ2DQ, 134 135 /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector 136 /// to an MMX vector. If you think this is too close to the previous 137 /// mnemonic, so do I; blame Intel. 138 MOVDQ2Q, 139 140 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 141 /// i32, corresponds to X86::PEXTRB. 142 PEXTRB, 143 144 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 145 /// i32, corresponds to X86::PEXTRW. 146 PEXTRW, 147 148 /// INSERTPS - Insert any element of a 4 x float vector into any element 149 /// of a destination 4 x floatvector. 150 INSERTPS, 151 152 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 153 /// corresponds to X86::PINSRB. 154 PINSRB, 155 156 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 157 /// corresponds to X86::PINSRW. 158 PINSRW, MMX_PINSRW, 159 160 /// PSHUFB - Shuffle 16 8-bit values within a vector. 161 PSHUFB, 162 163 /// PANDN - and with not'd value. 164 PANDN, 165 166 /// PSIGNB/W/D - Copy integer sign. 167 PSIGNB, PSIGNW, PSIGND, 168 169 /// PBLENDVB - Variable blend 170 PBLENDVB, 171 172 /// FMAX, FMIN - Floating point max and min. 173 /// 174 FMAX, FMIN, 175 176 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 177 /// approximation. Note that these typically require refinement 178 /// in order to obtain suitable precision. 179 FRSQRT, FRCP, 180 181 // TLSADDR - Thread Local Storage. 182 TLSADDR, 183 184 // TLSCALL - Thread Local Storage. When calling to an OS provided 185 // thunk at the address from an earlier relocation. 186 TLSCALL, 187 188 // EH_RETURN - Exception Handling helpers. 189 EH_RETURN, 190 191 /// TC_RETURN - Tail call return. 192 /// operand #0 chain 193 /// operand #1 callee (register or absolute) 194 /// operand #2 stack adjustment 195 /// operand #3 optional in flag 196 TC_RETURN, 197 198 // VZEXT_MOVL - Vector move low and zero extend. 199 VZEXT_MOVL, 200 201 // VSHL, VSRL - Vector logical left / right shift. 202 VSHL, VSRL, 203 204 // CMPPD, CMPPS - Vector double/float comparison. 205 // CMPPD, CMPPS - Vector double/float comparison. 206 CMPPD, CMPPS, 207 208 // PCMP* - Vector integer comparisons. 209 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ, 210 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ, 211 212 // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results. 213 ADD, SUB, ADC, SBB, SMUL, 214 INC, DEC, OR, XOR, AND, 215 216 UMUL, // LOW, HI, FLAGS = umul LHS, RHS 217 218 // MUL_IMM - X86 specific multiply by immediate. 219 MUL_IMM, 220 221 // PTEST - Vector bitwise comparisons 222 PTEST, 223 224 // TESTP - Vector packed fp sign bitwise comparisons 225 TESTP, 226 227 // Several flavors of instructions with vector shuffle behaviors. 228 PALIGN, 229 PSHUFD, 230 PSHUFHW, 231 PSHUFLW, 232 PSHUFHW_LD, 233 PSHUFLW_LD, 234 SHUFPD, 235 SHUFPS, 236 MOVDDUP, 237 MOVSHDUP, 238 MOVSLDUP, 239 MOVSHDUP_LD, 240 MOVSLDUP_LD, 241 MOVLHPS, 242 MOVLHPD, 243 MOVHLPS, 244 MOVHLPD, 245 MOVLPS, 246 MOVLPD, 247 MOVSD, 248 MOVSS, 249 UNPCKLPS, 250 UNPCKLPD, 251 UNPCKHPS, 252 UNPCKHPD, 253 PUNPCKLBW, 254 PUNPCKLWD, 255 PUNPCKLDQ, 256 PUNPCKLQDQ, 257 PUNPCKHBW, 258 PUNPCKHWD, 259 PUNPCKHDQ, 260 PUNPCKHQDQ, 261 262 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 263 // according to %al. An operator is needed so that this can be expanded 264 // with control flow. 265 VASTART_SAVE_XMM_REGS, 266 267 // WIN_ALLOCA - Windows's _chkstk call to do stack probing. 268 WIN_ALLOCA, 269 270 // Memory barrier 271 MEMBARRIER, 272 MFENCE, 273 SFENCE, 274 LFENCE, 275 276 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 277 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 278 // Atomic 64-bit binary operations. 279 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 280 ATOMSUB64_DAG, 281 ATOMOR64_DAG, 282 ATOMXOR64_DAG, 283 ATOMAND64_DAG, 284 ATOMNAND64_DAG, 285 ATOMSWAP64_DAG, 286 287 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap. 288 LCMPXCHG_DAG, 289 LCMPXCHG8_DAG, 290 291 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 292 VZEXT_LOAD, 293 294 // FNSTCW16m - Store FP control world into i16 memory. 295 FNSTCW16m, 296 297 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 298 /// integer destination in memory and a FP reg source. This corresponds 299 /// to the X86::FIST*m instructions and the rounding mode change stuff. It 300 /// has two inputs (token chain and address) and two outputs (int value 301 /// and token chain). 302 FP_TO_INT16_IN_MEM, 303 FP_TO_INT32_IN_MEM, 304 FP_TO_INT64_IN_MEM, 305 306 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 307 /// integer source in memory and FP reg result. This corresponds to the 308 /// X86::FILD*m instructions. It has three inputs (token chain, address, 309 /// and source type) and two outputs (FP value and token chain). FILD_FLAG 310 /// also produces a flag). 311 FILD, 312 FILD_FLAG, 313 314 /// FLD - This instruction implements an extending load to FP stack slots. 315 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 316 /// operand, ptr to load from, and a ValueType node indicating the type 317 /// to load to. 318 FLD, 319 320 /// FST - This instruction implements a truncating store to FP stack 321 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 322 /// chain operand, value to store, address, and a ValueType to store it 323 /// as. 324 FST, 325 326 /// VAARG_64 - This instruction grabs the address of the next argument 327 /// from a va_list. (reads and modifies the va_list in memory) 328 VAARG_64 329 330 // WARNING: Do not add anything in the end unless you want the node to 331 // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be 332 // thought as target memory ops! 333 }; 334 } 335 336 /// Define some predicates that are used for node matching. 337 namespace X86 { 338 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 339 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 340 bool isPSHUFDMask(ShuffleVectorSDNode *N); 341 342 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 343 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 344 bool isPSHUFHWMask(ShuffleVectorSDNode *N); 345 346 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 347 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 348 bool isPSHUFLWMask(ShuffleVectorSDNode *N); 349 350 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 351 /// specifies a shuffle of elements that is suitable for input to SHUFP*. 352 bool isSHUFPMask(ShuffleVectorSDNode *N); 353 354 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 355 /// specifies a shuffle of elements that is suitable for input to MOVHLPS. 356 bool isMOVHLPSMask(ShuffleVectorSDNode *N); 357 358 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 359 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 360 /// <2, 3, 2, 3> 361 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N); 362 363 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 364 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}. 365 bool isMOVLPMask(ShuffleVectorSDNode *N); 366 367 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 368 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}. 369 /// as well as MOVLHPS. 370 bool isMOVLHPSMask(ShuffleVectorSDNode *N); 371 372 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 373 /// specifies a shuffle of elements that is suitable for input to UNPCKL. 374 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 375 376 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 377 /// specifies a shuffle of elements that is suitable for input to UNPCKH. 378 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 379 380 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 381 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 382 /// <0, 0, 1, 1> 383 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N); 384 385 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 386 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 387 /// <2, 2, 3, 3> 388 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N); 389 390 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 391 /// specifies a shuffle of elements that is suitable for input to MOVSS, 392 /// MOVSD, and MOVD, i.e. setting the lowest element. 393 bool isMOVLMask(ShuffleVectorSDNode *N); 394 395 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 396 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 397 bool isMOVSHDUPMask(ShuffleVectorSDNode *N); 398 399 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 400 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 401 bool isMOVSLDUPMask(ShuffleVectorSDNode *N); 402 403 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 404 /// specifies a shuffle of elements that is suitable for input to MOVDDUP. 405 bool isMOVDDUPMask(ShuffleVectorSDNode *N); 406 407 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand 408 /// specifies a shuffle of elements that is suitable for input to PALIGNR. 409 bool isPALIGNRMask(ShuffleVectorSDNode *N); 410 411 /// isVEXTRACTF128Index - Return true if the specified 412 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is 413 /// suitable for input to VEXTRACTF128. 414 bool isVEXTRACTF128Index(SDNode *N); 415 416 /// isVINSERTF128Index - Return true if the specified 417 /// INSERT_SUBVECTOR operand specifies a subvector insert that is 418 /// suitable for input to VINSERTF128. 419 bool isVINSERTF128Index(SDNode *N); 420 421 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 422 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 423 /// instructions. 424 unsigned getShuffleSHUFImmediate(SDNode *N); 425 426 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 427 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction. 428 unsigned getShufflePSHUFHWImmediate(SDNode *N); 429 430 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 431 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction. 432 unsigned getShufflePSHUFLWImmediate(SDNode *N); 433 434 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 435 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 436 unsigned getShufflePALIGNRImmediate(SDNode *N); 437 438 /// getExtractVEXTRACTF128Immediate - Return the appropriate 439 /// immediate to extract the specified EXTRACT_SUBVECTOR index 440 /// with VEXTRACTF128 instructions. 441 unsigned getExtractVEXTRACTF128Immediate(SDNode *N); 442 443 /// getInsertVINSERTF128Immediate - Return the appropriate 444 /// immediate to insert at the specified INSERT_SUBVECTOR index 445 /// with VINSERTF128 instructions. 446 unsigned getInsertVINSERTF128Immediate(SDNode *N); 447 448 /// isZeroNode - Returns true if Elt is a constant zero or a floating point 449 /// constant +0.0. 450 bool isZeroNode(SDValue Elt); 451 452 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 453 /// fit into displacement field of the instruction. 454 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 455 bool hasSymbolicDisplacement = true); 456 } 457 458 //===--------------------------------------------------------------------===// 459 // X86TargetLowering - X86 Implementation of the TargetLowering interface 460 class X86TargetLowering : public TargetLowering { 461 public: 462 explicit X86TargetLowering(X86TargetMachine &TM); 463 464 virtual unsigned getJumpTableEncoding() const; 465 466 virtual const MCExpr * 467 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 468 const MachineBasicBlock *MBB, unsigned uid, 469 MCContext &Ctx) const; 470 471 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 472 /// jumptable. 473 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 474 SelectionDAG &DAG) const; 475 virtual const MCExpr * 476 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 477 unsigned JTI, MCContext &Ctx) const; 478 479 /// getStackPtrReg - Return the stack pointer register we are using: either 480 /// ESP or RSP. 481 unsigned getStackPtrReg() const { return X86StackPtr; } 482 483 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 484 /// function arguments in the caller parameter area. For X86, aggregates 485 /// that contains are placed at 16-byte boundaries while the rest are at 486 /// 4-byte boundaries. 487 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 488 489 /// getOptimalMemOpType - Returns the target specific optimal type for load 490 /// and store operations as a result of memset, memcpy, and memmove 491 /// lowering. If DstAlign is zero that means it's safe to destination 492 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 493 /// means there isn't a need to check it against alignment requirement, 494 /// probably because the source does not need to be loaded. If 495 /// 'NonScalarIntSafe' is true, that means it's safe to return a 496 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 497 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 498 /// constant so it does not need to be loaded. 499 /// It returns EVT::Other if the type should be determined using generic 500 /// target-independent logic. 501 virtual EVT 502 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 503 bool NonScalarIntSafe, bool MemcpyStrSrc, 504 MachineFunction &MF) const; 505 506 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 507 /// unaligned memory accesses. of the specified type. 508 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 509 return true; 510 } 511 512 /// LowerOperation - Provide custom lowering hooks for some operations. 513 /// 514 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 515 516 /// ReplaceNodeResults - Replace the results of node with an illegal result 517 /// type with new values built out of custom code. 518 /// 519 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 520 SelectionDAG &DAG) const; 521 522 523 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 524 525 /// isTypeDesirableForOp - Return true if the target has native support for 526 /// the specified value type and it is 'desirable' to use the type for the 527 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 528 /// instruction encodings are longer and some i16 instructions are slow. 529 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const; 530 531 /// isTypeDesirable - Return true if the target has native support for the 532 /// specified value type and it is 'desirable' to use the type. e.g. On x86 533 /// i16 is legal, but undesirable since i16 instruction encodings are longer 534 /// and some i16 instructions are slow. 535 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const; 536 537 virtual MachineBasicBlock * 538 EmitInstrWithCustomInserter(MachineInstr *MI, 539 MachineBasicBlock *MBB) const; 540 541 542 /// getTargetNodeName - This method returns the name of a target specific 543 /// DAG node. 544 virtual const char *getTargetNodeName(unsigned Opcode) const; 545 546 /// getSetCCResultType - Return the ISD::SETCC ValueType 547 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; 548 549 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 550 /// in Mask are known to be either zero or one and return them in the 551 /// KnownZero/KnownOne bitsets. 552 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 553 const APInt &Mask, 554 APInt &KnownZero, 555 APInt &KnownOne, 556 const SelectionDAG &DAG, 557 unsigned Depth = 0) const; 558 559 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the 560 // operation that are sign bits. 561 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 562 unsigned Depth) const; 563 564 virtual bool 565 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 566 567 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 568 569 virtual bool ExpandInlineAsm(CallInst *CI) const; 570 571 ConstraintType getConstraintType(const std::string &Constraint) const; 572 573 /// Examine constraint string and operand type and determine a weight value. 574 /// The operand object must already have been set up with the operand type. 575 virtual ConstraintWeight getSingleConstraintMatchWeight( 576 AsmOperandInfo &info, const char *constraint) const; 577 578 std::vector<unsigned> 579 getRegClassForInlineAsmConstraint(const std::string &Constraint, 580 EVT VT) const; 581 582 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 583 584 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 585 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 586 /// true it means one of the asm constraint of the inline asm instruction 587 /// being processed is 'm'. 588 virtual void LowerAsmOperandForConstraint(SDValue Op, 589 char ConstraintLetter, 590 std::vector<SDValue> &Ops, 591 SelectionDAG &DAG) const; 592 593 /// getRegForInlineAsmConstraint - Given a physical register constraint 594 /// (e.g. {edx}), return the register number and the register class for the 595 /// register. This should only be used for C_Register constraints. On 596 /// error, this returns a register number of 0. 597 std::pair<unsigned, const TargetRegisterClass*> 598 getRegForInlineAsmConstraint(const std::string &Constraint, 599 EVT VT) const; 600 601 /// isLegalAddressingMode - Return true if the addressing mode represented 602 /// by AM is legal for this target, for a load/store of the specified type. 603 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 604 605 /// isTruncateFree - Return true if it's free to truncate a value of 606 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 607 /// register EAX to i16 by referencing its sub-register AX. 608 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const; 609 virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 610 611 /// isZExtFree - Return true if any actual instruction that defines a 612 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 613 /// register. This does not necessarily include registers defined in 614 /// unknown ways, such as incoming arguments, or copies from unknown 615 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 616 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 617 /// all instructions that define 32-bit values implicit zero-extend the 618 /// result out to 64 bits. 619 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const; 620 virtual bool isZExtFree(EVT VT1, EVT VT2) const; 621 622 /// isNarrowingProfitable - Return true if it's profitable to narrow 623 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 624 /// from i32 to i8 but not from i32 to i16. 625 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 626 627 /// isFPImmLegal - Returns true if the target can instruction select the 628 /// specified FP immediate natively. If false, the legalizer will 629 /// materialize the FP immediate as a load from a constant pool. 630 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 631 632 /// isShuffleMaskLegal - Targets can use this to indicate that they only 633 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 634 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 635 /// values are assumed to be legal. 636 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 637 EVT VT) const; 638 639 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 640 /// used by Targets can use this to indicate if there is a suitable 641 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 642 /// pool entry. 643 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 644 EVT VT) const; 645 646 /// ShouldShrinkFPConstant - If true, then instruction selection should 647 /// seek to shrink the FP constant of the specified type to a smaller type 648 /// in order to save space and / or reduce runtime. 649 virtual bool ShouldShrinkFPConstant(EVT VT) const { 650 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 651 // expensive than a straight movsd. On the other hand, it's important to 652 // shrink long double fp constant since fldt is very slow. 653 return !X86ScalarSSEf64 || VT == MVT::f80; 654 } 655 656 const X86Subtarget* getSubtarget() const { 657 return Subtarget; 658 } 659 660 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 661 /// computed in an SSE register, not on the X87 floating point stack. 662 bool isScalarFPTypeInSSEReg(EVT VT) const { 663 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 664 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 665 } 666 667 /// createFastISel - This method returns a target specific FastISel object, 668 /// or null if the target does not support "fast" ISel. 669 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const; 670 671 /// getFunctionAlignment - Return the Log2 alignment of this function. 672 virtual unsigned getFunctionAlignment(const Function *F) const; 673 674 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 675 MachineFunction &MF) const; 676 677 /// getStackCookieLocation - Return true if the target stores stack 678 /// protector cookies at a fixed offset in some non-standard address 679 /// space, and populates the address space and offset as 680 /// appropriate. 681 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const; 682 683 protected: 684 std::pair<const TargetRegisterClass*, uint8_t> 685 findRepresentativeClass(EVT VT) const; 686 687 private: 688 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 689 /// make the right decision when generating code for different targets. 690 const X86Subtarget *Subtarget; 691 const X86RegisterInfo *RegInfo; 692 const TargetData *TD; 693 694 /// X86StackPtr - X86 physical register used as stack ptr. 695 unsigned X86StackPtr; 696 697 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 698 /// floating point ops. 699 /// When SSE is available, use it for f32 operations. 700 /// When SSE2 is available, use it for f64 operations. 701 bool X86ScalarSSEf32; 702 bool X86ScalarSSEf64; 703 704 /// LegalFPImmediates - A list of legal fp immediates. 705 std::vector<APFloat> LegalFPImmediates; 706 707 /// addLegalFPImmediate - Indicate that this x86 target can instruction 708 /// select the specified FP immediate natively. 709 void addLegalFPImmediate(const APFloat& Imm) { 710 LegalFPImmediates.push_back(Imm); 711 } 712 713 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 714 CallingConv::ID CallConv, bool isVarArg, 715 const SmallVectorImpl<ISD::InputArg> &Ins, 716 DebugLoc dl, SelectionDAG &DAG, 717 SmallVectorImpl<SDValue> &InVals) const; 718 SDValue LowerMemArgument(SDValue Chain, 719 CallingConv::ID CallConv, 720 const SmallVectorImpl<ISD::InputArg> &ArgInfo, 721 DebugLoc dl, SelectionDAG &DAG, 722 const CCValAssign &VA, MachineFrameInfo *MFI, 723 unsigned i) const; 724 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 725 DebugLoc dl, SelectionDAG &DAG, 726 const CCValAssign &VA, 727 ISD::ArgFlagsTy Flags) const; 728 729 // Call lowering helpers. 730 731 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 732 /// for tail call optimization. Targets which want to do tail call 733 /// optimization should implement this function. 734 bool IsEligibleForTailCallOptimization(SDValue Callee, 735 CallingConv::ID CalleeCC, 736 bool isVarArg, 737 bool isCalleeStructRet, 738 bool isCallerStructRet, 739 const SmallVectorImpl<ISD::OutputArg> &Outs, 740 const SmallVectorImpl<SDValue> &OutVals, 741 const SmallVectorImpl<ISD::InputArg> &Ins, 742 SelectionDAG& DAG) const; 743 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const; 744 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 745 SDValue Chain, bool IsTailCall, bool Is64Bit, 746 int FPDiff, DebugLoc dl) const; 747 748 unsigned GetAlignedArgumentStackSize(unsigned StackSize, 749 SelectionDAG &DAG) const; 750 751 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 752 bool isSigned) const; 753 754 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 755 SelectionDAG &DAG) const; 756 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 757 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 758 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 759 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 760 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 761 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 762 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const; 763 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const; 764 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 765 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const; 766 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 767 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 768 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 769 int64_t Offset, SelectionDAG &DAG) const; 770 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 771 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 772 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 773 SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const; 774 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 775 SelectionDAG &DAG) const; 776 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const; 777 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 778 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 779 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const; 780 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const; 781 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 782 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const; 783 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; 784 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const; 785 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 786 SDValue LowerToBT(SDValue And, ISD::CondCode CC, 787 DebugLoc dl, SelectionDAG &DAG) const; 788 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 789 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const; 790 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 791 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 792 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const; 793 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 794 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 795 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 796 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 797 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 798 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 799 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 800 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 801 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const; 802 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 803 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 804 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 805 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const; 806 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const; 807 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const; 808 SDValue LowerSHL(SDValue Op, SelectionDAG &DAG) const; 809 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const; 810 811 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 812 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const; 813 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const; 814 SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const; 815 816 // Utility functions to help LowerVECTOR_SHUFFLE 817 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const; 818 819 virtual SDValue 820 LowerFormalArguments(SDValue Chain, 821 CallingConv::ID CallConv, bool isVarArg, 822 const SmallVectorImpl<ISD::InputArg> &Ins, 823 DebugLoc dl, SelectionDAG &DAG, 824 SmallVectorImpl<SDValue> &InVals) const; 825 virtual SDValue 826 LowerCall(SDValue Chain, SDValue Callee, 827 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 828 const SmallVectorImpl<ISD::OutputArg> &Outs, 829 const SmallVectorImpl<SDValue> &OutVals, 830 const SmallVectorImpl<ISD::InputArg> &Ins, 831 DebugLoc dl, SelectionDAG &DAG, 832 SmallVectorImpl<SDValue> &InVals) const; 833 834 virtual SDValue 835 LowerReturn(SDValue Chain, 836 CallingConv::ID CallConv, bool isVarArg, 837 const SmallVectorImpl<ISD::OutputArg> &Outs, 838 const SmallVectorImpl<SDValue> &OutVals, 839 DebugLoc dl, SelectionDAG &DAG) const; 840 841 virtual bool isUsedByReturnOnly(SDNode *N) const; 842 843 virtual bool 844 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 845 const SmallVectorImpl<ISD::OutputArg> &Outs, 846 LLVMContext &Context) const; 847 848 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results, 849 SelectionDAG &DAG, unsigned NewOp) const; 850 851 /// Utility function to emit string processing sse4.2 instructions 852 /// that return in xmm0. 853 /// This takes the instruction to expand, the associated machine basic 854 /// block, the number of args, and whether or not the second arg is 855 /// in memory or not. 856 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, 857 unsigned argNum, bool inMem) const; 858 859 /// Utility functions to emit monitor and mwait instructions. These 860 /// need to make sure that the arguments to the intrinsic are in the 861 /// correct registers. 862 MachineBasicBlock *EmitMonitor(MachineInstr *MI, 863 MachineBasicBlock *BB) const; 864 MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const; 865 866 /// Utility function to emit atomic bitwise operations (and, or, xor). 867 /// It takes the bitwise instruction to expand, the associated machine basic 868 /// block, and the associated X86 opcodes for reg/reg and reg/imm. 869 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter( 870 MachineInstr *BInstr, 871 MachineBasicBlock *BB, 872 unsigned regOpc, 873 unsigned immOpc, 874 unsigned loadOpc, 875 unsigned cxchgOpc, 876 unsigned notOpc, 877 unsigned EAXreg, 878 TargetRegisterClass *RC, 879 bool invSrc = false) const; 880 881 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter( 882 MachineInstr *BInstr, 883 MachineBasicBlock *BB, 884 unsigned regOpcL, 885 unsigned regOpcH, 886 unsigned immOpcL, 887 unsigned immOpcH, 888 bool invSrc = false) const; 889 890 /// Utility function to emit atomic min and max. It takes the min/max 891 /// instruction to expand, the associated basic block, and the associated 892 /// cmov opcode for moving the min or max value. 893 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, 894 MachineBasicBlock *BB, 895 unsigned cmovOpc) const; 896 897 // Utility function to emit the low-level va_arg code for X86-64. 898 MachineBasicBlock *EmitVAARG64WithCustomInserter( 899 MachineInstr *MI, 900 MachineBasicBlock *MBB) const; 901 902 /// Utility function to emit the xmm reg save portion of va_start. 903 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 904 MachineInstr *BInstr, 905 MachineBasicBlock *BB) const; 906 907 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 908 MachineBasicBlock *BB) const; 909 910 MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI, 911 MachineBasicBlock *BB) const; 912 913 MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, 914 MachineBasicBlock *BB) const; 915 916 MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI, 917 MachineBasicBlock *BB) const; 918 919 /// Emit nodes that will be selected as "test Op0,Op0", or something 920 /// equivalent, for use with the given x86 condition code. 921 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const; 922 923 /// Emit nodes that will be selected as "cmp Op0,Op1", or something 924 /// equivalent, for use with the given x86 condition code. 925 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 926 SelectionDAG &DAG) const; 927 }; 928 929 namespace X86 { 930 FastISel *createFastISel(FunctionLoweringInfo &funcInfo); 931 } 932} 933 934#endif // X86ISELLOWERING_H 935