X86ISelLowering.h revision 204961
159243Sobrien//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 259243Sobrien// 359243Sobrien// The LLVM Compiler Infrastructure 459243Sobrien// 559243Sobrien// This file is distributed under the University of Illinois Open Source 659243Sobrien// License. See LICENSE.TXT for details. 759243Sobrien// 859243Sobrien//===----------------------------------------------------------------------===// 959243Sobrien// 1059243Sobrien// This file defines the interfaces that X86 uses to lower LLVM code into a 1159243Sobrien// selection DAG. 1259243Sobrien// 1359243Sobrien//===----------------------------------------------------------------------===// 1459243Sobrien 1559243Sobrien#ifndef X86ISELLOWERING_H 1659243Sobrien#define X86ISELLOWERING_H 1759243Sobrien 1859243Sobrien#include "X86Subtarget.h" 1959243Sobrien#include "X86RegisterInfo.h" 2059243Sobrien#include "X86MachineFunctionInfo.h" 2159243Sobrien#include "llvm/Target/TargetLowering.h" 2259243Sobrien#include "llvm/Target/TargetOptions.h" 2359243Sobrien#include "llvm/CodeGen/FastISel.h" 2459243Sobrien#include "llvm/CodeGen/SelectionDAG.h" 2559243Sobrien#include "llvm/CodeGen/CallingConvLower.h" 2659243Sobrien 2759243Sobriennamespace llvm { 2859243Sobrien namespace X86ISD { 2959243Sobrien // X86 Specific DAG Nodes 3059243Sobrien enum NodeType { 3159243Sobrien // Start the numbering where the builtin ops leave off. 3259243Sobrien FIRST_NUMBER = ISD::BUILTIN_OP_END, 3359243Sobrien 3459243Sobrien /// BSF - Bit scan forward. 3559243Sobrien /// BSR - Bit scan reverse. 3659243Sobrien BSF, 3759243Sobrien BSR, 3859243Sobrien 3959243Sobrien /// SHLD, SHRD - Double shift instructions. These correspond to 4059243Sobrien /// X86::SHLDxx and X86::SHRDxx instructions. 4159243Sobrien SHLD, 4259243Sobrien SHRD, 4359243Sobrien 4459243Sobrien /// FAND - Bitwise logical AND of floating point values. This corresponds 4559243Sobrien /// to X86::ANDPS or X86::ANDPD. 4659243Sobrien FAND, 4759243Sobrien 4859243Sobrien /// FOR - Bitwise logical OR of floating point values. This corresponds 4959243Sobrien /// to X86::ORPS or X86::ORPD. 5059243Sobrien FOR, 5159243Sobrien 5259243Sobrien /// FXOR - Bitwise logical XOR of floating point values. This corresponds 5359243Sobrien /// to X86::XORPS or X86::XORPD. 5459243Sobrien FXOR, 5559243Sobrien 5659243Sobrien /// FSRL - Bitwise logical right shift of floating point values. These 5759243Sobrien /// corresponds to X86::PSRLDQ. 5859243Sobrien FSRL, 5959243Sobrien 6059243Sobrien /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 6159243Sobrien /// integer source in memory and FP reg result. This corresponds to the 6259243Sobrien /// X86::FILD*m instructions. It has three inputs (token chain, address, 6359243Sobrien /// and source type) and two outputs (FP value and token chain). FILD_FLAG 6459243Sobrien /// also produces a flag). 6559243Sobrien FILD, 6659243Sobrien FILD_FLAG, 6759243Sobrien 6859243Sobrien /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 6959243Sobrien /// integer destination in memory and a FP reg source. This corresponds 7059243Sobrien /// to the X86::FIST*m instructions and the rounding mode change stuff. It 7159243Sobrien /// has two inputs (token chain and address) and two outputs (int value 7259243Sobrien /// and token chain). 7359243Sobrien FP_TO_INT16_IN_MEM, 7459243Sobrien FP_TO_INT32_IN_MEM, 7559243Sobrien FP_TO_INT64_IN_MEM, 7659243Sobrien 7759243Sobrien /// FLD - This instruction implements an extending load to FP stack slots. 7859243Sobrien /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 7959243Sobrien /// operand, ptr to load from, and a ValueType node indicating the type 8059243Sobrien /// to load to. 8159243Sobrien FLD, 8259243Sobrien 8359243Sobrien /// FST - This instruction implements a truncating store to FP stack 8459243Sobrien /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 8559243Sobrien /// chain operand, value to store, address, and a ValueType to store it 8659243Sobrien /// as. 8759243Sobrien FST, 8859243Sobrien 8959243Sobrien /// CALL - These operations represent an abstract X86 call 9059243Sobrien /// instruction, which includes a bunch of information. In particular the 9159243Sobrien /// operands of these node are: 9259243Sobrien /// 9359243Sobrien /// #0 - The incoming token chain 9459243Sobrien /// #1 - The callee 9559243Sobrien /// #2 - The number of arg bytes the caller pushes on the stack. 9659243Sobrien /// #3 - The number of arg bytes the callee pops off the stack. 9759243Sobrien /// #4 - The value to pass in AL/AX/EAX (optional) 9859243Sobrien /// #5 - The value to pass in DL/DX/EDX (optional) 9959243Sobrien /// 10059243Sobrien /// The result values of these nodes are: 10159243Sobrien /// 10259243Sobrien /// #0 - The outgoing token chain 10359243Sobrien /// #1 - The first register result value (optional) 10459243Sobrien /// #2 - The second register result value (optional) 10559243Sobrien /// 10659243Sobrien CALL, 10759243Sobrien 10859243Sobrien /// RDTSC_DAG - This operation implements the lowering for 10959243Sobrien /// readcyclecounter 11059243Sobrien RDTSC_DAG, 11159243Sobrien 11259243Sobrien /// X86 compare and logical compare instructions. 11359243Sobrien CMP, COMI, UCOMI, 11459243Sobrien 11559243Sobrien /// X86 bit-test instructions. 11659243Sobrien BT, 11759243Sobrien 11859243Sobrien /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag 11959243Sobrien /// operand produced by a CMP instruction. 12059243Sobrien SETCC, 12159243Sobrien 12259243Sobrien // Same as SETCC except it's materialized with a sbb and the value is all 12359243Sobrien // one's or all zero's. 12459243Sobrien SETCC_CARRY, 12559243Sobrien 12659243Sobrien /// X86 conditional moves. Operand 0 and operand 1 are the two values 12759243Sobrien /// to select from. Operand 2 is the condition code, and operand 3 is the 12859243Sobrien /// flag operand produced by a CMP or TEST instruction. It also writes a 12959243Sobrien /// flag result. 13059243Sobrien CMOV, 13159243Sobrien 13259243Sobrien /// X86 conditional branches. Operand 0 is the chain operand, operand 1 13359243Sobrien /// is the block to branch if condition is true, operand 2 is the 13459243Sobrien /// condition code, and operand 3 is the flag operand produced by a CMP 13559243Sobrien /// or TEST instruction. 13659243Sobrien BRCOND, 13759243Sobrien 13859243Sobrien /// Return with a flag operand. Operand 0 is the chain operand, operand 13959243Sobrien /// 1 is the number of bytes of stack to pop. 14059243Sobrien RET_FLAG, 14159243Sobrien 14259243Sobrien /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 14359243Sobrien REP_STOS, 14459243Sobrien 14559243Sobrien /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 14659243Sobrien REP_MOVS, 14759243Sobrien 14859243Sobrien /// GlobalBaseReg - On Darwin, this node represents the result of the popl 14959243Sobrien /// at function entry, used for PIC code. 15059243Sobrien GlobalBaseReg, 15159243Sobrien 15259243Sobrien /// Wrapper - A wrapper node for TargetConstantPool, 15359243Sobrien /// TargetExternalSymbol, and TargetGlobalAddress. 15459243Sobrien Wrapper, 15559243Sobrien 15659243Sobrien /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 15759243Sobrien /// relative displacements. 15859243Sobrien WrapperRIP, 15959243Sobrien 16059243Sobrien /// MOVQ2DQ - Copies a 64-bit value from a vector to another vector. 16159415Sobrien /// Can be used to move a vector value from a MMX register to a XMM 16259415Sobrien /// register. 16359415Sobrien MOVQ2DQ, 16459415Sobrien 16559415Sobrien /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 16659415Sobrien /// i32, corresponds to X86::PEXTRB. 16759243Sobrien PEXTRB, 16859243Sobrien 16959243Sobrien /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 17059243Sobrien /// i32, corresponds to X86::PEXTRW. 17159243Sobrien PEXTRW, 17259243Sobrien 17359243Sobrien /// INSERTPS - Insert any element of a 4 x float vector into any element 17459243Sobrien /// of a destination 4 x floatvector. 17559243Sobrien INSERTPS, 17659243Sobrien 17759243Sobrien /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 17859243Sobrien /// corresponds to X86::PINSRB. 17959243Sobrien PINSRB, 18059243Sobrien 18159243Sobrien /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 18259243Sobrien /// corresponds to X86::PINSRW. 18359243Sobrien PINSRW, MMX_PINSRW, 18459243Sobrien 18559243Sobrien /// PSHUFB - Shuffle 16 8-bit values within a vector. 18659243Sobrien PSHUFB, 18759243Sobrien 18859243Sobrien /// FMAX, FMIN - Floating point max and min. 18959243Sobrien /// 19059243Sobrien FMAX, FMIN, 19159243Sobrien 19259243Sobrien /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 19359243Sobrien /// approximation. Note that these typically require refinement 19459243Sobrien /// in order to obtain suitable precision. 19559243Sobrien FRSQRT, FRCP, 19659243Sobrien 19759243Sobrien // TLSADDR - Thread Local Storage. 19859243Sobrien TLSADDR, 19959243Sobrien 20059243Sobrien // SegmentBaseAddress - The address segment:0 20159243Sobrien SegmentBaseAddress, 20259243Sobrien 20359243Sobrien // EH_RETURN - Exception Handling helpers. 20459243Sobrien EH_RETURN, 20559243Sobrien 20659243Sobrien /// TC_RETURN - Tail call return. 20759243Sobrien /// operand #0 chain 20859243Sobrien /// operand #1 callee (register or absolute) 20959243Sobrien /// operand #2 stack adjustment 21059243Sobrien /// operand #3 optional in flag 21159243Sobrien TC_RETURN, 21259243Sobrien 21359243Sobrien // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap. 21459243Sobrien LCMPXCHG_DAG, 21559243Sobrien LCMPXCHG8_DAG, 21659243Sobrien 21759243Sobrien // FNSTCW16m - Store FP control world into i16 memory. 21859243Sobrien FNSTCW16m, 21959243Sobrien 22059243Sobrien // VZEXT_MOVL - Vector move low and zero extend. 22159243Sobrien VZEXT_MOVL, 22259243Sobrien 22359243Sobrien // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 22459243Sobrien VZEXT_LOAD, 22559243Sobrien 22659243Sobrien // VSHL, VSRL - Vector logical left / right shift. 22759243Sobrien VSHL, VSRL, 22859243Sobrien 22959243Sobrien // CMPPD, CMPPS - Vector double/float comparison. 23059243Sobrien // CMPPD, CMPPS - Vector double/float comparison. 23159243Sobrien CMPPD, CMPPS, 23259243Sobrien 23359243Sobrien // PCMP* - Vector integer comparisons. 23459243Sobrien PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ, 23559243Sobrien PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ, 23659243Sobrien 23759243Sobrien // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results. 23859243Sobrien ADD, SUB, SMUL, UMUL, 23959243Sobrien INC, DEC, OR, XOR, AND, 24059243Sobrien 24159243Sobrien // MUL_IMM - X86 specific multiply by immediate. 24259243Sobrien MUL_IMM, 24359243Sobrien 24459243Sobrien // PTEST - Vector bitwise comparisons 24559243Sobrien PTEST, 24659243Sobrien 24759243Sobrien // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 24859243Sobrien // according to %al. An operator is needed so that this can be expanded 24959243Sobrien // with control flow. 25059243Sobrien VASTART_SAVE_XMM_REGS, 25159243Sobrien 25259243Sobrien // MINGW_ALLOCA - MingW's __alloca call to do stack probing. 25359243Sobrien MINGW_ALLOCA, 25459243Sobrien 25559243Sobrien // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 25659243Sobrien // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 25759243Sobrien // Atomic 64-bit binary operations. 25859243Sobrien ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 25959243Sobrien ATOMSUB64_DAG, 26059243Sobrien ATOMOR64_DAG, 26159243Sobrien ATOMXOR64_DAG, 26259243Sobrien ATOMAND64_DAG, 26359243Sobrien ATOMNAND64_DAG, 26459243Sobrien ATOMSWAP64_DAG 26559243Sobrien 26659243Sobrien // WARNING: Do not add anything in the end unless you want the node to 26759243Sobrien // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be 26859243Sobrien // thought as target memory ops! 26959243Sobrien }; 27059243Sobrien } 27159243Sobrien 27259243Sobrien /// Define some predicates that are used for node matching. 27359243Sobrien namespace X86 { 27459243Sobrien /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 27559243Sobrien /// specifies a shuffle of elements that is suitable for input to PSHUFD. 27659243Sobrien bool isPSHUFDMask(ShuffleVectorSDNode *N); 27759243Sobrien 27859243Sobrien /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 27959243Sobrien /// specifies a shuffle of elements that is suitable for input to PSHUFD. 28059243Sobrien bool isPSHUFHWMask(ShuffleVectorSDNode *N); 28159243Sobrien 28259243Sobrien /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 28359243Sobrien /// specifies a shuffle of elements that is suitable for input to PSHUFD. 28459243Sobrien bool isPSHUFLWMask(ShuffleVectorSDNode *N); 28559243Sobrien 28659243Sobrien /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 28759243Sobrien /// specifies a shuffle of elements that is suitable for input to SHUFP*. 28859243Sobrien bool isSHUFPMask(ShuffleVectorSDNode *N); 28959243Sobrien 29059243Sobrien /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 29159243Sobrien /// specifies a shuffle of elements that is suitable for input to MOVHLPS. 29259243Sobrien bool isMOVHLPSMask(ShuffleVectorSDNode *N); 29359243Sobrien 29459243Sobrien /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 29559243Sobrien /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 29659243Sobrien /// <2, 3, 2, 3> 29759243Sobrien bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N); 29859243Sobrien 29959243Sobrien /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 30059243Sobrien /// specifies a shuffle of elements that is suitable for MOVLP{S|D}. 30159243Sobrien bool isMOVLPMask(ShuffleVectorSDNode *N); 30259243Sobrien 30359243Sobrien /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 30459243Sobrien /// specifies a shuffle of elements that is suitable for MOVHP{S|D}. 30559243Sobrien /// as well as MOVLHPS. 30659243Sobrien bool isMOVLHPSMask(ShuffleVectorSDNode *N); 30759243Sobrien 30859243Sobrien /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 30959243Sobrien /// specifies a shuffle of elements that is suitable for input to UNPCKL. 31059243Sobrien bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 31159243Sobrien 31259243Sobrien /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 31359243Sobrien /// specifies a shuffle of elements that is suitable for input to UNPCKH. 31459243Sobrien bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 31559243Sobrien 31659243Sobrien /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 31759243Sobrien /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 31859243Sobrien /// <0, 0, 1, 1> 31959243Sobrien bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N); 32059243Sobrien 32159243Sobrien /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 32259243Sobrien /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 32359243Sobrien /// <2, 2, 3, 3> 32459243Sobrien bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N); 32559243Sobrien 32659243Sobrien /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 32759243Sobrien /// specifies a shuffle of elements that is suitable for input to MOVSS, 32859243Sobrien /// MOVSD, and MOVD, i.e. setting the lowest element. 32959243Sobrien bool isMOVLMask(ShuffleVectorSDNode *N); 33059243Sobrien 33159243Sobrien /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 33259243Sobrien /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 33359243Sobrien bool isMOVSHDUPMask(ShuffleVectorSDNode *N); 33459243Sobrien 33559243Sobrien /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 33659243Sobrien /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 33759243Sobrien bool isMOVSLDUPMask(ShuffleVectorSDNode *N); 33859243Sobrien 33959243Sobrien /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 34059243Sobrien /// specifies a shuffle of elements that is suitable for input to MOVDDUP. 34159243Sobrien bool isMOVDDUPMask(ShuffleVectorSDNode *N); 34259243Sobrien 34359243Sobrien /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand 34459243Sobrien /// specifies a shuffle of elements that is suitable for input to PALIGNR. 34559243Sobrien bool isPALIGNRMask(ShuffleVectorSDNode *N); 34659243Sobrien 34759243Sobrien /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 34859243Sobrien /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 34959243Sobrien /// instructions. 35059243Sobrien unsigned getShuffleSHUFImmediate(SDNode *N); 35159243Sobrien 35259243Sobrien /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 35359243Sobrien /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction. 35459243Sobrien unsigned getShufflePSHUFHWImmediate(SDNode *N); 35559243Sobrien 35659243Sobrien /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 35759415Sobrien /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction. 35859415Sobrien unsigned getShufflePSHUFLWImmediate(SDNode *N); 35959415Sobrien 36059415Sobrien /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 36159415Sobrien /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 36259415Sobrien unsigned getShufflePALIGNRImmediate(SDNode *N); 36359415Sobrien 36459415Sobrien /// isZeroNode - Returns true if Elt is a constant zero or a floating point 36559243Sobrien /// constant +0.0. 36659243Sobrien bool isZeroNode(SDValue Elt); 36759243Sobrien 36859243Sobrien /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 36959243Sobrien /// fit into displacement field of the instruction. 37059243Sobrien bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 37159243Sobrien bool hasSymbolicDisplacement = true); 37259243Sobrien } 37359243Sobrien 37459243Sobrien //===--------------------------------------------------------------------===// 37559243Sobrien // X86TargetLowering - X86 Implementation of the TargetLowering interface 37659243Sobrien class X86TargetLowering : public TargetLowering { 37759243Sobrien int VarArgsFrameIndex; // FrameIndex for start of varargs area. 37859243Sobrien int RegSaveFrameIndex; // X86-64 vararg func register save area. 37959243Sobrien unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset. 38059243Sobrien unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset. 38159243Sobrien int BytesToPopOnReturn; // Number of arg bytes ret should pop. 38259243Sobrien 38359243Sobrien public: 38459415Sobrien explicit X86TargetLowering(X86TargetMachine &TM); 38559415Sobrien 38659415Sobrien /// getPICBaseSymbol - Return the X86-32 PIC base. 38759415Sobrien MCSymbol *getPICBaseSymbol(const MachineFunction *MF, MCContext &Ctx) const; 38859415Sobrien 38959415Sobrien virtual unsigned getJumpTableEncoding() const; 39059415Sobrien 39159415Sobrien virtual const MCExpr * 39259243Sobrien LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 39359243Sobrien const MachineBasicBlock *MBB, unsigned uid, 39459243Sobrien MCContext &Ctx) const; 39559243Sobrien 39659243Sobrien /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 39759243Sobrien /// jumptable. 39859243Sobrien virtual SDValue getPICJumpTableRelocBase(SDValue Table, 39959243Sobrien SelectionDAG &DAG) const; 40059243Sobrien virtual const MCExpr * 40159243Sobrien getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 40259243Sobrien unsigned JTI, MCContext &Ctx) const; 40359243Sobrien 40459243Sobrien // Return the number of bytes that a function should pop when it returns (in 40559243Sobrien // addition to the space used by the return address). 40659243Sobrien // 40759243Sobrien unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; } 40859243Sobrien 40959243Sobrien /// getStackPtrReg - Return the stack pointer register we are using: either 41059243Sobrien /// ESP or RSP. 41159243Sobrien unsigned getStackPtrReg() const { return X86StackPtr; } 41259243Sobrien 41359243Sobrien /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 41459243Sobrien /// function arguments in the caller parameter area. For X86, aggregates 41559243Sobrien /// that contains are placed at 16-byte boundaries while the rest are at 41659243Sobrien /// 4-byte boundaries. 41759243Sobrien virtual unsigned getByValTypeAlignment(const Type *Ty) const; 41859243Sobrien 41959243Sobrien /// getOptimalMemOpType - Returns the target specific optimal type for load 42059243Sobrien /// and store operations as a result of memset, memcpy, and memmove 42159243Sobrien /// lowering. It returns EVT::iAny if SelectionDAG should be responsible for 42259243Sobrien /// determining it. 42359243Sobrien virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align, 42459243Sobrien bool isSrcConst, bool isSrcStr, 42559243Sobrien SelectionDAG &DAG) const; 42659243Sobrien 42759243Sobrien /// allowsUnalignedMemoryAccesses - Returns true if the target allows 42859243Sobrien /// unaligned memory accesses. of the specified type. 42959243Sobrien virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 43059243Sobrien return true; 43159243Sobrien } 43259243Sobrien 43359243Sobrien /// LowerOperation - Provide custom lowering hooks for some operations. 43459243Sobrien /// 43559243Sobrien virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 43659243Sobrien 43759243Sobrien /// ReplaceNodeResults - Replace the results of node with an illegal result 43859243Sobrien /// type with new values built out of custom code. 43959243Sobrien /// 44059243Sobrien virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 44159243Sobrien SelectionDAG &DAG); 44259243Sobrien 44359243Sobrien 44459243Sobrien virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 44559243Sobrien 44659243Sobrien virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 44759243Sobrien MachineBasicBlock *MBB, 44859243Sobrien DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 44959243Sobrien 45059243Sobrien 45159243Sobrien /// getTargetNodeName - This method returns the name of a target specific 45259243Sobrien /// DAG node. 45359243Sobrien virtual const char *getTargetNodeName(unsigned Opcode) const; 45459243Sobrien 45559243Sobrien /// getSetCCResultType - Return the ISD::SETCC ValueType 45659243Sobrien virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; 45759243Sobrien 45859243Sobrien /// computeMaskedBitsForTargetNode - Determine which of the bits specified 45959243Sobrien /// in Mask are known to be either zero or one and return them in the 46059243Sobrien /// KnownZero/KnownOne bitsets. 46159243Sobrien virtual void computeMaskedBitsForTargetNode(const SDValue Op, 46259243Sobrien const APInt &Mask, 46359243Sobrien APInt &KnownZero, 46459243Sobrien APInt &KnownOne, 46559243Sobrien const SelectionDAG &DAG, 46659243Sobrien unsigned Depth = 0) const; 46759243Sobrien 46859243Sobrien virtual bool 46959243Sobrien isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 47059243Sobrien 47159243Sobrien SDValue getReturnAddressFrameIndex(SelectionDAG &DAG); 47259243Sobrien 47359243Sobrien virtual bool ExpandInlineAsm(CallInst *CI) const; 47459243Sobrien 47559243Sobrien ConstraintType getConstraintType(const std::string &Constraint) const; 47659243Sobrien 47759415Sobrien std::vector<unsigned> 47859243Sobrien getRegClassForInlineAsmConstraint(const std::string &Constraint, 47959243Sobrien EVT VT) const; 48059243Sobrien 48159243Sobrien virtual const char *LowerXConstraint(EVT ConstraintVT) const; 48259243Sobrien 48359243Sobrien /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 48459243Sobrien /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 48559243Sobrien /// true it means one of the asm constraint of the inline asm instruction 48659243Sobrien /// being processed is 'm'. 48759243Sobrien virtual void LowerAsmOperandForConstraint(SDValue Op, 48859243Sobrien char ConstraintLetter, 48959243Sobrien bool hasMemory, 49059243Sobrien std::vector<SDValue> &Ops, 49159243Sobrien SelectionDAG &DAG) const; 49259243Sobrien 49359243Sobrien /// getRegForInlineAsmConstraint - Given a physical register constraint 49459243Sobrien /// (e.g. {edx}), return the register number and the register class for the 49559243Sobrien /// register. This should only be used for C_Register constraints. On 49659243Sobrien /// error, this returns a register number of 0. 49759243Sobrien std::pair<unsigned, const TargetRegisterClass*> 49859243Sobrien getRegForInlineAsmConstraint(const std::string &Constraint, 49959243Sobrien EVT VT) const; 50059243Sobrien 50159243Sobrien /// isLegalAddressingMode - Return true if the addressing mode represented 50259243Sobrien /// by AM is legal for this target, for a load/store of the specified type. 50359243Sobrien virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 50459243Sobrien 50559243Sobrien /// isTruncateFree - Return true if it's free to truncate a value of 50659243Sobrien /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 50759243Sobrien /// register EAX to i16 by referencing its sub-register AX. 50859243Sobrien virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const; 50959243Sobrien virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 51059243Sobrien 51159243Sobrien /// isZExtFree - Return true if any actual instruction that defines a 51259243Sobrien /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 51359243Sobrien /// register. This does not necessarily include registers defined in 51459243Sobrien /// unknown ways, such as incoming arguments, or copies from unknown 51559243Sobrien /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 51659243Sobrien /// does not necessarily apply to truncate instructions. e.g. on x86-64, 51759243Sobrien /// all instructions that define 32-bit values implicit zero-extend the 51859243Sobrien /// result out to 64 bits. 51959243Sobrien virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const; 52059243Sobrien virtual bool isZExtFree(EVT VT1, EVT VT2) const; 52159243Sobrien 52259243Sobrien /// isNarrowingProfitable - Return true if it's profitable to narrow 52359243Sobrien /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 52459243Sobrien /// from i32 to i8 but not from i32 to i16. 52559243Sobrien virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 52659243Sobrien 52759243Sobrien /// isFPImmLegal - Returns true if the target can instruction select the 52859243Sobrien /// specified FP immediate natively. If false, the legalizer will 52959243Sobrien /// materialize the FP immediate as a load from a constant pool. 53059243Sobrien virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 53159243Sobrien 53259243Sobrien /// isShuffleMaskLegal - Targets can use this to indicate that they only 53359243Sobrien /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 53459243Sobrien /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 53559243Sobrien /// values are assumed to be legal. 53659243Sobrien virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 53759243Sobrien EVT VT) const; 53859243Sobrien 53959243Sobrien /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 54059243Sobrien /// used by Targets can use this to indicate if there is a suitable 54159243Sobrien /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 54259243Sobrien /// pool entry. 54359243Sobrien virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 54459243Sobrien EVT VT) const; 54559243Sobrien 54659243Sobrien /// ShouldShrinkFPConstant - If true, then instruction selection should 54759243Sobrien /// seek to shrink the FP constant of the specified type to a smaller type 54859243Sobrien /// in order to save space and / or reduce runtime. 54959243Sobrien virtual bool ShouldShrinkFPConstant(EVT VT) const { 55059243Sobrien // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 55159243Sobrien // expensive than a straight movsd. On the other hand, it's important to 55259243Sobrien // shrink long double fp constant since fldt is very slow. 55359243Sobrien return !X86ScalarSSEf64 || VT == MVT::f80; 55459243Sobrien } 55559243Sobrien 55659243Sobrien virtual const X86Subtarget* getSubtarget() { 55759243Sobrien return Subtarget; 55859243Sobrien } 55959243Sobrien 56059243Sobrien /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 56159243Sobrien /// computed in an SSE register, not on the X87 floating point stack. 56259243Sobrien bool isScalarFPTypeInSSEReg(EVT VT) const { 56359243Sobrien return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 56459243Sobrien (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 56559243Sobrien } 56659243Sobrien 56759243Sobrien /// getWidenVectorType: given a vector type, returns the type to widen 56859243Sobrien /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 56959243Sobrien /// If there is no vector type that we want to widen to, returns EVT::Other 57059243Sobrien /// When and were to widen is target dependent based on the cost of 57159243Sobrien /// scalarizing vs using the wider vector type. 57259243Sobrien virtual EVT getWidenVectorType(EVT VT) const; 57359243Sobrien 57459243Sobrien /// createFastISel - This method returns a target specific FastISel object, 57559243Sobrien /// or null if the target does not support "fast" ISel. 57659243Sobrien virtual FastISel * 57759243Sobrien createFastISel(MachineFunction &mf, 57859243Sobrien MachineModuleInfo *mmi, DwarfWriter *dw, 57959243Sobrien DenseMap<const Value *, unsigned> &, 58059243Sobrien DenseMap<const BasicBlock *, MachineBasicBlock *> &, 58159243Sobrien DenseMap<const AllocaInst *, int> & 58259243Sobrien#ifndef NDEBUG 58359243Sobrien , SmallSet<Instruction*, 8> & 58459243Sobrien#endif 58559243Sobrien ); 58659243Sobrien 58759243Sobrien /// getFunctionAlignment - Return the Log2 alignment of this function. 58859243Sobrien virtual unsigned getFunctionAlignment(const Function *F) const; 58959243Sobrien 59059243Sobrien private: 59159243Sobrien /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 59259243Sobrien /// make the right decision when generating code for different targets. 59359243Sobrien const X86Subtarget *Subtarget; 59459243Sobrien const X86RegisterInfo *RegInfo; 59559243Sobrien const TargetData *TD; 59659243Sobrien 59759243Sobrien /// X86StackPtr - X86 physical register used as stack ptr. 59859243Sobrien unsigned X86StackPtr; 59959243Sobrien 60059243Sobrien /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 60159243Sobrien /// floating point ops. 60259243Sobrien /// When SSE is available, use it for f32 operations. 60359243Sobrien /// When SSE2 is available, use it for f64 operations. 60459243Sobrien bool X86ScalarSSEf32; 60559243Sobrien bool X86ScalarSSEf64; 60659243Sobrien 60759243Sobrien /// LegalFPImmediates - A list of legal fp immediates. 60859243Sobrien std::vector<APFloat> LegalFPImmediates; 60959243Sobrien 61059243Sobrien /// addLegalFPImmediate - Indicate that this x86 target can instruction 61159243Sobrien /// select the specified FP immediate natively. 61259243Sobrien void addLegalFPImmediate(const APFloat& Imm) { 61359243Sobrien LegalFPImmediates.push_back(Imm); 61459243Sobrien } 61559243Sobrien 61659243Sobrien SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 61759243Sobrien CallingConv::ID CallConv, bool isVarArg, 61859243Sobrien const SmallVectorImpl<ISD::InputArg> &Ins, 61959243Sobrien DebugLoc dl, SelectionDAG &DAG, 62059243Sobrien SmallVectorImpl<SDValue> &InVals); 62159243Sobrien SDValue LowerMemArgument(SDValue Chain, 62259243Sobrien CallingConv::ID CallConv, 62359243Sobrien const SmallVectorImpl<ISD::InputArg> &ArgInfo, 62459243Sobrien DebugLoc dl, SelectionDAG &DAG, 62559243Sobrien const CCValAssign &VA, MachineFrameInfo *MFI, 62659243Sobrien unsigned i); 62759243Sobrien SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 62859243Sobrien DebugLoc dl, SelectionDAG &DAG, 62959243Sobrien const CCValAssign &VA, 63059243Sobrien ISD::ArgFlagsTy Flags); 63159243Sobrien 63259243Sobrien // Call lowering helpers. 63359243Sobrien 63459243Sobrien /// IsEligibleForTailCallOptimization - Check whether the call is eligible 63559243Sobrien /// for tail call optimization. Targets which want to do tail call 63659243Sobrien /// optimization should implement this function. 63759243Sobrien bool IsEligibleForTailCallOptimization(SDValue Callee, 63859243Sobrien CallingConv::ID CalleeCC, 63959243Sobrien bool isVarArg, 64059243Sobrien const SmallVectorImpl<ISD::OutputArg> &Outs, 64159243Sobrien const SmallVectorImpl<ISD::InputArg> &Ins, 64259243Sobrien SelectionDAG& DAG) const; 64359243Sobrien bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv); 64459243Sobrien SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 64559243Sobrien SDValue Chain, bool IsTailCall, bool Is64Bit, 64659243Sobrien int FPDiff, DebugLoc dl); 64759243Sobrien 64859243Sobrien CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const; 64959243Sobrien unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG); 65059243Sobrien 65159243Sobrien std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 65259243Sobrien bool isSigned); 65359243Sobrien 65459243Sobrien SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 65559243Sobrien SelectionDAG &DAG); 65659243Sobrien SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); 65759243Sobrien SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG); 65859243Sobrien SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); 65959243Sobrien SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); 66059243Sobrien SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); 66159243Sobrien SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); 66259243Sobrien SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); 66359243Sobrien SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); 66459243Sobrien SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); 66559243Sobrien SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); 66659243Sobrien SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 66759243Sobrien int64_t Offset, SelectionDAG &DAG) const; 66859243Sobrien SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); 66959243Sobrien SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); 67059243Sobrien SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG); 67159243Sobrien SDValue LowerShift(SDValue Op, SelectionDAG &DAG); 67259243Sobrien SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 67359243Sobrien SelectionDAG &DAG); 67459243Sobrien SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); 67559243Sobrien SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG); 67659243Sobrien SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG); 67759243Sobrien SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG); 67859243Sobrien SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG); 67959243Sobrien SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG); 68059243Sobrien SDValue LowerFABS(SDValue Op, SelectionDAG &DAG); 68159243Sobrien SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG); 68259243Sobrien SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG); 68359243Sobrien SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); 68459243Sobrien SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG); 68559243Sobrien SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG); 68659243Sobrien SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG); 68759243Sobrien SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG); 68859243Sobrien SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); 68959243Sobrien SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG); 69059243Sobrien SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG); 69159243Sobrien SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG); 69259243Sobrien SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG); 69359243Sobrien SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); 69459243Sobrien SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); 69559243Sobrien SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); 69659243Sobrien SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG); 69759243Sobrien SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG); 69859243Sobrien SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG); 69959243Sobrien SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); 70059243Sobrien SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG); 70159243Sobrien SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG); 70259243Sobrien SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG); 70359243Sobrien SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG); 70459243Sobrien 70559243Sobrien SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG); 70659243Sobrien SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG); 70759243Sobrien SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG); 70859243Sobrien 70959243Sobrien virtual SDValue 71059243Sobrien LowerFormalArguments(SDValue Chain, 71159243Sobrien CallingConv::ID CallConv, bool isVarArg, 71259243Sobrien const SmallVectorImpl<ISD::InputArg> &Ins, 71359243Sobrien DebugLoc dl, SelectionDAG &DAG, 71459243Sobrien SmallVectorImpl<SDValue> &InVals); 71559243Sobrien virtual SDValue 71659243Sobrien LowerCall(SDValue Chain, SDValue Callee, 71759243Sobrien CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 71859243Sobrien const SmallVectorImpl<ISD::OutputArg> &Outs, 71959243Sobrien const SmallVectorImpl<ISD::InputArg> &Ins, 72059243Sobrien DebugLoc dl, SelectionDAG &DAG, 72159243Sobrien SmallVectorImpl<SDValue> &InVals); 72259243Sobrien 72359243Sobrien virtual SDValue 72459243Sobrien LowerReturn(SDValue Chain, 72559243Sobrien CallingConv::ID CallConv, bool isVarArg, 72659243Sobrien const SmallVectorImpl<ISD::OutputArg> &Outs, 72759243Sobrien DebugLoc dl, SelectionDAG &DAG); 72859243Sobrien 72959243Sobrien virtual bool 73059243Sobrien CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 73159243Sobrien const SmallVectorImpl<EVT> &OutTys, 73259243Sobrien const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 73359243Sobrien SelectionDAG &DAG); 73459243Sobrien 73559243Sobrien void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results, 73659243Sobrien SelectionDAG &DAG, unsigned NewOp); 73759243Sobrien 73859243Sobrien SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 73959243Sobrien SDValue Chain, 74059243Sobrien SDValue Dst, SDValue Src, 74159243Sobrien SDValue Size, unsigned Align, 74259243Sobrien const Value *DstSV, uint64_t DstSVOff); 74359243Sobrien SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 74459243Sobrien SDValue Chain, 74559243Sobrien SDValue Dst, SDValue Src, 746 SDValue Size, unsigned Align, 747 bool AlwaysInline, 748 const Value *DstSV, uint64_t DstSVOff, 749 const Value *SrcSV, uint64_t SrcSVOff); 750 751 /// Utility function to emit string processing sse4.2 instructions 752 /// that return in xmm0. 753 /// This takes the instruction to expand, the associated machine basic 754 /// block, the number of args, and whether or not the second arg is 755 /// in memory or not. 756 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, 757 unsigned argNum, bool inMem) const; 758 759 /// Utility function to emit atomic bitwise operations (and, or, xor). 760 /// It takes the bitwise instruction to expand, the associated machine basic 761 /// block, and the associated X86 opcodes for reg/reg and reg/imm. 762 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter( 763 MachineInstr *BInstr, 764 MachineBasicBlock *BB, 765 unsigned regOpc, 766 unsigned immOpc, 767 unsigned loadOpc, 768 unsigned cxchgOpc, 769 unsigned copyOpc, 770 unsigned notOpc, 771 unsigned EAXreg, 772 TargetRegisterClass *RC, 773 bool invSrc = false) const; 774 775 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter( 776 MachineInstr *BInstr, 777 MachineBasicBlock *BB, 778 unsigned regOpcL, 779 unsigned regOpcH, 780 unsigned immOpcL, 781 unsigned immOpcH, 782 bool invSrc = false) const; 783 784 /// Utility function to emit atomic min and max. It takes the min/max 785 /// instruction to expand, the associated basic block, and the associated 786 /// cmov opcode for moving the min or max value. 787 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, 788 MachineBasicBlock *BB, 789 unsigned cmovOpc) const; 790 791 /// Utility function to emit the xmm reg save portion of va_start. 792 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 793 MachineInstr *BInstr, 794 MachineBasicBlock *BB) const; 795 796 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 797 MachineBasicBlock *BB, 798 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 799 800 MachineBasicBlock *EmitLoweredMingwAlloca(MachineInstr *MI, 801 MachineBasicBlock *BB, 802 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 803 804 /// Emit nodes that will be selected as "test Op0,Op0", or something 805 /// equivalent, for use with the given x86 condition code. 806 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG); 807 808 /// Emit nodes that will be selected as "cmp Op0,Op1", or something 809 /// equivalent, for use with the given x86 condition code. 810 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 811 SelectionDAG &DAG); 812 }; 813 814 namespace X86 { 815 FastISel *createFastISel(MachineFunction &mf, 816 MachineModuleInfo *mmi, DwarfWriter *dw, 817 DenseMap<const Value *, unsigned> &, 818 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 819 DenseMap<const AllocaInst *, int> & 820#ifndef NDEBUG 821 , SmallSet<Instruction*, 8> & 822#endif 823 ); 824 } 825} 826 827#endif // X86ISELLOWERING_H 828