X86ISelLowering.h revision 204642
1//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that X86 uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef X86ISELLOWERING_H 16#define X86ISELLOWERING_H 17 18#include "X86Subtarget.h" 19#include "X86RegisterInfo.h" 20#include "X86MachineFunctionInfo.h" 21#include "llvm/Target/TargetLowering.h" 22#include "llvm/Target/TargetOptions.h" 23#include "llvm/CodeGen/FastISel.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/CallingConvLower.h" 26 27namespace llvm { 28 namespace X86ISD { 29 // X86 Specific DAG Nodes 30 enum NodeType { 31 // Start the numbering where the builtin ops leave off. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 /// BSF - Bit scan forward. 35 /// BSR - Bit scan reverse. 36 BSF, 37 BSR, 38 39 /// SHLD, SHRD - Double shift instructions. These correspond to 40 /// X86::SHLDxx and X86::SHRDxx instructions. 41 SHLD, 42 SHRD, 43 44 /// FAND - Bitwise logical AND of floating point values. This corresponds 45 /// to X86::ANDPS or X86::ANDPD. 46 FAND, 47 48 /// FOR - Bitwise logical OR of floating point values. This corresponds 49 /// to X86::ORPS or X86::ORPD. 50 FOR, 51 52 /// FXOR - Bitwise logical XOR of floating point values. This corresponds 53 /// to X86::XORPS or X86::XORPD. 54 FXOR, 55 56 /// FSRL - Bitwise logical right shift of floating point values. These 57 /// corresponds to X86::PSRLDQ. 58 FSRL, 59 60 /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 61 /// integer source in memory and FP reg result. This corresponds to the 62 /// X86::FILD*m instructions. It has three inputs (token chain, address, 63 /// and source type) and two outputs (FP value and token chain). FILD_FLAG 64 /// also produces a flag). 65 FILD, 66 FILD_FLAG, 67 68 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 69 /// integer destination in memory and a FP reg source. This corresponds 70 /// to the X86::FIST*m instructions and the rounding mode change stuff. It 71 /// has two inputs (token chain and address) and two outputs (int value 72 /// and token chain). 73 FP_TO_INT16_IN_MEM, 74 FP_TO_INT32_IN_MEM, 75 FP_TO_INT64_IN_MEM, 76 77 /// FLD - This instruction implements an extending load to FP stack slots. 78 /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 79 /// operand, ptr to load from, and a ValueType node indicating the type 80 /// to load to. 81 FLD, 82 83 /// FST - This instruction implements a truncating store to FP stack 84 /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 85 /// chain operand, value to store, address, and a ValueType to store it 86 /// as. 87 FST, 88 89 /// CALL - These operations represent an abstract X86 call 90 /// instruction, which includes a bunch of information. In particular the 91 /// operands of these node are: 92 /// 93 /// #0 - The incoming token chain 94 /// #1 - The callee 95 /// #2 - The number of arg bytes the caller pushes on the stack. 96 /// #3 - The number of arg bytes the callee pops off the stack. 97 /// #4 - The value to pass in AL/AX/EAX (optional) 98 /// #5 - The value to pass in DL/DX/EDX (optional) 99 /// 100 /// The result values of these nodes are: 101 /// 102 /// #0 - The outgoing token chain 103 /// #1 - The first register result value (optional) 104 /// #2 - The second register result value (optional) 105 /// 106 CALL, 107 108 /// RDTSC_DAG - This operation implements the lowering for 109 /// readcyclecounter 110 RDTSC_DAG, 111 112 /// X86 compare and logical compare instructions. 113 CMP, COMI, UCOMI, 114 115 /// X86 bit-test instructions. 116 BT, 117 118 /// X86 SetCC. Operand 0 is condition code, and operand 1 is the flag 119 /// operand produced by a CMP instruction. 120 SETCC, 121 122 // Same as SETCC except it's materialized with a sbb and the value is all 123 // one's or all zero's. 124 SETCC_CARRY, 125 126 /// X86 conditional moves. Operand 0 and operand 1 are the two values 127 /// to select from. Operand 2 is the condition code, and operand 3 is the 128 /// flag operand produced by a CMP or TEST instruction. It also writes a 129 /// flag result. 130 CMOV, 131 132 /// X86 conditional branches. Operand 0 is the chain operand, operand 1 133 /// is the block to branch if condition is true, operand 2 is the 134 /// condition code, and operand 3 is the flag operand produced by a CMP 135 /// or TEST instruction. 136 BRCOND, 137 138 /// Return with a flag operand. Operand 0 is the chain operand, operand 139 /// 1 is the number of bytes of stack to pop. 140 RET_FLAG, 141 142 /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 143 REP_STOS, 144 145 /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 146 REP_MOVS, 147 148 /// GlobalBaseReg - On Darwin, this node represents the result of the popl 149 /// at function entry, used for PIC code. 150 GlobalBaseReg, 151 152 /// Wrapper - A wrapper node for TargetConstantPool, 153 /// TargetExternalSymbol, and TargetGlobalAddress. 154 Wrapper, 155 156 /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 157 /// relative displacements. 158 WrapperRIP, 159 160 /// MOVQ2DQ - Copies a 64-bit value from a vector to another vector. 161 /// Can be used to move a vector value from a MMX register to a XMM 162 /// register. 163 MOVQ2DQ, 164 165 /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 166 /// i32, corresponds to X86::PEXTRB. 167 PEXTRB, 168 169 /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 170 /// i32, corresponds to X86::PEXTRW. 171 PEXTRW, 172 173 /// INSERTPS - Insert any element of a 4 x float vector into any element 174 /// of a destination 4 x floatvector. 175 INSERTPS, 176 177 /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 178 /// corresponds to X86::PINSRB. 179 PINSRB, 180 181 /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 182 /// corresponds to X86::PINSRW. 183 PINSRW, MMX_PINSRW, 184 185 /// PSHUFB - Shuffle 16 8-bit values within a vector. 186 PSHUFB, 187 188 /// FMAX, FMIN - Floating point max and min. 189 /// 190 FMAX, FMIN, 191 192 /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 193 /// approximation. Note that these typically require refinement 194 /// in order to obtain suitable precision. 195 FRSQRT, FRCP, 196 197 // TLSADDR - Thread Local Storage. 198 TLSADDR, 199 200 // SegmentBaseAddress - The address segment:0 201 SegmentBaseAddress, 202 203 // EH_RETURN - Exception Handling helpers. 204 EH_RETURN, 205 206 /// TC_RETURN - Tail call return. 207 /// operand #0 chain 208 /// operand #1 callee (register or absolute) 209 /// operand #2 stack adjustment 210 /// operand #3 optional in flag 211 TC_RETURN, 212 213 // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap. 214 LCMPXCHG_DAG, 215 LCMPXCHG8_DAG, 216 217 // FNSTCW16m - Store FP control world into i16 memory. 218 FNSTCW16m, 219 220 // VZEXT_MOVL - Vector move low and zero extend. 221 VZEXT_MOVL, 222 223 // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 224 VZEXT_LOAD, 225 226 // VSHL, VSRL - Vector logical left / right shift. 227 VSHL, VSRL, 228 229 // CMPPD, CMPPS - Vector double/float comparison. 230 // CMPPD, CMPPS - Vector double/float comparison. 231 CMPPD, CMPPS, 232 233 // PCMP* - Vector integer comparisons. 234 PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ, 235 PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ, 236 237 // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results. 238 ADD, SUB, SMUL, UMUL, 239 INC, DEC, OR, XOR, AND, 240 241 // MUL_IMM - X86 specific multiply by immediate. 242 MUL_IMM, 243 244 // PTEST - Vector bitwise comparisons 245 PTEST, 246 247 // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 248 // according to %al. An operator is needed so that this can be expanded 249 // with control flow. 250 VASTART_SAVE_XMM_REGS, 251 252 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 253 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 254 // Atomic 64-bit binary operations. 255 ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 256 ATOMSUB64_DAG, 257 ATOMOR64_DAG, 258 ATOMXOR64_DAG, 259 ATOMAND64_DAG, 260 ATOMNAND64_DAG, 261 ATOMSWAP64_DAG 262 }; 263 } 264 265 /// Define some predicates that are used for node matching. 266 namespace X86 { 267 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand 268 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 269 bool isPSHUFDMask(ShuffleVectorSDNode *N); 270 271 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand 272 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 273 bool isPSHUFHWMask(ShuffleVectorSDNode *N); 274 275 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand 276 /// specifies a shuffle of elements that is suitable for input to PSHUFD. 277 bool isPSHUFLWMask(ShuffleVectorSDNode *N); 278 279 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 280 /// specifies a shuffle of elements that is suitable for input to SHUFP*. 281 bool isSHUFPMask(ShuffleVectorSDNode *N); 282 283 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 284 /// specifies a shuffle of elements that is suitable for input to MOVHLPS. 285 bool isMOVHLPSMask(ShuffleVectorSDNode *N); 286 287 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 288 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 289 /// <2, 3, 2, 3> 290 bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N); 291 292 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 293 /// specifies a shuffle of elements that is suitable for MOVLP{S|D}. 294 bool isMOVLPMask(ShuffleVectorSDNode *N); 295 296 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand 297 /// specifies a shuffle of elements that is suitable for MOVHP{S|D}. 298 /// as well as MOVLHPS. 299 bool isMOVLHPSMask(ShuffleVectorSDNode *N); 300 301 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 302 /// specifies a shuffle of elements that is suitable for input to UNPCKL. 303 bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 304 305 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 306 /// specifies a shuffle of elements that is suitable for input to UNPCKH. 307 bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false); 308 309 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 310 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 311 /// <0, 0, 1, 1> 312 bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N); 313 314 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 315 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 316 /// <2, 2, 3, 3> 317 bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N); 318 319 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 320 /// specifies a shuffle of elements that is suitable for input to MOVSS, 321 /// MOVSD, and MOVD, i.e. setting the lowest element. 322 bool isMOVLMask(ShuffleVectorSDNode *N); 323 324 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 325 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 326 bool isMOVSHDUPMask(ShuffleVectorSDNode *N); 327 328 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 329 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 330 bool isMOVSLDUPMask(ShuffleVectorSDNode *N); 331 332 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 333 /// specifies a shuffle of elements that is suitable for input to MOVDDUP. 334 bool isMOVDDUPMask(ShuffleVectorSDNode *N); 335 336 /// isPALIGNRMask - Return true if the specified VECTOR_SHUFFLE operand 337 /// specifies a shuffle of elements that is suitable for input to PALIGNR. 338 bool isPALIGNRMask(ShuffleVectorSDNode *N); 339 340 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 341 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP* 342 /// instructions. 343 unsigned getShuffleSHUFImmediate(SDNode *N); 344 345 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 346 /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction. 347 unsigned getShufflePSHUFHWImmediate(SDNode *N); 348 349 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 350 /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction. 351 unsigned getShufflePSHUFLWImmediate(SDNode *N); 352 353 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 354 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 355 unsigned getShufflePALIGNRImmediate(SDNode *N); 356 357 /// isZeroNode - Returns true if Elt is a constant zero or a floating point 358 /// constant +0.0. 359 bool isZeroNode(SDValue Elt); 360 361 /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 362 /// fit into displacement field of the instruction. 363 bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 364 bool hasSymbolicDisplacement = true); 365 } 366 367 //===--------------------------------------------------------------------===// 368 // X86TargetLowering - X86 Implementation of the TargetLowering interface 369 class X86TargetLowering : public TargetLowering { 370 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 371 int RegSaveFrameIndex; // X86-64 vararg func register save area. 372 unsigned VarArgsGPOffset; // X86-64 vararg func int reg offset. 373 unsigned VarArgsFPOffset; // X86-64 vararg func fp reg offset. 374 int BytesToPopOnReturn; // Number of arg bytes ret should pop. 375 376 public: 377 explicit X86TargetLowering(X86TargetMachine &TM); 378 379 /// getPICBaseSymbol - Return the X86-32 PIC base. 380 MCSymbol *getPICBaseSymbol(const MachineFunction *MF, MCContext &Ctx) const; 381 382 virtual unsigned getJumpTableEncoding() const; 383 384 virtual const MCExpr * 385 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 386 const MachineBasicBlock *MBB, unsigned uid, 387 MCContext &Ctx) const; 388 389 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 390 /// jumptable. 391 virtual SDValue getPICJumpTableRelocBase(SDValue Table, 392 SelectionDAG &DAG) const; 393 virtual const MCExpr * 394 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 395 unsigned JTI, MCContext &Ctx) const; 396 397 // Return the number of bytes that a function should pop when it returns (in 398 // addition to the space used by the return address). 399 // 400 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; } 401 402 /// getStackPtrReg - Return the stack pointer register we are using: either 403 /// ESP or RSP. 404 unsigned getStackPtrReg() const { return X86StackPtr; } 405 406 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 407 /// function arguments in the caller parameter area. For X86, aggregates 408 /// that contains are placed at 16-byte boundaries while the rest are at 409 /// 4-byte boundaries. 410 virtual unsigned getByValTypeAlignment(const Type *Ty) const; 411 412 /// getOptimalMemOpType - Returns the target specific optimal type for load 413 /// and store operations as a result of memset, memcpy, and memmove 414 /// lowering. It returns EVT::iAny if SelectionDAG should be responsible for 415 /// determining it. 416 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align, 417 bool isSrcConst, bool isSrcStr, 418 SelectionDAG &DAG) const; 419 420 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 421 /// unaligned memory accesses. of the specified type. 422 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const { 423 return true; 424 } 425 426 /// LowerOperation - Provide custom lowering hooks for some operations. 427 /// 428 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 429 430 /// ReplaceNodeResults - Replace the results of node with an illegal result 431 /// type with new values built out of custom code. 432 /// 433 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 434 SelectionDAG &DAG); 435 436 437 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 438 439 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 440 MachineBasicBlock *MBB, 441 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 442 443 444 /// getTargetNodeName - This method returns the name of a target specific 445 /// DAG node. 446 virtual const char *getTargetNodeName(unsigned Opcode) const; 447 448 /// getSetCCResultType - Return the ISD::SETCC ValueType 449 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; 450 451 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 452 /// in Mask are known to be either zero or one and return them in the 453 /// KnownZero/KnownOne bitsets. 454 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 455 const APInt &Mask, 456 APInt &KnownZero, 457 APInt &KnownOne, 458 const SelectionDAG &DAG, 459 unsigned Depth = 0) const; 460 461 virtual bool 462 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const; 463 464 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG); 465 466 virtual bool ExpandInlineAsm(CallInst *CI) const; 467 468 ConstraintType getConstraintType(const std::string &Constraint) const; 469 470 std::vector<unsigned> 471 getRegClassForInlineAsmConstraint(const std::string &Constraint, 472 EVT VT) const; 473 474 virtual const char *LowerXConstraint(EVT ConstraintVT) const; 475 476 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 477 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 478 /// true it means one of the asm constraint of the inline asm instruction 479 /// being processed is 'm'. 480 virtual void LowerAsmOperandForConstraint(SDValue Op, 481 char ConstraintLetter, 482 bool hasMemory, 483 std::vector<SDValue> &Ops, 484 SelectionDAG &DAG) const; 485 486 /// getRegForInlineAsmConstraint - Given a physical register constraint 487 /// (e.g. {edx}), return the register number and the register class for the 488 /// register. This should only be used for C_Register constraints. On 489 /// error, this returns a register number of 0. 490 std::pair<unsigned, const TargetRegisterClass*> 491 getRegForInlineAsmConstraint(const std::string &Constraint, 492 EVT VT) const; 493 494 /// isLegalAddressingMode - Return true if the addressing mode represented 495 /// by AM is legal for this target, for a load/store of the specified type. 496 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 497 498 /// isTruncateFree - Return true if it's free to truncate a value of 499 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 500 /// register EAX to i16 by referencing its sub-register AX. 501 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const; 502 virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 503 504 /// isZExtFree - Return true if any actual instruction that defines a 505 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 506 /// register. This does not necessarily include registers defined in 507 /// unknown ways, such as incoming arguments, or copies from unknown 508 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 509 /// does not necessarily apply to truncate instructions. e.g. on x86-64, 510 /// all instructions that define 32-bit values implicit zero-extend the 511 /// result out to 64 bits. 512 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const; 513 virtual bool isZExtFree(EVT VT1, EVT VT2) const; 514 515 /// isNarrowingProfitable - Return true if it's profitable to narrow 516 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 517 /// from i32 to i8 but not from i32 to i16. 518 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 519 520 /// isFPImmLegal - Returns true if the target can instruction select the 521 /// specified FP immediate natively. If false, the legalizer will 522 /// materialize the FP immediate as a load from a constant pool. 523 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 524 525 /// isShuffleMaskLegal - Targets can use this to indicate that they only 526 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 527 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 528 /// values are assumed to be legal. 529 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 530 EVT VT) const; 531 532 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 533 /// used by Targets can use this to indicate if there is a suitable 534 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 535 /// pool entry. 536 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 537 EVT VT) const; 538 539 /// ShouldShrinkFPConstant - If true, then instruction selection should 540 /// seek to shrink the FP constant of the specified type to a smaller type 541 /// in order to save space and / or reduce runtime. 542 virtual bool ShouldShrinkFPConstant(EVT VT) const { 543 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 544 // expensive than a straight movsd. On the other hand, it's important to 545 // shrink long double fp constant since fldt is very slow. 546 return !X86ScalarSSEf64 || VT == MVT::f80; 547 } 548 549 virtual const X86Subtarget* getSubtarget() { 550 return Subtarget; 551 } 552 553 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 554 /// computed in an SSE register, not on the X87 floating point stack. 555 bool isScalarFPTypeInSSEReg(EVT VT) const { 556 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 557 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 558 } 559 560 /// getWidenVectorType: given a vector type, returns the type to widen 561 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. 562 /// If there is no vector type that we want to widen to, returns EVT::Other 563 /// When and were to widen is target dependent based on the cost of 564 /// scalarizing vs using the wider vector type. 565 virtual EVT getWidenVectorType(EVT VT) const; 566 567 /// createFastISel - This method returns a target specific FastISel object, 568 /// or null if the target does not support "fast" ISel. 569 virtual FastISel * 570 createFastISel(MachineFunction &mf, 571 MachineModuleInfo *mmi, DwarfWriter *dw, 572 DenseMap<const Value *, unsigned> &, 573 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 574 DenseMap<const AllocaInst *, int> & 575#ifndef NDEBUG 576 , SmallSet<Instruction*, 8> & 577#endif 578 ); 579 580 /// getFunctionAlignment - Return the Log2 alignment of this function. 581 virtual unsigned getFunctionAlignment(const Function *F) const; 582 583 private: 584 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 585 /// make the right decision when generating code for different targets. 586 const X86Subtarget *Subtarget; 587 const X86RegisterInfo *RegInfo; 588 const TargetData *TD; 589 590 /// X86StackPtr - X86 physical register used as stack ptr. 591 unsigned X86StackPtr; 592 593 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 594 /// floating point ops. 595 /// When SSE is available, use it for f32 operations. 596 /// When SSE2 is available, use it for f64 operations. 597 bool X86ScalarSSEf32; 598 bool X86ScalarSSEf64; 599 600 /// LegalFPImmediates - A list of legal fp immediates. 601 std::vector<APFloat> LegalFPImmediates; 602 603 /// addLegalFPImmediate - Indicate that this x86 target can instruction 604 /// select the specified FP immediate natively. 605 void addLegalFPImmediate(const APFloat& Imm) { 606 LegalFPImmediates.push_back(Imm); 607 } 608 609 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 610 CallingConv::ID CallConv, bool isVarArg, 611 const SmallVectorImpl<ISD::InputArg> &Ins, 612 DebugLoc dl, SelectionDAG &DAG, 613 SmallVectorImpl<SDValue> &InVals); 614 SDValue LowerMemArgument(SDValue Chain, 615 CallingConv::ID CallConv, 616 const SmallVectorImpl<ISD::InputArg> &ArgInfo, 617 DebugLoc dl, SelectionDAG &DAG, 618 const CCValAssign &VA, MachineFrameInfo *MFI, 619 unsigned i); 620 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 621 DebugLoc dl, SelectionDAG &DAG, 622 const CCValAssign &VA, 623 ISD::ArgFlagsTy Flags); 624 625 // Call lowering helpers. 626 627 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 628 /// for tail call optimization. Targets which want to do tail call 629 /// optimization should implement this function. 630 bool IsEligibleForTailCallOptimization(SDValue Callee, 631 CallingConv::ID CalleeCC, 632 bool isVarArg, 633 const SmallVectorImpl<ISD::OutputArg> &Outs, 634 const SmallVectorImpl<ISD::InputArg> &Ins, 635 SelectionDAG& DAG) const; 636 bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv); 637 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 638 SDValue Chain, bool IsTailCall, bool Is64Bit, 639 int FPDiff, DebugLoc dl); 640 641 CCAssignFn *CCAssignFnForNode(CallingConv::ID CallConv) const; 642 unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG); 643 644 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 645 bool isSigned); 646 647 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 648 SelectionDAG &DAG); 649 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG); 650 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG); 651 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG); 652 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); 653 SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); 654 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG); 655 SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG); 656 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG); 657 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG); 658 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); 659 SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 660 int64_t Offset, SelectionDAG &DAG) const; 661 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG); 662 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); 663 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG); 664 SDValue LowerShift(SDValue Op, SelectionDAG &DAG); 665 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 666 SelectionDAG &DAG); 667 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); 668 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG); 669 SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG); 670 SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG); 671 SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG); 672 SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG); 673 SDValue LowerFABS(SDValue Op, SelectionDAG &DAG); 674 SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG); 675 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG); 676 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG); 677 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG); 678 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG); 679 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG); 680 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG); 681 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG); 682 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG); 683 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG); 684 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG); 685 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG); 686 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); 687 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG); 688 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); 689 SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG); 690 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG); 691 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG); 692 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG); 693 SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG); 694 SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG); 695 SDValue LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG); 696 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG); 697 698 SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG); 699 SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG); 700 SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG); 701 702 virtual SDValue 703 LowerFormalArguments(SDValue Chain, 704 CallingConv::ID CallConv, bool isVarArg, 705 const SmallVectorImpl<ISD::InputArg> &Ins, 706 DebugLoc dl, SelectionDAG &DAG, 707 SmallVectorImpl<SDValue> &InVals); 708 virtual SDValue 709 LowerCall(SDValue Chain, SDValue Callee, 710 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, 711 const SmallVectorImpl<ISD::OutputArg> &Outs, 712 const SmallVectorImpl<ISD::InputArg> &Ins, 713 DebugLoc dl, SelectionDAG &DAG, 714 SmallVectorImpl<SDValue> &InVals); 715 716 virtual SDValue 717 LowerReturn(SDValue Chain, 718 CallingConv::ID CallConv, bool isVarArg, 719 const SmallVectorImpl<ISD::OutputArg> &Outs, 720 DebugLoc dl, SelectionDAG &DAG); 721 722 virtual bool 723 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg, 724 const SmallVectorImpl<EVT> &OutTys, 725 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags, 726 SelectionDAG &DAG); 727 728 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results, 729 SelectionDAG &DAG, unsigned NewOp); 730 731 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, 732 SDValue Chain, 733 SDValue Dst, SDValue Src, 734 SDValue Size, unsigned Align, 735 const Value *DstSV, uint64_t DstSVOff); 736 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 737 SDValue Chain, 738 SDValue Dst, SDValue Src, 739 SDValue Size, unsigned Align, 740 bool AlwaysInline, 741 const Value *DstSV, uint64_t DstSVOff, 742 const Value *SrcSV, uint64_t SrcSVOff); 743 744 /// Utility function to emit string processing sse4.2 instructions 745 /// that return in xmm0. 746 /// This takes the instruction to expand, the associated machine basic 747 /// block, the number of args, and whether or not the second arg is 748 /// in memory or not. 749 MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, 750 unsigned argNum, bool inMem) const; 751 752 /// Utility function to emit atomic bitwise operations (and, or, xor). 753 /// It takes the bitwise instruction to expand, the associated machine basic 754 /// block, and the associated X86 opcodes for reg/reg and reg/imm. 755 MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter( 756 MachineInstr *BInstr, 757 MachineBasicBlock *BB, 758 unsigned regOpc, 759 unsigned immOpc, 760 unsigned loadOpc, 761 unsigned cxchgOpc, 762 unsigned copyOpc, 763 unsigned notOpc, 764 unsigned EAXreg, 765 TargetRegisterClass *RC, 766 bool invSrc = false) const; 767 768 MachineBasicBlock *EmitAtomicBit6432WithCustomInserter( 769 MachineInstr *BInstr, 770 MachineBasicBlock *BB, 771 unsigned regOpcL, 772 unsigned regOpcH, 773 unsigned immOpcL, 774 unsigned immOpcH, 775 bool invSrc = false) const; 776 777 /// Utility function to emit atomic min and max. It takes the min/max 778 /// instruction to expand, the associated basic block, and the associated 779 /// cmov opcode for moving the min or max value. 780 MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr, 781 MachineBasicBlock *BB, 782 unsigned cmovOpc) const; 783 784 /// Utility function to emit the xmm reg save portion of va_start. 785 MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 786 MachineInstr *BInstr, 787 MachineBasicBlock *BB) const; 788 789 MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 790 MachineBasicBlock *BB, 791 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const; 792 793 /// Emit nodes that will be selected as "test Op0,Op0", or something 794 /// equivalent, for use with the given x86 condition code. 795 SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG); 796 797 /// Emit nodes that will be selected as "cmp Op0,Op1", or something 798 /// equivalent, for use with the given x86 condition code. 799 SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 800 SelectionDAG &DAG); 801 }; 802 803 namespace X86 { 804 FastISel *createFastISel(MachineFunction &mf, 805 MachineModuleInfo *mmi, DwarfWriter *dw, 806 DenseMap<const Value *, unsigned> &, 807 DenseMap<const BasicBlock *, MachineBasicBlock *> &, 808 DenseMap<const AllocaInst *, int> & 809#ifndef NDEBUG 810 , SmallSet<Instruction*, 8> & 811#endif 812 ); 813 } 814} 815 816#endif // X86ISELLOWERING_H 817