1193323Sed//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines the interfaces that X86 uses to lower LLVM code into a 11193323Sed// selection DAG. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#ifndef X86ISELLOWERING_H 16193323Sed#define X86ISELLOWERING_H 17193323Sed 18249423Sdim#include "X86MachineFunctionInfo.h" 19249423Sdim#include "X86RegisterInfo.h" 20193323Sed#include "X86Subtarget.h" 21249423Sdim#include "llvm/CodeGen/CallingConvLower.h" 22249423Sdim#include "llvm/CodeGen/FastISel.h" 23249423Sdim#include "llvm/CodeGen/SelectionDAG.h" 24193323Sed#include "llvm/Target/TargetLowering.h" 25203954Srdivacky#include "llvm/Target/TargetOptions.h" 26193323Sed 27193323Sednamespace llvm { 28193323Sed namespace X86ISD { 29193323Sed // X86 Specific DAG Nodes 30193323Sed enum NodeType { 31193323Sed // Start the numbering where the builtin ops leave off. 32193323Sed FIRST_NUMBER = ISD::BUILTIN_OP_END, 33193323Sed 34193323Sed /// BSF - Bit scan forward. 35193323Sed /// BSR - Bit scan reverse. 36193323Sed BSF, 37193323Sed BSR, 38193323Sed 39193323Sed /// SHLD, SHRD - Double shift instructions. These correspond to 40193323Sed /// X86::SHLDxx and X86::SHRDxx instructions. 41193323Sed SHLD, 42193323Sed SHRD, 43193323Sed 44193323Sed /// FAND - Bitwise logical AND of floating point values. This corresponds 45193323Sed /// to X86::ANDPS or X86::ANDPD. 46193323Sed FAND, 47193323Sed 48193323Sed /// FOR - Bitwise logical OR of floating point values. This corresponds 49193323Sed /// to X86::ORPS or X86::ORPD. 50193323Sed FOR, 51193323Sed 52193323Sed /// FXOR - Bitwise logical XOR of floating point values. This corresponds 53193323Sed /// to X86::XORPS or X86::XORPD. 54193323Sed FXOR, 55193323Sed 56263508Sdim /// FANDN - Bitwise logical ANDNOT of floating point values. This 57263508Sdim /// corresponds to X86::ANDNPS or X86::ANDNPD. 58263508Sdim FANDN, 59263508Sdim 60193323Sed /// FSRL - Bitwise logical right shift of floating point values. These 61193323Sed /// corresponds to X86::PSRLDQ. 62193323Sed FSRL, 63193323Sed 64198090Srdivacky /// CALL - These operations represent an abstract X86 call 65193323Sed /// instruction, which includes a bunch of information. In particular the 66193323Sed /// operands of these node are: 67193323Sed /// 68193323Sed /// #0 - The incoming token chain 69193323Sed /// #1 - The callee 70193323Sed /// #2 - The number of arg bytes the caller pushes on the stack. 71193323Sed /// #3 - The number of arg bytes the callee pops off the stack. 72193323Sed /// #4 - The value to pass in AL/AX/EAX (optional) 73193323Sed /// #5 - The value to pass in DL/DX/EDX (optional) 74193323Sed /// 75193323Sed /// The result values of these nodes are: 76193323Sed /// 77193323Sed /// #0 - The outgoing token chain 78193323Sed /// #1 - The first register result value (optional) 79193323Sed /// #2 - The second register result value (optional) 80193323Sed /// 81193323Sed CALL, 82198090Srdivacky 83218893Sdim /// RDTSC_DAG - This operation implements the lowering for 84193323Sed /// readcyclecounter 85193323Sed RDTSC_DAG, 86193323Sed 87193323Sed /// X86 compare and logical compare instructions. 88193323Sed CMP, COMI, UCOMI, 89193323Sed 90193323Sed /// X86 bit-test instructions. 91193323Sed BT, 92193323Sed 93218893Sdim /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS 94218893Sdim /// operand, usually produced by a CMP instruction. 95193323Sed SETCC, 96193323Sed 97200581Srdivacky // Same as SETCC except it's materialized with a sbb and the value is all 98200581Srdivacky // one's or all zero's. 99218893Sdim SETCC_CARRY, // R = carry_bit ? ~0 : 0 100200581Srdivacky 101223017Sdim /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. 102223017Sdim /// Operands are two FP values to compare; result is a mask of 103223017Sdim /// 0s or 1s. Generally DTRT for C/C++ with NaNs. 104223017Sdim FSETCCss, FSETCCsd, 105223017Sdim 106223017Sdim /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, 107223017Sdim /// result in an integer GPR. Needs masking for scalar result. 108223017Sdim FGETSIGNx86, 109223017Sdim 110193323Sed /// X86 conditional moves. Operand 0 and operand 1 are the two values 111193323Sed /// to select from. Operand 2 is the condition code, and operand 3 is the 112193323Sed /// flag operand produced by a CMP or TEST instruction. It also writes a 113193323Sed /// flag result. 114193323Sed CMOV, 115193323Sed 116193323Sed /// X86 conditional branches. Operand 0 is the chain operand, operand 1 117193323Sed /// is the block to branch if condition is true, operand 2 is the 118193323Sed /// condition code, and operand 3 is the flag operand produced by a CMP 119193323Sed /// or TEST instruction. 120193323Sed BRCOND, 121193323Sed 122193323Sed /// Return with a flag operand. Operand 0 is the chain operand, operand 123193323Sed /// 1 is the number of bytes of stack to pop. 124193323Sed RET_FLAG, 125193323Sed 126193323Sed /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx. 127193323Sed REP_STOS, 128193323Sed 129193323Sed /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx. 130193323Sed REP_MOVS, 131193323Sed 132193323Sed /// GlobalBaseReg - On Darwin, this node represents the result of the popl 133193323Sed /// at function entry, used for PIC code. 134193323Sed GlobalBaseReg, 135193323Sed 136193323Sed /// Wrapper - A wrapper node for TargetConstantPool, 137193323Sed /// TargetExternalSymbol, and TargetGlobalAddress. 138193323Sed Wrapper, 139193323Sed 140193323Sed /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP 141193323Sed /// relative displacements. 142193323Sed WrapperRIP, 143193323Sed 144218893Sdim /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector 145218893Sdim /// to an MMX vector. If you think this is too close to the previous 146218893Sdim /// mnemonic, so do I; blame Intel. 147218893Sdim MOVDQ2Q, 148218893Sdim 149243830Sdim /// MMX_MOVD2W - Copies a 32-bit value from the low word of a MMX 150243830Sdim /// vector to a GPR. 151243830Sdim MMX_MOVD2W, 152243830Sdim 153193323Sed /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to 154193323Sed /// i32, corresponds to X86::PEXTRB. 155193323Sed PEXTRB, 156193323Sed 157193323Sed /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to 158193323Sed /// i32, corresponds to X86::PEXTRW. 159193323Sed PEXTRW, 160193323Sed 161193323Sed /// INSERTPS - Insert any element of a 4 x float vector into any element 162193323Sed /// of a destination 4 x floatvector. 163193323Sed INSERTPS, 164193323Sed 165193323Sed /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector, 166193323Sed /// corresponds to X86::PINSRB. 167193323Sed PINSRB, 168193323Sed 169193323Sed /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector, 170193323Sed /// corresponds to X86::PINSRW. 171204642Srdivacky PINSRW, MMX_PINSRW, 172193323Sed 173193323Sed /// PSHUFB - Shuffle 16 8-bit values within a vector. 174193323Sed PSHUFB, 175219077Sdim 176224145Sdim /// ANDNP - Bitwise Logical AND NOT of Packed FP values. 177224145Sdim ANDNP, 178219077Sdim 179234353Sdim /// PSIGN - Copy integer sign. 180234353Sdim PSIGN, 181219077Sdim 182249423Sdim /// BLENDV - Blend where the selector is a register. 183226633Sdim BLENDV, 184219077Sdim 185249423Sdim /// BLENDI - Blend where the selector is an immediate. 186249423Sdim BLENDI, 187234353Sdim 188249423Sdim // SUBUS - Integer sub with unsigned saturation. 189249423Sdim SUBUS, 190249423Sdim 191234353Sdim /// HADD - Integer horizontal add. 192234353Sdim HADD, 193234353Sdim 194234353Sdim /// HSUB - Integer horizontal sub. 195234353Sdim HSUB, 196234353Sdim 197226633Sdim /// FHADD - Floating point horizontal add. 198226633Sdim FHADD, 199226633Sdim 200226633Sdim /// FHSUB - Floating point horizontal sub. 201226633Sdim FHSUB, 202226633Sdim 203249423Sdim /// UMAX, UMIN - Unsigned integer max and min. 204249423Sdim UMAX, UMIN, 205249423Sdim 206249423Sdim /// SMAX, SMIN - Signed integer max and min. 207249423Sdim SMAX, SMIN, 208249423Sdim 209193323Sed /// FMAX, FMIN - Floating point max and min. 210193323Sed /// 211193323Sed FMAX, FMIN, 212193323Sed 213243830Sdim /// FMAXC, FMINC - Commutative FMIN and FMAX. 214243830Sdim FMAXC, FMINC, 215243830Sdim 216193323Sed /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal 217193323Sed /// approximation. Note that these typically require refinement 218193323Sed /// in order to obtain suitable precision. 219193323Sed FRSQRT, FRCP, 220193323Sed 221193323Sed // TLSADDR - Thread Local Storage. 222193323Sed TLSADDR, 223218893Sdim 224239462Sdim // TLSBASEADDR - Thread Local Storage. A call to get the start address 225239462Sdim // of the TLS block for the current module. 226239462Sdim TLSBASEADDR, 227239462Sdim 228210299Sed // TLSCALL - Thread Local Storage. When calling to an OS provided 229210299Sed // thunk at the address from an earlier relocation. 230210299Sed TLSCALL, 231193323Sed 232193323Sed // EH_RETURN - Exception Handling helpers. 233193323Sed EH_RETURN, 234218893Sdim 235243830Sdim // EH_SJLJ_SETJMP - SjLj exception handling setjmp. 236243830Sdim EH_SJLJ_SETJMP, 237243830Sdim 238243830Sdim // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. 239243830Sdim EH_SJLJ_LONGJMP, 240243830Sdim 241249423Sdim /// TC_RETURN - Tail call return. See X86TargetLowering::LowerCall for 242249423Sdim /// the list of operands. 243193323Sed TC_RETURN, 244193323Sed 245193323Sed // VZEXT_MOVL - Vector move low and zero extend. 246193323Sed VZEXT_MOVL, 247193323Sed 248234353Sdim // VSEXT_MOVL - Vector move low and sign extend. 249234353Sdim VSEXT_MOVL, 250193323Sed 251243830Sdim // VZEXT - Vector integer zero-extend. 252243830Sdim VZEXT, 253243830Sdim 254243830Sdim // VSEXT - Vector integer signed-extend. 255243830Sdim VSEXT, 256243830Sdim 257263508Sdim // VTRUNC - Vector integer truncate. 258263508Sdim VTRUNC, 259263508Sdim 260263508Sdim // VTRUNC - Vector integer truncate with mask. 261263508Sdim VTRUNCM, 262263508Sdim 263239462Sdim // VFPEXT - Vector FP extend. 264239462Sdim VFPEXT, 265239462Sdim 266243830Sdim // VFPROUND - Vector FP round. 267243830Sdim VFPROUND, 268243830Sdim 269234353Sdim // VSHL, VSRL - 128-bit vector logical left / right shift 270234353Sdim VSHLDQ, VSRLDQ, 271218893Sdim 272234353Sdim // VSHL, VSRL, VSRA - Vector shift elements 273234353Sdim VSHL, VSRL, VSRA, 274234353Sdim 275234353Sdim // VSHLI, VSRLI, VSRAI - Vector shift elements by immediate 276234353Sdim VSHLI, VSRLI, VSRAI, 277234353Sdim 278234353Sdim // CMPP - Vector packed double/float comparison. 279234353Sdim CMPP, 280234353Sdim 281193323Sed // PCMP* - Vector integer comparisons. 282234353Sdim PCMPEQ, PCMPGT, 283263508Sdim // PCMP*M - Vector integer comparisons, the result is in a mask vector. 284263508Sdim PCMPEQM, PCMPGTM, 285193323Sed 286263508Sdim /// CMPM, CMPMU - Vector comparison generating mask bits for fp and 287263508Sdim /// integer signed and unsigned data types. 288263508Sdim CMPM, 289263508Sdim CMPMU, 290263508Sdim 291218893Sdim // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results. 292218893Sdim ADD, SUB, ADC, SBB, SMUL, 293198090Srdivacky INC, DEC, OR, XOR, AND, 294219077Sdim 295234353Sdim BLSI, // BLSI - Extract lowest set isolated bit 296234353Sdim BLSMSK, // BLSMSK - Get mask up to lowest set bit 297234353Sdim BLSR, // BLSR - Reset lowest set bit 298263508Sdim BZHI, // BZHI - Zero high bits 299263508Sdim BEXTR, // BEXTR - Bit field extract 300234353Sdim 301218893Sdim UMUL, // LOW, HI, FLAGS = umul LHS, RHS 302193323Sed 303193323Sed // MUL_IMM - X86 specific multiply by immediate. 304198090Srdivacky MUL_IMM, 305218893Sdim 306263508Sdim // PTEST - Vector bitwise comparisons. 307198090Srdivacky PTEST, 308198090Srdivacky 309263508Sdim // TESTP - Vector packed fp sign bitwise comparisons. 310212904Sdim TESTP, 311212904Sdim 312263508Sdim // TESTM - Vector "test" in AVX-512, the result is in a mask vector. 313263508Sdim TESTM, 314263508Sdim 315263508Sdim // OR/AND test for masks 316263508Sdim KORTEST, 317263508Sdim KTEST, 318263508Sdim 319212904Sdim // Several flavors of instructions with vector shuffle behaviors. 320249423Sdim PALIGNR, 321212904Sdim PSHUFD, 322212904Sdim PSHUFHW, 323212904Sdim PSHUFLW, 324234353Sdim SHUFP, 325212904Sdim MOVDDUP, 326212904Sdim MOVSHDUP, 327212904Sdim MOVSLDUP, 328212904Sdim MOVLHPS, 329212904Sdim MOVLHPD, 330212904Sdim MOVHLPS, 331212904Sdim MOVLPS, 332212904Sdim MOVLPD, 333212904Sdim MOVSD, 334212904Sdim MOVSS, 335234353Sdim UNPCKL, 336234353Sdim UNPCKH, 337234353Sdim VPERMILP, 338234982Sdim VPERMV, 339263508Sdim VPERMV3, 340234982Sdim VPERMI, 341234353Sdim VPERM2X128, 342226633Sdim VBROADCAST, 343263508Sdim // masked broadcast 344263508Sdim VBROADCASTM, 345263508Sdim VINSERT, 346212904Sdim 347234353Sdim // PMULUDQ - Vector multiply packed unsigned doubleword integers 348234353Sdim PMULUDQ, 349234353Sdim 350239462Sdim // FMA nodes 351239462Sdim FMADD, 352239462Sdim FNMADD, 353239462Sdim FMSUB, 354239462Sdim FNMSUB, 355239462Sdim FMADDSUB, 356239462Sdim FMSUBADD, 357239462Sdim 358198090Srdivacky // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, 359198090Srdivacky // according to %al. An operator is needed so that this can be expanded 360198090Srdivacky // with control flow. 361198090Srdivacky VASTART_SAVE_XMM_REGS, 362198090Srdivacky 363218893Sdim // WIN_ALLOCA - Windows's _chkstk call to do stack probing. 364218893Sdim WIN_ALLOCA, 365204961Srdivacky 366226633Sdim // SEG_ALLOCA - For allocating variable amounts of stack space when using 367226633Sdim // segmented stacks. Check if the current stacklet has enough space, and 368226633Sdim // falls back to heap allocation if not. 369226633Sdim SEG_ALLOCA, 370226633Sdim 371234353Sdim // WIN_FTOL - Windows's _ftol2 runtime routine to do fptoui. 372234353Sdim WIN_FTOL, 373234353Sdim 374218893Sdim // Memory barrier 375218893Sdim MEMBARRIER, 376218893Sdim MFENCE, 377218893Sdim SFENCE, 378218893Sdim LFENCE, 379218893Sdim 380239462Sdim // FNSTSW16r - Store FP status word into i16 register. 381239462Sdim FNSTSW16r, 382239462Sdim 383239462Sdim // SAHF - Store contents of %ah into %eflags. 384239462Sdim SAHF, 385239462Sdim 386239462Sdim // RDRAND - Get a random integer and indicate whether it is valid in CF. 387239462Sdim RDRAND, 388239462Sdim 389249423Sdim // RDSEED - Get a NIST SP800-90B & C compliant random integer and 390249423Sdim // indicate whether it is valid in CF. 391249423Sdim RDSEED, 392249423Sdim 393239462Sdim // PCMP*STRI 394239462Sdim PCMPISTRI, 395239462Sdim PCMPESTRI, 396239462Sdim 397249423Sdim // XTEST - Test if in transactional execution. 398249423Sdim XTEST, 399249423Sdim 400218893Sdim // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, 401218893Sdim // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - 402198090Srdivacky // Atomic 64-bit binary operations. 403198090Srdivacky ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 404198090Srdivacky ATOMSUB64_DAG, 405198090Srdivacky ATOMOR64_DAG, 406198090Srdivacky ATOMXOR64_DAG, 407198090Srdivacky ATOMAND64_DAG, 408198090Srdivacky ATOMNAND64_DAG, 409243830Sdim ATOMMAX64_DAG, 410243830Sdim ATOMMIN64_DAG, 411243830Sdim ATOMUMAX64_DAG, 412243830Sdim ATOMUMIN64_DAG, 413212904Sdim ATOMSWAP64_DAG, 414204961Srdivacky 415226633Sdim // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap. 416218893Sdim LCMPXCHG_DAG, 417218893Sdim LCMPXCHG8_DAG, 418226633Sdim LCMPXCHG16_DAG, 419218893Sdim 420218893Sdim // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. 421218893Sdim VZEXT_LOAD, 422218893Sdim 423218893Sdim // FNSTCW16m - Store FP control world into i16 memory. 424218893Sdim FNSTCW16m, 425218893Sdim 426218893Sdim /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the 427218893Sdim /// integer destination in memory and a FP reg source. This corresponds 428218893Sdim /// to the X86::FIST*m instructions and the rounding mode change stuff. It 429218893Sdim /// has two inputs (token chain and address) and two outputs (int value 430218893Sdim /// and token chain). 431218893Sdim FP_TO_INT16_IN_MEM, 432218893Sdim FP_TO_INT32_IN_MEM, 433218893Sdim FP_TO_INT64_IN_MEM, 434218893Sdim 435218893Sdim /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the 436218893Sdim /// integer source in memory and FP reg result. This corresponds to the 437218893Sdim /// X86::FILD*m instructions. It has three inputs (token chain, address, 438218893Sdim /// and source type) and two outputs (FP value and token chain). FILD_FLAG 439218893Sdim /// also produces a flag). 440218893Sdim FILD, 441218893Sdim FILD_FLAG, 442218893Sdim 443218893Sdim /// FLD - This instruction implements an extending load to FP stack slots. 444218893Sdim /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 445218893Sdim /// operand, ptr to load from, and a ValueType node indicating the type 446218893Sdim /// to load to. 447218893Sdim FLD, 448218893Sdim 449218893Sdim /// FST - This instruction implements a truncating store to FP stack 450218893Sdim /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 451218893Sdim /// chain operand, value to store, address, and a ValueType to store it 452218893Sdim /// as. 453218893Sdim FST, 454218893Sdim 455218893Sdim /// VAARG_64 - This instruction grabs the address of the next argument 456218893Sdim /// from a va_list. (reads and modifies the va_list in memory) 457218893Sdim VAARG_64 458218893Sdim 459204961Srdivacky // WARNING: Do not add anything in the end unless you want the node to 460204961Srdivacky // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be 461204961Srdivacky // thought as target memory ops! 462193323Sed }; 463193323Sed } 464193323Sed 465193323Sed /// Define some predicates that are used for node matching. 466193323Sed namespace X86 { 467263508Sdim /// isVEXTRACT128Index - Return true if the specified 468218893Sdim /// EXTRACT_SUBVECTOR operand specifies a vector extract that is 469263508Sdim /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions. 470263508Sdim bool isVEXTRACT128Index(SDNode *N); 471218893Sdim 472263508Sdim /// isVINSERT128Index - Return true if the specified 473218893Sdim /// INSERT_SUBVECTOR operand specifies a subvector insert that is 474263508Sdim /// suitable for input to VINSERTF128, VINSERTI128 instructions. 475263508Sdim bool isVINSERT128Index(SDNode *N); 476218893Sdim 477263508Sdim /// isVEXTRACT256Index - Return true if the specified 478263508Sdim /// EXTRACT_SUBVECTOR operand specifies a vector extract that is 479263508Sdim /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions. 480263508Sdim bool isVEXTRACT256Index(SDNode *N); 481263508Sdim 482263508Sdim /// isVINSERT256Index - Return true if the specified 483263508Sdim /// INSERT_SUBVECTOR operand specifies a subvector insert that is 484263508Sdim /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions. 485263508Sdim bool isVINSERT256Index(SDNode *N); 486263508Sdim 487263508Sdim /// getExtractVEXTRACT128Immediate - Return the appropriate 488218893Sdim /// immediate to extract the specified EXTRACT_SUBVECTOR index 489263508Sdim /// with VEXTRACTF128, VEXTRACTI128 instructions. 490263508Sdim unsigned getExtractVEXTRACT128Immediate(SDNode *N); 491218893Sdim 492263508Sdim /// getInsertVINSERT128Immediate - Return the appropriate 493218893Sdim /// immediate to insert at the specified INSERT_SUBVECTOR index 494263508Sdim /// with VINSERTF128, VINSERT128 instructions. 495263508Sdim unsigned getInsertVINSERT128Immediate(SDNode *N); 496218893Sdim 497263508Sdim /// getExtractVEXTRACT256Immediate - Return the appropriate 498263508Sdim /// immediate to extract the specified EXTRACT_SUBVECTOR index 499263508Sdim /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions. 500263508Sdim unsigned getExtractVEXTRACT256Immediate(SDNode *N); 501263508Sdim 502263508Sdim /// getInsertVINSERT256Immediate - Return the appropriate 503263508Sdim /// immediate to insert at the specified INSERT_SUBVECTOR index 504263508Sdim /// with VINSERTF64x4, VINSERTI64x4 instructions. 505263508Sdim unsigned getInsertVINSERT256Immediate(SDNode *N); 506263508Sdim 507198090Srdivacky /// isZeroNode - Returns true if Elt is a constant zero or a floating point 508198090Srdivacky /// constant +0.0. 509198090Srdivacky bool isZeroNode(SDValue Elt); 510198090Srdivacky 511198090Srdivacky /// isOffsetSuitableForCodeModel - Returns true of the given offset can be 512198090Srdivacky /// fit into displacement field of the instruction. 513198090Srdivacky bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 514198090Srdivacky bool hasSymbolicDisplacement = true); 515224145Sdim 516224145Sdim 517224145Sdim /// isCalleePop - Determines whether the callee is required to pop its 518224145Sdim /// own arguments. Callee pop is necessary to support tail calls. 519224145Sdim bool isCalleePop(CallingConv::ID CallingConv, 520224145Sdim bool is64Bit, bool IsVarArg, bool TailCallOpt); 521193323Sed } 522193323Sed 523193323Sed //===--------------------------------------------------------------------===// 524193323Sed // X86TargetLowering - X86 Implementation of the TargetLowering interface 525193323Sed class X86TargetLowering : public TargetLowering { 526193323Sed public: 527193323Sed explicit X86TargetLowering(X86TargetMachine &TM); 528193323Sed 529203954Srdivacky virtual unsigned getJumpTableEncoding() const; 530203954Srdivacky 531249423Sdim virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; } 532219077Sdim 533203954Srdivacky virtual const MCExpr * 534203954Srdivacky LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 535203954Srdivacky const MachineBasicBlock *MBB, unsigned uid, 536203954Srdivacky MCContext &Ctx) const; 537218893Sdim 538193323Sed /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 539193323Sed /// jumptable. 540203954Srdivacky virtual SDValue getPICJumpTableRelocBase(SDValue Table, 541203954Srdivacky SelectionDAG &DAG) const; 542203954Srdivacky virtual const MCExpr * 543203954Srdivacky getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 544203954Srdivacky unsigned JTI, MCContext &Ctx) const; 545218893Sdim 546193323Sed /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 547193323Sed /// function arguments in the caller parameter area. For X86, aggregates 548193323Sed /// that contains are placed at 16-byte boundaries while the rest are at 549193323Sed /// 4-byte boundaries. 550226633Sdim virtual unsigned getByValTypeAlignment(Type *Ty) const; 551193323Sed 552193323Sed /// getOptimalMemOpType - Returns the target specific optimal type for load 553206124Srdivacky /// and store operations as a result of memset, memcpy, and memmove 554206124Srdivacky /// lowering. If DstAlign is zero that means it's safe to destination 555206124Srdivacky /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 556206124Srdivacky /// means there isn't a need to check it against alignment requirement, 557249423Sdim /// probably because the source does not need to be loaded. If 'IsMemset' is 558249423Sdim /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 559249423Sdim /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 560249423Sdim /// source is constant so it does not need to be loaded. 561207618Srdivacky /// It returns EVT::Other if the type should be determined using generic 562207618Srdivacky /// target-independent logic. 563206124Srdivacky virtual EVT 564263508Sdim getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 565249423Sdim bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 566207618Srdivacky MachineFunction &MF) const; 567195340Sed 568249423Sdim /// isSafeMemOpType - Returns true if it's safe to use load / store of the 569249423Sdim /// specified type to expand memcpy / memset inline. This is mostly true 570249423Sdim /// for all types except for some special cases. For example, on X86 571249423Sdim /// targets without SSE2 f64 load / store are done with fldl / fstpl which 572249423Sdim /// also does type conversion. Note the specified type doesn't have to be 573249423Sdim /// legal as the hook is used before type legalization. 574249423Sdim virtual bool isSafeMemOpType(MVT VT) const; 575249423Sdim 576198090Srdivacky /// allowsUnalignedMemoryAccesses - Returns true if the target allows 577249423Sdim /// unaligned memory accesses. of the specified type. Returns whether it 578249423Sdim /// is "fast" by reference in the second argument. 579249423Sdim virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const; 580198090Srdivacky 581193323Sed /// LowerOperation - Provide custom lowering hooks for some operations. 582193323Sed /// 583207618Srdivacky virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 584193323Sed 585193323Sed /// ReplaceNodeResults - Replace the results of node with an illegal result 586193323Sed /// type with new values built out of custom code. 587193323Sed /// 588193323Sed virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 589207618Srdivacky SelectionDAG &DAG) const; 590193323Sed 591218893Sdim 592193323Sed virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 593193323Sed 594207618Srdivacky /// isTypeDesirableForOp - Return true if the target has native support for 595207618Srdivacky /// the specified value type and it is 'desirable' to use the type for the 596207618Srdivacky /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 597207618Srdivacky /// instruction encodings are longer and some i16 instructions are slow. 598207618Srdivacky virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const; 599193323Sed 600207618Srdivacky /// isTypeDesirable - Return true if the target has native support for the 601207618Srdivacky /// specified value type and it is 'desirable' to use the type. e.g. On x86 602207618Srdivacky /// i16 is legal, but undesirable since i16 instruction encodings are longer 603207618Srdivacky /// and some i16 instructions are slow. 604207618Srdivacky virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const; 605207618Srdivacky 606207618Srdivacky virtual MachineBasicBlock * 607207618Srdivacky EmitInstrWithCustomInserter(MachineInstr *MI, 608207618Srdivacky MachineBasicBlock *MBB) const; 609207618Srdivacky 610218893Sdim 611193323Sed /// getTargetNodeName - This method returns the name of a target specific 612193323Sed /// DAG node. 613193323Sed virtual const char *getTargetNodeName(unsigned Opcode) const; 614193323Sed 615226633Sdim /// getSetCCResultType - Return the value type to use for ISD::SETCC. 616263508Sdim virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 617193323Sed 618218893Sdim /// computeMaskedBitsForTargetNode - Determine which of the bits specified 619218893Sdim /// in Mask are known to be either zero or one and return them in the 620193323Sed /// KnownZero/KnownOne bitsets. 621193323Sed virtual void computeMaskedBitsForTargetNode(const SDValue Op, 622218893Sdim APInt &KnownZero, 623193323Sed APInt &KnownOne, 624193323Sed const SelectionDAG &DAG, 625193323Sed unsigned Depth = 0) const; 626193323Sed 627218893Sdim // ComputeNumSignBitsForTargetNode - Determine the number of bits in the 628218893Sdim // operation that are sign bits. 629218893Sdim virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 630218893Sdim unsigned Depth) const; 631218893Sdim 632193323Sed virtual bool 633207618Srdivacky isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; 634218893Sdim 635207618Srdivacky SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 636193323Sed 637198090Srdivacky virtual bool ExpandInlineAsm(CallInst *CI) const; 638218893Sdim 639193323Sed ConstraintType getConstraintType(const std::string &Constraint) const; 640218893Sdim 641218893Sdim /// Examine constraint string and operand type and determine a weight value. 642218893Sdim /// The operand object must already have been set up with the operand type. 643218893Sdim virtual ConstraintWeight getSingleConstraintMatchWeight( 644218893Sdim AsmOperandInfo &info, const char *constraint) const; 645218893Sdim 646198090Srdivacky virtual const char *LowerXConstraint(EVT ConstraintVT) const; 647193323Sed 648193323Sed /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 649193323Sed /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 650193323Sed /// true it means one of the asm constraint of the inline asm instruction 651193323Sed /// being processed is 'm'. 652193323Sed virtual void LowerAsmOperandForConstraint(SDValue Op, 653223017Sdim std::string &Constraint, 654193323Sed std::vector<SDValue> &Ops, 655193323Sed SelectionDAG &DAG) const; 656218893Sdim 657193323Sed /// getRegForInlineAsmConstraint - Given a physical register constraint 658193323Sed /// (e.g. {edx}), return the register number and the register class for the 659193323Sed /// register. This should only be used for C_Register constraints. On 660193323Sed /// error, this returns a register number of 0. 661218893Sdim std::pair<unsigned, const TargetRegisterClass*> 662193323Sed getRegForInlineAsmConstraint(const std::string &Constraint, 663263508Sdim MVT VT) const; 664218893Sdim 665193323Sed /// isLegalAddressingMode - Return true if the addressing mode represented 666193323Sed /// by AM is legal for this target, for a load/store of the specified type. 667226633Sdim virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 668193323Sed 669239462Sdim /// isLegalICmpImmediate - Return true if the specified immediate is legal 670239462Sdim /// icmp immediate, that is the target has icmp instructions which can 671239462Sdim /// compare a register against the immediate without having to materialize 672239462Sdim /// the immediate into a register. 673239462Sdim virtual bool isLegalICmpImmediate(int64_t Imm) const; 674239462Sdim 675239462Sdim /// isLegalAddImmediate - Return true if the specified immediate is legal 676239462Sdim /// add immediate, that is the target has add instructions which can 677239462Sdim /// add a register and the immediate without having to materialize 678239462Sdim /// the immediate into a register. 679239462Sdim virtual bool isLegalAddImmediate(int64_t Imm) const; 680239462Sdim 681193323Sed /// isTruncateFree - Return true if it's free to truncate a value of 682193323Sed /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 683193323Sed /// register EAX to i16 by referencing its sub-register AX. 684226633Sdim virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; 685198090Srdivacky virtual bool isTruncateFree(EVT VT1, EVT VT2) const; 686193323Sed 687263508Sdim virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const; 688263508Sdim 689193323Sed /// isZExtFree - Return true if any actual instruction that defines a 690193323Sed /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 691193323Sed /// register. This does not necessarily include registers defined in 692193323Sed /// unknown ways, such as incoming arguments, or copies from unknown 693193323Sed /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 694193323Sed /// does not necessarily apply to truncate instructions. e.g. on x86-64, 695193323Sed /// all instructions that define 32-bit values implicit zero-extend the 696193323Sed /// result out to 64 bits. 697226633Sdim virtual bool isZExtFree(Type *Ty1, Type *Ty2) const; 698198090Srdivacky virtual bool isZExtFree(EVT VT1, EVT VT2) const; 699249423Sdim virtual bool isZExtFree(SDValue Val, EVT VT2) const; 700193323Sed 701263508Sdim /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 702263508Sdim /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 703263508Sdim /// expanded to FMAs when this method returns true, otherwise fmuladd is 704263508Sdim /// expanded to fmul + fadd. 705263508Sdim virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const; 706239462Sdim 707193323Sed /// isNarrowingProfitable - Return true if it's profitable to narrow 708193323Sed /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 709193323Sed /// from i32 to i8 but not from i32 to i16. 710198090Srdivacky virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; 711193323Sed 712198892Srdivacky /// isFPImmLegal - Returns true if the target can instruction select the 713198892Srdivacky /// specified FP immediate natively. If false, the legalizer will 714198892Srdivacky /// materialize the FP immediate as a load from a constant pool. 715198892Srdivacky virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 716198892Srdivacky 717193323Sed /// isShuffleMaskLegal - Targets can use this to indicate that they only 718193323Sed /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 719193323Sed /// By default, if a target supports the VECTOR_SHUFFLE node, all mask 720193323Sed /// values are assumed to be legal. 721193323Sed virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 722198090Srdivacky EVT VT) const; 723193323Sed 724193323Sed /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is 725193323Sed /// used by Targets can use this to indicate if there is a suitable 726193323Sed /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant 727193323Sed /// pool entry. 728193323Sed virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 729198090Srdivacky EVT VT) const; 730193323Sed 731193323Sed /// ShouldShrinkFPConstant - If true, then instruction selection should 732193323Sed /// seek to shrink the FP constant of the specified type to a smaller type 733193323Sed /// in order to save space and / or reduce runtime. 734198090Srdivacky virtual bool ShouldShrinkFPConstant(EVT VT) const { 735193323Sed // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 736193323Sed // expensive than a straight movsd. On the other hand, it's important to 737193323Sed // shrink long double fp constant since fldt is very slow. 738193323Sed return !X86ScalarSSEf64 || VT == MVT::f80; 739193323Sed } 740218893Sdim 741208599Srdivacky const X86Subtarget* getSubtarget() const { 742193323Sed return Subtarget; 743193323Sed } 744193323Sed 745193323Sed /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 746193323Sed /// computed in an SSE register, not on the X87 floating point stack. 747198090Srdivacky bool isScalarFPTypeInSSEReg(EVT VT) const { 748193323Sed return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 749193323Sed (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 750193323Sed } 751193323Sed 752234353Sdim /// isTargetFTOL - Return true if the target uses the MSVC _ftol2 routine 753234353Sdim /// for fptoui. 754234353Sdim bool isTargetFTOL() const { 755234353Sdim return Subtarget->isTargetWindows() && !Subtarget->is64Bit(); 756234353Sdim } 757234353Sdim 758234353Sdim /// isIntegerTypeFTOL - Return true if the MSVC _ftol2 routine should be 759234353Sdim /// used for fptoui to the given type. 760234353Sdim bool isIntegerTypeFTOL(EVT VT) const { 761234353Sdim return isTargetFTOL() && VT == MVT::i64; 762234353Sdim } 763234353Sdim 764193323Sed /// createFastISel - This method returns a target specific FastISel object, 765193323Sed /// or null if the target does not support "fast" ISel. 766239462Sdim virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 767239462Sdim const TargetLibraryInfo *libInfo) const; 768195340Sed 769210299Sed /// getStackCookieLocation - Return true if the target stores stack 770210299Sed /// protector cookies at a fixed offset in some non-standard address 771210299Sed /// space, and populates the address space and offset as 772210299Sed /// appropriate. 773210299Sed virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const; 774210299Sed 775223017Sdim SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 776223017Sdim SelectionDAG &DAG) const; 777223017Sdim 778263508Sdim virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const LLVM_OVERRIDE; 779263508Sdim 780251662Sdim /// \brief Reset the operation actions based on target options. 781251662Sdim virtual void resetOperationActions(); 782251662Sdim 783212904Sdim protected: 784212904Sdim std::pair<const TargetRegisterClass*, uint8_t> 785249423Sdim findRepresentativeClass(MVT VT) const; 786212904Sdim 787193323Sed private: 788193323Sed /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 789193323Sed /// make the right decision when generating code for different targets. 790193323Sed const X86Subtarget *Subtarget; 791243830Sdim const DataLayout *TD; 792193323Sed 793251662Sdim /// Used to store the TargetOptions so that we don't waste time resetting 794251662Sdim /// the operation actions unless we have to. 795251662Sdim TargetOptions TO; 796251662Sdim 797218893Sdim /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 798193323Sed /// floating point ops. 799193323Sed /// When SSE is available, use it for f32 operations. 800193323Sed /// When SSE2 is available, use it for f64 operations. 801193323Sed bool X86ScalarSSEf32; 802193323Sed bool X86ScalarSSEf64; 803193323Sed 804198892Srdivacky /// LegalFPImmediates - A list of legal fp immediates. 805198892Srdivacky std::vector<APFloat> LegalFPImmediates; 806198892Srdivacky 807198892Srdivacky /// addLegalFPImmediate - Indicate that this x86 target can instruction 808198892Srdivacky /// select the specified FP immediate natively. 809198892Srdivacky void addLegalFPImmediate(const APFloat& Imm) { 810198892Srdivacky LegalFPImmediates.push_back(Imm); 811198892Srdivacky } 812198892Srdivacky 813198090Srdivacky SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 814198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 815198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 816263508Sdim SDLoc dl, SelectionDAG &DAG, 817207618Srdivacky SmallVectorImpl<SDValue> &InVals) const; 818198090Srdivacky SDValue LowerMemArgument(SDValue Chain, 819198090Srdivacky CallingConv::ID CallConv, 820198090Srdivacky const SmallVectorImpl<ISD::InputArg> &ArgInfo, 821263508Sdim SDLoc dl, SelectionDAG &DAG, 822198090Srdivacky const CCValAssign &VA, MachineFrameInfo *MFI, 823207618Srdivacky unsigned i) const; 824198090Srdivacky SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 825263508Sdim SDLoc dl, SelectionDAG &DAG, 826198090Srdivacky const CCValAssign &VA, 827207618Srdivacky ISD::ArgFlagsTy Flags) const; 828193323Sed 829193323Sed // Call lowering helpers. 830203954Srdivacky 831203954Srdivacky /// IsEligibleForTailCallOptimization - Check whether the call is eligible 832203954Srdivacky /// for tail call optimization. Targets which want to do tail call 833203954Srdivacky /// optimization should implement this function. 834203954Srdivacky bool IsEligibleForTailCallOptimization(SDValue Callee, 835203954Srdivacky CallingConv::ID CalleeCC, 836203954Srdivacky bool isVarArg, 837205218Srdivacky bool isCalleeStructRet, 838205218Srdivacky bool isCallerStructRet, 839243830Sdim Type *RetTy, 840203954Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 841210299Sed const SmallVectorImpl<SDValue> &OutVals, 842203954Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 843203954Srdivacky SelectionDAG& DAG) const; 844207618Srdivacky bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const; 845193323Sed SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 846193323Sed SDValue Chain, bool IsTailCall, bool Is64Bit, 847263508Sdim int FPDiff, SDLoc dl) const; 848193323Sed 849207618Srdivacky unsigned GetAlignedArgumentStackSize(unsigned StackSize, 850207618Srdivacky SelectionDAG &DAG) const; 851193323Sed 852193323Sed std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 853234353Sdim bool isSigned, 854234353Sdim bool isReplace) const; 855200581Srdivacky 856207618Srdivacky SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 857263508Sdim SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const; 858207618Srdivacky SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 859207618Srdivacky SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 860207618Srdivacky SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 861207618Srdivacky SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 862207618Srdivacky SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 863263508Sdim SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl, 864193323Sed int64_t Offset, SelectionDAG &DAG) const; 865207618Srdivacky SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 866207618Srdivacky SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 867207618Srdivacky SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 868223017Sdim SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const; 869207618Srdivacky SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 870207618Srdivacky SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 871207618Srdivacky SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const; 872207618Srdivacky SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const; 873243830Sdim SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const; 874249423Sdim SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 875207618Srdivacky SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 876207618Srdivacky SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const; 877207618Srdivacky SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; 878207618Srdivacky SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const; 879207618Srdivacky SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 880207618Srdivacky SDValue LowerToBT(SDValue And, ISD::CondCode CC, 881263508Sdim SDLoc dl, SelectionDAG &DAG) const; 882207618Srdivacky SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 883207618Srdivacky SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 884207618Srdivacky SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 885207618Srdivacky SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const; 886207618Srdivacky SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 887207618Srdivacky SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 888207618Srdivacky SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 889207618Srdivacky SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 890207618Srdivacky SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 891207618Srdivacky SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 892207618Srdivacky SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const; 893207618Srdivacky SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 894243830Sdim SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 895243830Sdim SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 896226633Sdim SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 897207618Srdivacky SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 898224145Sdim SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const; 899193323Sed 900198090Srdivacky virtual SDValue 901198090Srdivacky LowerFormalArguments(SDValue Chain, 902198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 903198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 904263508Sdim SDLoc dl, SelectionDAG &DAG, 905207618Srdivacky SmallVectorImpl<SDValue> &InVals) const; 906198090Srdivacky virtual SDValue 907239462Sdim LowerCall(CallLoweringInfo &CLI, 908207618Srdivacky SmallVectorImpl<SDValue> &InVals) const; 909198090Srdivacky 910198090Srdivacky virtual SDValue 911198090Srdivacky LowerReturn(SDValue Chain, 912198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 913198090Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 914210299Sed const SmallVectorImpl<SDValue> &OutVals, 915263508Sdim SDLoc dl, SelectionDAG &DAG) const; 916198090Srdivacky 917234353Sdim virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const; 918218893Sdim 919221345Sdim virtual bool mayBeEmittedAsTailCall(CallInst *CI) const; 920221345Sdim 921249423Sdim virtual MVT 922249423Sdim getTypeForExtArgOrReturn(MVT VT, ISD::NodeType ExtendKind) const; 923221345Sdim 924199481Srdivacky virtual bool 925223017Sdim CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 926239462Sdim bool isVarArg, 927239462Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 928239462Sdim LLVMContext &Context) const; 929199481Srdivacky 930263508Sdim virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const; 931263508Sdim 932243830Sdim /// Utility function to emit atomic-load-arith operations (and, or, xor, 933243830Sdim /// nand, max, min, umax, umin). It takes the corresponding instruction to 934243830Sdim /// expand, the associated machine basic block, and the associated X86 935243830Sdim /// opcodes for reg/reg. 936243830Sdim MachineBasicBlock *EmitAtomicLoadArith(MachineInstr *MI, 937243830Sdim MachineBasicBlock *MBB) const; 938198090Srdivacky 939243830Sdim /// Utility function to emit atomic-load-arith operations (and, or, xor, 940243830Sdim /// nand, add, sub, swap) for 64-bit operands on 32-bit target. 941243830Sdim MachineBasicBlock *EmitAtomicLoadArith6432(MachineInstr *MI, 942243830Sdim MachineBasicBlock *MBB) const; 943218893Sdim 944218893Sdim // Utility function to emit the low-level va_arg code for X86-64. 945218893Sdim MachineBasicBlock *EmitVAARG64WithCustomInserter( 946218893Sdim MachineInstr *MI, 947218893Sdim MachineBasicBlock *MBB) const; 948218893Sdim 949198090Srdivacky /// Utility function to emit the xmm reg save portion of va_start. 950198090Srdivacky MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 951198090Srdivacky MachineInstr *BInstr, 952198090Srdivacky MachineBasicBlock *BB) const; 953198090Srdivacky 954198090Srdivacky MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 955207618Srdivacky MachineBasicBlock *BB) const; 956204961Srdivacky 957218893Sdim MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI, 958207618Srdivacky MachineBasicBlock *BB) const; 959218893Sdim 960226633Sdim MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI, 961226633Sdim MachineBasicBlock *BB, 962226633Sdim bool Is64Bit) const; 963226633Sdim 964210299Sed MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, 965210299Sed MachineBasicBlock *BB) const; 966204961Srdivacky 967218893Sdim MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI, 968218893Sdim MachineBasicBlock *BB) const; 969218893Sdim 970243830Sdim MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, 971243830Sdim MachineBasicBlock *MBB) const; 972243830Sdim 973243830Sdim MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, 974243830Sdim MachineBasicBlock *MBB) const; 975243830Sdim 976193323Sed /// Emit nodes that will be selected as "test Op0,Op0", or something 977193323Sed /// equivalent, for use with the given x86 condition code. 978207618Srdivacky SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const; 979193323Sed 980193323Sed /// Emit nodes that will be selected as "cmp Op0,Op1", or something 981193323Sed /// equivalent, for use with the given x86 condition code. 982193323Sed SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 983207618Srdivacky SelectionDAG &DAG) const; 984239462Sdim 985239462Sdim /// Convert a comparison if required by the subtarget. 986239462Sdim SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const; 987193323Sed }; 988193323Sed 989193323Sed namespace X86 { 990239462Sdim FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 991239462Sdim const TargetLibraryInfo *libInfo); 992193323Sed } 993193323Sed} 994193323Sed 995193323Sed#endif // X86ISELLOWERING_H 996