X86FloatingPoint.cpp revision 203954
1193323Sed//===-- X86FloatingPoint.cpp - Floating point Reg -> Stack converter ------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines the pass which converts floating point instructions from 11193323Sed// virtual registers into register stack instructions. This pass uses live 12193323Sed// variable information to indicate where the FPn registers are used and their 13193323Sed// lifetimes. 14193323Sed// 15193323Sed// This pass is hampered by the lack of decent CFG manipulation routines for 16193323Sed// machine code. In particular, this wants to be able to split critical edges 17193323Sed// as necessary, traverse the machine basic block CFG in depth-first order, and 18193323Sed// allow there to be multiple machine basic blocks for each LLVM basicblock 19193323Sed// (needed for critical edge splitting). 20193323Sed// 21193323Sed// In particular, this pass currently barfs on critical edges. Because of this, 22193323Sed// it requires the instruction selector to insert FP_REG_KILL instructions on 23193323Sed// the exits of any basic block that has critical edges going from it, or which 24193323Sed// branch to a critical basic block. 25193323Sed// 26193323Sed// FIXME: this is not implemented yet. The stackifier pass only works on local 27193323Sed// basic blocks. 28193323Sed// 29193323Sed//===----------------------------------------------------------------------===// 30193323Sed 31193323Sed#define DEBUG_TYPE "x86-codegen" 32193323Sed#include "X86.h" 33193323Sed#include "X86InstrInfo.h" 34198090Srdivacky#include "llvm/ADT/DepthFirstIterator.h" 35198090Srdivacky#include "llvm/ADT/SmallPtrSet.h" 36198090Srdivacky#include "llvm/ADT/SmallVector.h" 37198090Srdivacky#include "llvm/ADT/Statistic.h" 38198090Srdivacky#include "llvm/ADT/STLExtras.h" 39193323Sed#include "llvm/CodeGen/MachineFunctionPass.h" 40193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 41193323Sed#include "llvm/CodeGen/MachineRegisterInfo.h" 42193323Sed#include "llvm/CodeGen/Passes.h" 43198090Srdivacky#include "llvm/Support/Debug.h" 44198090Srdivacky#include "llvm/Support/ErrorHandling.h" 45198090Srdivacky#include "llvm/Support/raw_ostream.h" 46193323Sed#include "llvm/Target/TargetInstrInfo.h" 47193323Sed#include "llvm/Target/TargetMachine.h" 48193323Sed#include <algorithm> 49193323Sedusing namespace llvm; 50193323Sed 51193323SedSTATISTIC(NumFXCH, "Number of fxch instructions inserted"); 52193323SedSTATISTIC(NumFP , "Number of floating point instructions"); 53193323Sed 54193323Sednamespace { 55198892Srdivacky struct FPS : public MachineFunctionPass { 56193323Sed static char ID; 57193323Sed FPS() : MachineFunctionPass(&ID) {} 58193323Sed 59193323Sed virtual void getAnalysisUsage(AnalysisUsage &AU) const { 60198090Srdivacky AU.setPreservesCFG(); 61193323Sed AU.addPreservedID(MachineLoopInfoID); 62193323Sed AU.addPreservedID(MachineDominatorsID); 63193323Sed MachineFunctionPass::getAnalysisUsage(AU); 64193323Sed } 65193323Sed 66193323Sed virtual bool runOnMachineFunction(MachineFunction &MF); 67193323Sed 68193323Sed virtual const char *getPassName() const { return "X86 FP Stackifier"; } 69193323Sed 70193323Sed private: 71193323Sed const TargetInstrInfo *TII; // Machine instruction info. 72193323Sed MachineBasicBlock *MBB; // Current basic block 73193323Sed unsigned Stack[8]; // FP<n> Registers in each stack slot... 74193323Sed unsigned RegMap[8]; // Track which stack slot contains each register 75193323Sed unsigned StackTop; // The current top of the FP stack. 76193323Sed 77193323Sed void dumpStack() const { 78202375Srdivacky dbgs() << "Stack contents:"; 79193323Sed for (unsigned i = 0; i != StackTop; ++i) { 80202375Srdivacky dbgs() << " FP" << Stack[i]; 81193323Sed assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!"); 82193323Sed } 83202375Srdivacky dbgs() << "\n"; 84193323Sed } 85193323Sed private: 86193323Sed /// isStackEmpty - Return true if the FP stack is empty. 87193323Sed bool isStackEmpty() const { 88193323Sed return StackTop == 0; 89193323Sed } 90193323Sed 91193323Sed // getSlot - Return the stack slot number a particular register number is 92193323Sed // in. 93193323Sed unsigned getSlot(unsigned RegNo) const { 94193323Sed assert(RegNo < 8 && "Regno out of range!"); 95193323Sed return RegMap[RegNo]; 96193323Sed } 97193323Sed 98193323Sed // getStackEntry - Return the X86::FP<n> register in register ST(i). 99193323Sed unsigned getStackEntry(unsigned STi) const { 100193323Sed assert(STi < StackTop && "Access past stack top!"); 101193323Sed return Stack[StackTop-1-STi]; 102193323Sed } 103193323Sed 104193323Sed // getSTReg - Return the X86::ST(i) register which contains the specified 105193323Sed // FP<RegNo> register. 106193323Sed unsigned getSTReg(unsigned RegNo) const { 107193323Sed return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; 108193323Sed } 109193323Sed 110193323Sed // pushReg - Push the specified FP<n> register onto the stack. 111193323Sed void pushReg(unsigned Reg) { 112193323Sed assert(Reg < 8 && "Register number out of range!"); 113193323Sed assert(StackTop < 8 && "Stack overflow!"); 114193323Sed Stack[StackTop] = Reg; 115193323Sed RegMap[Reg] = StackTop++; 116193323Sed } 117193323Sed 118193323Sed bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; } 119193323Sed void moveToTop(unsigned RegNo, MachineBasicBlock::iterator I) { 120193323Sed MachineInstr *MI = I; 121193323Sed DebugLoc dl = MI->getDebugLoc(); 122193323Sed if (isAtTop(RegNo)) return; 123193323Sed 124193323Sed unsigned STReg = getSTReg(RegNo); 125193323Sed unsigned RegOnTop = getStackEntry(0); 126193323Sed 127193323Sed // Swap the slots the regs are in. 128193323Sed std::swap(RegMap[RegNo], RegMap[RegOnTop]); 129193323Sed 130193323Sed // Swap stack slot contents. 131193323Sed assert(RegMap[RegOnTop] < StackTop); 132193323Sed std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); 133193323Sed 134193323Sed // Emit an fxch to update the runtime processors version of the state. 135193323Sed BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); 136193323Sed NumFXCH++; 137193323Sed } 138193323Sed 139193323Sed void duplicateToTop(unsigned RegNo, unsigned AsReg, MachineInstr *I) { 140193323Sed DebugLoc dl = I->getDebugLoc(); 141193323Sed unsigned STReg = getSTReg(RegNo); 142193323Sed pushReg(AsReg); // New register on top of stack 143193323Sed 144193323Sed BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); 145193323Sed } 146193323Sed 147193323Sed // popStackAfter - Pop the current value off of the top of the FP stack 148193323Sed // after the specified instruction. 149193323Sed void popStackAfter(MachineBasicBlock::iterator &I); 150193323Sed 151193323Sed // freeStackSlotAfter - Free the specified register from the register stack, 152193323Sed // so that it is no longer in a register. If the register is currently at 153193323Sed // the top of the stack, we just pop the current instruction, otherwise we 154193323Sed // store the current top-of-stack into the specified slot, then pop the top 155193323Sed // of stack. 156193323Sed void freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned Reg); 157193323Sed 158193323Sed bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB); 159193323Sed 160193323Sed void handleZeroArgFP(MachineBasicBlock::iterator &I); 161193323Sed void handleOneArgFP(MachineBasicBlock::iterator &I); 162193323Sed void handleOneArgFPRW(MachineBasicBlock::iterator &I); 163193323Sed void handleTwoArgFP(MachineBasicBlock::iterator &I); 164193323Sed void handleCompareFP(MachineBasicBlock::iterator &I); 165193323Sed void handleCondMovFP(MachineBasicBlock::iterator &I); 166193323Sed void handleSpecialFP(MachineBasicBlock::iterator &I); 167193323Sed }; 168193323Sed char FPS::ID = 0; 169193323Sed} 170193323Sed 171193323SedFunctionPass *llvm::createX86FloatingPointStackifierPass() { return new FPS(); } 172193323Sed 173193323Sed/// getFPReg - Return the X86::FPx register number for the specified operand. 174193323Sed/// For example, this returns 3 for X86::FP3. 175193323Sedstatic unsigned getFPReg(const MachineOperand &MO) { 176193323Sed assert(MO.isReg() && "Expected an FP register!"); 177193323Sed unsigned Reg = MO.getReg(); 178193323Sed assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); 179193323Sed return Reg - X86::FP0; 180193323Sed} 181193323Sed 182193323Sed 183193323Sed/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP 184193323Sed/// register references into FP stack references. 185193323Sed/// 186193323Sedbool FPS::runOnMachineFunction(MachineFunction &MF) { 187193323Sed // We only need to run this pass if there are any FP registers used in this 188193323Sed // function. If it is all integer, there is nothing for us to do! 189193323Sed bool FPIsUsed = false; 190193323Sed 191193323Sed assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!"); 192193323Sed for (unsigned i = 0; i <= 6; ++i) 193193323Sed if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) { 194193323Sed FPIsUsed = true; 195193323Sed break; 196193323Sed } 197193323Sed 198193323Sed // Early exit. 199193323Sed if (!FPIsUsed) return false; 200193323Sed 201193323Sed TII = MF.getTarget().getInstrInfo(); 202193323Sed StackTop = 0; 203193323Sed 204193323Sed // Process the function in depth first order so that we process at least one 205193323Sed // of the predecessors for every reachable block in the function. 206193323Sed SmallPtrSet<MachineBasicBlock*, 8> Processed; 207193323Sed MachineBasicBlock *Entry = MF.begin(); 208193323Sed 209193323Sed bool Changed = false; 210193323Sed for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8> > 211193323Sed I = df_ext_begin(Entry, Processed), E = df_ext_end(Entry, Processed); 212193323Sed I != E; ++I) 213193323Sed Changed |= processBasicBlock(MF, **I); 214193323Sed 215198090Srdivacky // Process any unreachable blocks in arbitrary order now. 216198090Srdivacky if (MF.size() == Processed.size()) 217198090Srdivacky return Changed; 218198090Srdivacky 219198090Srdivacky for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB) 220198090Srdivacky if (Processed.insert(BB)) 221198090Srdivacky Changed |= processBasicBlock(MF, *BB); 222198090Srdivacky 223193323Sed return Changed; 224193323Sed} 225193323Sed 226193323Sed/// processBasicBlock - Loop over all of the instructions in the basic block, 227193323Sed/// transforming FP instructions into their stack form. 228193323Sed/// 229193323Sedbool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { 230193323Sed bool Changed = false; 231193323Sed MBB = &BB; 232193323Sed 233193323Sed for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) { 234193323Sed MachineInstr *MI = I; 235193323Sed unsigned Flags = MI->getDesc().TSFlags; 236193323Sed 237193323Sed unsigned FPInstClass = Flags & X86II::FPTypeMask; 238203954Srdivacky if (MI->isInlineAsm()) 239193323Sed FPInstClass = X86II::SpecialFP; 240193323Sed 241193323Sed if (FPInstClass == X86II::NotFP) 242193323Sed continue; // Efficiently ignore non-fp insts! 243193323Sed 244193323Sed MachineInstr *PrevMI = 0; 245193323Sed if (I != BB.begin()) 246193323Sed PrevMI = prior(I); 247193323Sed 248193323Sed ++NumFP; // Keep track of # of pseudo instrs 249202375Srdivacky DEBUG(dbgs() << "\nFPInst:\t" << *MI); 250193323Sed 251193323Sed // Get dead variables list now because the MI pointer may be deleted as part 252193323Sed // of processing! 253193323Sed SmallVector<unsigned, 8> DeadRegs; 254193323Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 255193323Sed const MachineOperand &MO = MI->getOperand(i); 256193323Sed if (MO.isReg() && MO.isDead()) 257193323Sed DeadRegs.push_back(MO.getReg()); 258193323Sed } 259193323Sed 260193323Sed switch (FPInstClass) { 261193323Sed case X86II::ZeroArgFP: handleZeroArgFP(I); break; 262193323Sed case X86II::OneArgFP: handleOneArgFP(I); break; // fstp ST(0) 263193323Sed case X86II::OneArgFPRW: handleOneArgFPRW(I); break; // ST(0) = fsqrt(ST(0)) 264193323Sed case X86II::TwoArgFP: handleTwoArgFP(I); break; 265193323Sed case X86II::CompareFP: handleCompareFP(I); break; 266193323Sed case X86II::CondMovFP: handleCondMovFP(I); break; 267193323Sed case X86II::SpecialFP: handleSpecialFP(I); break; 268198090Srdivacky default: llvm_unreachable("Unknown FP Type!"); 269193323Sed } 270193323Sed 271193323Sed // Check to see if any of the values defined by this instruction are dead 272193323Sed // after definition. If so, pop them. 273193323Sed for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) { 274193323Sed unsigned Reg = DeadRegs[i]; 275193323Sed if (Reg >= X86::FP0 && Reg <= X86::FP6) { 276202375Srdivacky DEBUG(dbgs() << "Register FP#" << Reg-X86::FP0 << " is dead!\n"); 277193323Sed freeStackSlotAfter(I, Reg-X86::FP0); 278193323Sed } 279193323Sed } 280193323Sed 281193323Sed // Print out all of the instructions expanded to if -debug 282193323Sed DEBUG( 283193323Sed MachineBasicBlock::iterator PrevI(PrevMI); 284193323Sed if (I == PrevI) { 285202375Srdivacky dbgs() << "Just deleted pseudo instruction\n"; 286193323Sed } else { 287193323Sed MachineBasicBlock::iterator Start = I; 288193323Sed // Rewind to first instruction newly inserted. 289193323Sed while (Start != BB.begin() && prior(Start) != PrevI) --Start; 290202375Srdivacky dbgs() << "Inserted instructions:\n\t"; 291202375Srdivacky Start->print(dbgs(), &MF.getTarget()); 292200581Srdivacky while (++Start != llvm::next(I)) {} 293193323Sed } 294193323Sed dumpStack(); 295193323Sed ); 296193323Sed 297193323Sed Changed = true; 298193323Sed } 299193323Sed 300193323Sed assert(isStackEmpty() && "Stack not empty at end of basic block?"); 301193323Sed return Changed; 302193323Sed} 303193323Sed 304193323Sed//===----------------------------------------------------------------------===// 305193323Sed// Efficient Lookup Table Support 306193323Sed//===----------------------------------------------------------------------===// 307193323Sed 308193323Sednamespace { 309193323Sed struct TableEntry { 310193323Sed unsigned from; 311193323Sed unsigned to; 312193323Sed bool operator<(const TableEntry &TE) const { return from < TE.from; } 313193323Sed friend bool operator<(const TableEntry &TE, unsigned V) { 314193323Sed return TE.from < V; 315193323Sed } 316193323Sed friend bool operator<(unsigned V, const TableEntry &TE) { 317193323Sed return V < TE.from; 318193323Sed } 319193323Sed }; 320193323Sed} 321193323Sed 322193323Sed#ifndef NDEBUG 323193323Sedstatic bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) { 324193323Sed for (unsigned i = 0; i != NumEntries-1; ++i) 325193323Sed if (!(Table[i] < Table[i+1])) return false; 326193323Sed return true; 327193323Sed} 328193323Sed#endif 329193323Sed 330193323Sedstatic int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) { 331193323Sed const TableEntry *I = std::lower_bound(Table, Table+N, Opcode); 332193323Sed if (I != Table+N && I->from == Opcode) 333193323Sed return I->to; 334193323Sed return -1; 335193323Sed} 336193323Sed 337193323Sed#ifdef NDEBUG 338193323Sed#define ASSERT_SORTED(TABLE) 339193323Sed#else 340193323Sed#define ASSERT_SORTED(TABLE) \ 341193323Sed { static bool TABLE##Checked = false; \ 342193323Sed if (!TABLE##Checked) { \ 343193323Sed assert(TableIsSorted(TABLE, array_lengthof(TABLE)) && \ 344193323Sed "All lookup tables must be sorted for efficient access!"); \ 345193323Sed TABLE##Checked = true; \ 346193323Sed } \ 347193323Sed } 348193323Sed#endif 349193323Sed 350193323Sed//===----------------------------------------------------------------------===// 351193323Sed// Register File -> Register Stack Mapping Methods 352193323Sed//===----------------------------------------------------------------------===// 353193323Sed 354193323Sed// OpcodeTable - Sorted map of register instructions to their stack version. 355193323Sed// The first element is an register file pseudo instruction, the second is the 356193323Sed// concrete X86 instruction which uses the register stack. 357193323Sed// 358193323Sedstatic const TableEntry OpcodeTable[] = { 359193323Sed { X86::ABS_Fp32 , X86::ABS_F }, 360193323Sed { X86::ABS_Fp64 , X86::ABS_F }, 361193323Sed { X86::ABS_Fp80 , X86::ABS_F }, 362193323Sed { X86::ADD_Fp32m , X86::ADD_F32m }, 363193323Sed { X86::ADD_Fp64m , X86::ADD_F64m }, 364193323Sed { X86::ADD_Fp64m32 , X86::ADD_F32m }, 365193323Sed { X86::ADD_Fp80m32 , X86::ADD_F32m }, 366193323Sed { X86::ADD_Fp80m64 , X86::ADD_F64m }, 367193323Sed { X86::ADD_FpI16m32 , X86::ADD_FI16m }, 368193323Sed { X86::ADD_FpI16m64 , X86::ADD_FI16m }, 369193323Sed { X86::ADD_FpI16m80 , X86::ADD_FI16m }, 370193323Sed { X86::ADD_FpI32m32 , X86::ADD_FI32m }, 371193323Sed { X86::ADD_FpI32m64 , X86::ADD_FI32m }, 372193323Sed { X86::ADD_FpI32m80 , X86::ADD_FI32m }, 373193323Sed { X86::CHS_Fp32 , X86::CHS_F }, 374193323Sed { X86::CHS_Fp64 , X86::CHS_F }, 375193323Sed { X86::CHS_Fp80 , X86::CHS_F }, 376193323Sed { X86::CMOVBE_Fp32 , X86::CMOVBE_F }, 377193323Sed { X86::CMOVBE_Fp64 , X86::CMOVBE_F }, 378193323Sed { X86::CMOVBE_Fp80 , X86::CMOVBE_F }, 379193323Sed { X86::CMOVB_Fp32 , X86::CMOVB_F }, 380193323Sed { X86::CMOVB_Fp64 , X86::CMOVB_F }, 381193323Sed { X86::CMOVB_Fp80 , X86::CMOVB_F }, 382193323Sed { X86::CMOVE_Fp32 , X86::CMOVE_F }, 383193323Sed { X86::CMOVE_Fp64 , X86::CMOVE_F }, 384193323Sed { X86::CMOVE_Fp80 , X86::CMOVE_F }, 385193323Sed { X86::CMOVNBE_Fp32 , X86::CMOVNBE_F }, 386193323Sed { X86::CMOVNBE_Fp64 , X86::CMOVNBE_F }, 387193323Sed { X86::CMOVNBE_Fp80 , X86::CMOVNBE_F }, 388193323Sed { X86::CMOVNB_Fp32 , X86::CMOVNB_F }, 389193323Sed { X86::CMOVNB_Fp64 , X86::CMOVNB_F }, 390193323Sed { X86::CMOVNB_Fp80 , X86::CMOVNB_F }, 391193323Sed { X86::CMOVNE_Fp32 , X86::CMOVNE_F }, 392193323Sed { X86::CMOVNE_Fp64 , X86::CMOVNE_F }, 393193323Sed { X86::CMOVNE_Fp80 , X86::CMOVNE_F }, 394193323Sed { X86::CMOVNP_Fp32 , X86::CMOVNP_F }, 395193323Sed { X86::CMOVNP_Fp64 , X86::CMOVNP_F }, 396193323Sed { X86::CMOVNP_Fp80 , X86::CMOVNP_F }, 397193323Sed { X86::CMOVP_Fp32 , X86::CMOVP_F }, 398193323Sed { X86::CMOVP_Fp64 , X86::CMOVP_F }, 399193323Sed { X86::CMOVP_Fp80 , X86::CMOVP_F }, 400193323Sed { X86::COS_Fp32 , X86::COS_F }, 401193323Sed { X86::COS_Fp64 , X86::COS_F }, 402193323Sed { X86::COS_Fp80 , X86::COS_F }, 403193323Sed { X86::DIVR_Fp32m , X86::DIVR_F32m }, 404193323Sed { X86::DIVR_Fp64m , X86::DIVR_F64m }, 405193323Sed { X86::DIVR_Fp64m32 , X86::DIVR_F32m }, 406193323Sed { X86::DIVR_Fp80m32 , X86::DIVR_F32m }, 407193323Sed { X86::DIVR_Fp80m64 , X86::DIVR_F64m }, 408193323Sed { X86::DIVR_FpI16m32, X86::DIVR_FI16m}, 409193323Sed { X86::DIVR_FpI16m64, X86::DIVR_FI16m}, 410193323Sed { X86::DIVR_FpI16m80, X86::DIVR_FI16m}, 411193323Sed { X86::DIVR_FpI32m32, X86::DIVR_FI32m}, 412193323Sed { X86::DIVR_FpI32m64, X86::DIVR_FI32m}, 413193323Sed { X86::DIVR_FpI32m80, X86::DIVR_FI32m}, 414193323Sed { X86::DIV_Fp32m , X86::DIV_F32m }, 415193323Sed { X86::DIV_Fp64m , X86::DIV_F64m }, 416193323Sed { X86::DIV_Fp64m32 , X86::DIV_F32m }, 417193323Sed { X86::DIV_Fp80m32 , X86::DIV_F32m }, 418193323Sed { X86::DIV_Fp80m64 , X86::DIV_F64m }, 419193323Sed { X86::DIV_FpI16m32 , X86::DIV_FI16m }, 420193323Sed { X86::DIV_FpI16m64 , X86::DIV_FI16m }, 421193323Sed { X86::DIV_FpI16m80 , X86::DIV_FI16m }, 422193323Sed { X86::DIV_FpI32m32 , X86::DIV_FI32m }, 423193323Sed { X86::DIV_FpI32m64 , X86::DIV_FI32m }, 424193323Sed { X86::DIV_FpI32m80 , X86::DIV_FI32m }, 425193323Sed { X86::ILD_Fp16m32 , X86::ILD_F16m }, 426193323Sed { X86::ILD_Fp16m64 , X86::ILD_F16m }, 427193323Sed { X86::ILD_Fp16m80 , X86::ILD_F16m }, 428193323Sed { X86::ILD_Fp32m32 , X86::ILD_F32m }, 429193323Sed { X86::ILD_Fp32m64 , X86::ILD_F32m }, 430193323Sed { X86::ILD_Fp32m80 , X86::ILD_F32m }, 431193323Sed { X86::ILD_Fp64m32 , X86::ILD_F64m }, 432193323Sed { X86::ILD_Fp64m64 , X86::ILD_F64m }, 433193323Sed { X86::ILD_Fp64m80 , X86::ILD_F64m }, 434193323Sed { X86::ISTT_Fp16m32 , X86::ISTT_FP16m}, 435193323Sed { X86::ISTT_Fp16m64 , X86::ISTT_FP16m}, 436193323Sed { X86::ISTT_Fp16m80 , X86::ISTT_FP16m}, 437193323Sed { X86::ISTT_Fp32m32 , X86::ISTT_FP32m}, 438193323Sed { X86::ISTT_Fp32m64 , X86::ISTT_FP32m}, 439193323Sed { X86::ISTT_Fp32m80 , X86::ISTT_FP32m}, 440193323Sed { X86::ISTT_Fp64m32 , X86::ISTT_FP64m}, 441193323Sed { X86::ISTT_Fp64m64 , X86::ISTT_FP64m}, 442193323Sed { X86::ISTT_Fp64m80 , X86::ISTT_FP64m}, 443193323Sed { X86::IST_Fp16m32 , X86::IST_F16m }, 444193323Sed { X86::IST_Fp16m64 , X86::IST_F16m }, 445193323Sed { X86::IST_Fp16m80 , X86::IST_F16m }, 446193323Sed { X86::IST_Fp32m32 , X86::IST_F32m }, 447193323Sed { X86::IST_Fp32m64 , X86::IST_F32m }, 448193323Sed { X86::IST_Fp32m80 , X86::IST_F32m }, 449193323Sed { X86::IST_Fp64m32 , X86::IST_FP64m }, 450193323Sed { X86::IST_Fp64m64 , X86::IST_FP64m }, 451193323Sed { X86::IST_Fp64m80 , X86::IST_FP64m }, 452193323Sed { X86::LD_Fp032 , X86::LD_F0 }, 453193323Sed { X86::LD_Fp064 , X86::LD_F0 }, 454193323Sed { X86::LD_Fp080 , X86::LD_F0 }, 455193323Sed { X86::LD_Fp132 , X86::LD_F1 }, 456193323Sed { X86::LD_Fp164 , X86::LD_F1 }, 457193323Sed { X86::LD_Fp180 , X86::LD_F1 }, 458193323Sed { X86::LD_Fp32m , X86::LD_F32m }, 459193323Sed { X86::LD_Fp32m64 , X86::LD_F32m }, 460193323Sed { X86::LD_Fp32m80 , X86::LD_F32m }, 461193323Sed { X86::LD_Fp64m , X86::LD_F64m }, 462193323Sed { X86::LD_Fp64m80 , X86::LD_F64m }, 463193323Sed { X86::LD_Fp80m , X86::LD_F80m }, 464193323Sed { X86::MUL_Fp32m , X86::MUL_F32m }, 465193323Sed { X86::MUL_Fp64m , X86::MUL_F64m }, 466193323Sed { X86::MUL_Fp64m32 , X86::MUL_F32m }, 467193323Sed { X86::MUL_Fp80m32 , X86::MUL_F32m }, 468193323Sed { X86::MUL_Fp80m64 , X86::MUL_F64m }, 469193323Sed { X86::MUL_FpI16m32 , X86::MUL_FI16m }, 470193323Sed { X86::MUL_FpI16m64 , X86::MUL_FI16m }, 471193323Sed { X86::MUL_FpI16m80 , X86::MUL_FI16m }, 472193323Sed { X86::MUL_FpI32m32 , X86::MUL_FI32m }, 473193323Sed { X86::MUL_FpI32m64 , X86::MUL_FI32m }, 474193323Sed { X86::MUL_FpI32m80 , X86::MUL_FI32m }, 475193323Sed { X86::SIN_Fp32 , X86::SIN_F }, 476193323Sed { X86::SIN_Fp64 , X86::SIN_F }, 477193323Sed { X86::SIN_Fp80 , X86::SIN_F }, 478193323Sed { X86::SQRT_Fp32 , X86::SQRT_F }, 479193323Sed { X86::SQRT_Fp64 , X86::SQRT_F }, 480193323Sed { X86::SQRT_Fp80 , X86::SQRT_F }, 481193323Sed { X86::ST_Fp32m , X86::ST_F32m }, 482193323Sed { X86::ST_Fp64m , X86::ST_F64m }, 483193323Sed { X86::ST_Fp64m32 , X86::ST_F32m }, 484193323Sed { X86::ST_Fp80m32 , X86::ST_F32m }, 485193323Sed { X86::ST_Fp80m64 , X86::ST_F64m }, 486193323Sed { X86::ST_FpP80m , X86::ST_FP80m }, 487193323Sed { X86::SUBR_Fp32m , X86::SUBR_F32m }, 488193323Sed { X86::SUBR_Fp64m , X86::SUBR_F64m }, 489193323Sed { X86::SUBR_Fp64m32 , X86::SUBR_F32m }, 490193323Sed { X86::SUBR_Fp80m32 , X86::SUBR_F32m }, 491193323Sed { X86::SUBR_Fp80m64 , X86::SUBR_F64m }, 492193323Sed { X86::SUBR_FpI16m32, X86::SUBR_FI16m}, 493193323Sed { X86::SUBR_FpI16m64, X86::SUBR_FI16m}, 494193323Sed { X86::SUBR_FpI16m80, X86::SUBR_FI16m}, 495193323Sed { X86::SUBR_FpI32m32, X86::SUBR_FI32m}, 496193323Sed { X86::SUBR_FpI32m64, X86::SUBR_FI32m}, 497193323Sed { X86::SUBR_FpI32m80, X86::SUBR_FI32m}, 498193323Sed { X86::SUB_Fp32m , X86::SUB_F32m }, 499193323Sed { X86::SUB_Fp64m , X86::SUB_F64m }, 500193323Sed { X86::SUB_Fp64m32 , X86::SUB_F32m }, 501193323Sed { X86::SUB_Fp80m32 , X86::SUB_F32m }, 502193323Sed { X86::SUB_Fp80m64 , X86::SUB_F64m }, 503193323Sed { X86::SUB_FpI16m32 , X86::SUB_FI16m }, 504193323Sed { X86::SUB_FpI16m64 , X86::SUB_FI16m }, 505193323Sed { X86::SUB_FpI16m80 , X86::SUB_FI16m }, 506193323Sed { X86::SUB_FpI32m32 , X86::SUB_FI32m }, 507193323Sed { X86::SUB_FpI32m64 , X86::SUB_FI32m }, 508193323Sed { X86::SUB_FpI32m80 , X86::SUB_FI32m }, 509193323Sed { X86::TST_Fp32 , X86::TST_F }, 510193323Sed { X86::TST_Fp64 , X86::TST_F }, 511193323Sed { X86::TST_Fp80 , X86::TST_F }, 512193323Sed { X86::UCOM_FpIr32 , X86::UCOM_FIr }, 513193323Sed { X86::UCOM_FpIr64 , X86::UCOM_FIr }, 514193323Sed { X86::UCOM_FpIr80 , X86::UCOM_FIr }, 515193323Sed { X86::UCOM_Fpr32 , X86::UCOM_Fr }, 516193323Sed { X86::UCOM_Fpr64 , X86::UCOM_Fr }, 517193323Sed { X86::UCOM_Fpr80 , X86::UCOM_Fr }, 518193323Sed}; 519193323Sed 520193323Sedstatic unsigned getConcreteOpcode(unsigned Opcode) { 521193323Sed ASSERT_SORTED(OpcodeTable); 522193323Sed int Opc = Lookup(OpcodeTable, array_lengthof(OpcodeTable), Opcode); 523193323Sed assert(Opc != -1 && "FP Stack instruction not in OpcodeTable!"); 524193323Sed return Opc; 525193323Sed} 526193323Sed 527193323Sed//===----------------------------------------------------------------------===// 528193323Sed// Helper Methods 529193323Sed//===----------------------------------------------------------------------===// 530193323Sed 531193323Sed// PopTable - Sorted map of instructions to their popping version. The first 532193323Sed// element is an instruction, the second is the version which pops. 533193323Sed// 534193323Sedstatic const TableEntry PopTable[] = { 535193323Sed { X86::ADD_FrST0 , X86::ADD_FPrST0 }, 536193323Sed 537193323Sed { X86::DIVR_FrST0, X86::DIVR_FPrST0 }, 538193323Sed { X86::DIV_FrST0 , X86::DIV_FPrST0 }, 539193323Sed 540193323Sed { X86::IST_F16m , X86::IST_FP16m }, 541193323Sed { X86::IST_F32m , X86::IST_FP32m }, 542193323Sed 543193323Sed { X86::MUL_FrST0 , X86::MUL_FPrST0 }, 544193323Sed 545193323Sed { X86::ST_F32m , X86::ST_FP32m }, 546193323Sed { X86::ST_F64m , X86::ST_FP64m }, 547193323Sed { X86::ST_Frr , X86::ST_FPrr }, 548193323Sed 549193323Sed { X86::SUBR_FrST0, X86::SUBR_FPrST0 }, 550193323Sed { X86::SUB_FrST0 , X86::SUB_FPrST0 }, 551193323Sed 552193323Sed { X86::UCOM_FIr , X86::UCOM_FIPr }, 553193323Sed 554193323Sed { X86::UCOM_FPr , X86::UCOM_FPPr }, 555193323Sed { X86::UCOM_Fr , X86::UCOM_FPr }, 556193323Sed}; 557193323Sed 558193323Sed/// popStackAfter - Pop the current value off of the top of the FP stack after 559193323Sed/// the specified instruction. This attempts to be sneaky and combine the pop 560193323Sed/// into the instruction itself if possible. The iterator is left pointing to 561193323Sed/// the last instruction, be it a new pop instruction inserted, or the old 562193323Sed/// instruction if it was modified in place. 563193323Sed/// 564193323Sedvoid FPS::popStackAfter(MachineBasicBlock::iterator &I) { 565193323Sed MachineInstr* MI = I; 566193323Sed DebugLoc dl = MI->getDebugLoc(); 567193323Sed ASSERT_SORTED(PopTable); 568193323Sed assert(StackTop > 0 && "Cannot pop empty stack!"); 569193323Sed RegMap[Stack[--StackTop]] = ~0; // Update state 570193323Sed 571193323Sed // Check to see if there is a popping version of this instruction... 572193323Sed int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode()); 573193323Sed if (Opcode != -1) { 574193323Sed I->setDesc(TII->get(Opcode)); 575193323Sed if (Opcode == X86::UCOM_FPPr) 576193323Sed I->RemoveOperand(0); 577193323Sed } else { // Insert an explicit pop 578193323Sed I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); 579193323Sed } 580193323Sed} 581193323Sed 582193323Sed/// freeStackSlotAfter - Free the specified register from the register stack, so 583193323Sed/// that it is no longer in a register. If the register is currently at the top 584193323Sed/// of the stack, we just pop the current instruction, otherwise we store the 585193323Sed/// current top-of-stack into the specified slot, then pop the top of stack. 586193323Sedvoid FPS::freeStackSlotAfter(MachineBasicBlock::iterator &I, unsigned FPRegNo) { 587193323Sed if (getStackEntry(0) == FPRegNo) { // already at the top of stack? easy. 588193323Sed popStackAfter(I); 589193323Sed return; 590193323Sed } 591193323Sed 592193323Sed // Otherwise, store the top of stack into the dead slot, killing the operand 593193323Sed // without having to add in an explicit xchg then pop. 594193323Sed // 595193323Sed unsigned STReg = getSTReg(FPRegNo); 596193323Sed unsigned OldSlot = getSlot(FPRegNo); 597193323Sed unsigned TopReg = Stack[StackTop-1]; 598193323Sed Stack[OldSlot] = TopReg; 599193323Sed RegMap[TopReg] = OldSlot; 600193323Sed RegMap[FPRegNo] = ~0; 601193323Sed Stack[--StackTop] = ~0; 602193323Sed MachineInstr *MI = I; 603193323Sed DebugLoc dl = MI->getDebugLoc(); 604193323Sed I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(STReg); 605193323Sed} 606193323Sed 607193323Sed 608193323Sed//===----------------------------------------------------------------------===// 609193323Sed// Instruction transformation implementation 610193323Sed//===----------------------------------------------------------------------===// 611193323Sed 612193323Sed/// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem> 613193323Sed/// 614193323Sedvoid FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) { 615193323Sed MachineInstr *MI = I; 616193323Sed unsigned DestReg = getFPReg(MI->getOperand(0)); 617193323Sed 618193323Sed // Change from the pseudo instruction to the concrete instruction. 619193323Sed MI->RemoveOperand(0); // Remove the explicit ST(0) operand 620193323Sed MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 621193323Sed 622193323Sed // Result gets pushed on the stack. 623193323Sed pushReg(DestReg); 624193323Sed} 625193323Sed 626193323Sed/// handleOneArgFP - fst <mem>, ST(0) 627193323Sed/// 628193323Sedvoid FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { 629193323Sed MachineInstr *MI = I; 630193323Sed unsigned NumOps = MI->getDesc().getNumOperands(); 631193323Sed assert((NumOps == X86AddrNumOperands + 1 || NumOps == 1) && 632193323Sed "Can only handle fst* & ftst instructions!"); 633193323Sed 634193323Sed // Is this the last use of the source register? 635193323Sed unsigned Reg = getFPReg(MI->getOperand(NumOps-1)); 636193323Sed bool KillsSrc = MI->killsRegister(X86::FP0+Reg); 637193323Sed 638193323Sed // FISTP64m is strange because there isn't a non-popping versions. 639193323Sed // If we have one _and_ we don't want to pop the operand, duplicate the value 640193323Sed // on the stack instead of moving it. This ensure that popping the value is 641193323Sed // always ok. 642193323Sed // Ditto FISTTP16m, FISTTP32m, FISTTP64m, ST_FpP80m. 643193323Sed // 644193323Sed if (!KillsSrc && 645193323Sed (MI->getOpcode() == X86::IST_Fp64m32 || 646193323Sed MI->getOpcode() == X86::ISTT_Fp16m32 || 647193323Sed MI->getOpcode() == X86::ISTT_Fp32m32 || 648193323Sed MI->getOpcode() == X86::ISTT_Fp64m32 || 649193323Sed MI->getOpcode() == X86::IST_Fp64m64 || 650193323Sed MI->getOpcode() == X86::ISTT_Fp16m64 || 651193323Sed MI->getOpcode() == X86::ISTT_Fp32m64 || 652193323Sed MI->getOpcode() == X86::ISTT_Fp64m64 || 653193323Sed MI->getOpcode() == X86::IST_Fp64m80 || 654193323Sed MI->getOpcode() == X86::ISTT_Fp16m80 || 655193323Sed MI->getOpcode() == X86::ISTT_Fp32m80 || 656193323Sed MI->getOpcode() == X86::ISTT_Fp64m80 || 657193323Sed MI->getOpcode() == X86::ST_FpP80m)) { 658193323Sed duplicateToTop(Reg, 7 /*temp register*/, I); 659193323Sed } else { 660193323Sed moveToTop(Reg, I); // Move to the top of the stack... 661193323Sed } 662193323Sed 663193323Sed // Convert from the pseudo instruction to the concrete instruction. 664193323Sed MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand 665193323Sed MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 666193323Sed 667193323Sed if (MI->getOpcode() == X86::IST_FP64m || 668193323Sed MI->getOpcode() == X86::ISTT_FP16m || 669193323Sed MI->getOpcode() == X86::ISTT_FP32m || 670193323Sed MI->getOpcode() == X86::ISTT_FP64m || 671193323Sed MI->getOpcode() == X86::ST_FP80m) { 672193323Sed assert(StackTop > 0 && "Stack empty??"); 673193323Sed --StackTop; 674193323Sed } else if (KillsSrc) { // Last use of operand? 675193323Sed popStackAfter(I); 676193323Sed } 677193323Sed} 678193323Sed 679193323Sed 680193323Sed/// handleOneArgFPRW: Handle instructions that read from the top of stack and 681193323Sed/// replace the value with a newly computed value. These instructions may have 682193323Sed/// non-fp operands after their FP operands. 683193323Sed/// 684193323Sed/// Examples: 685193323Sed/// R1 = fchs R2 686193323Sed/// R1 = fadd R2, [mem] 687193323Sed/// 688193323Sedvoid FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { 689193323Sed MachineInstr *MI = I; 690193323Sed#ifndef NDEBUG 691193323Sed unsigned NumOps = MI->getDesc().getNumOperands(); 692193323Sed assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!"); 693193323Sed#endif 694193323Sed 695193323Sed // Is this the last use of the source register? 696193323Sed unsigned Reg = getFPReg(MI->getOperand(1)); 697193323Sed bool KillsSrc = MI->killsRegister(X86::FP0+Reg); 698193323Sed 699193323Sed if (KillsSrc) { 700193323Sed // If this is the last use of the source register, just make sure it's on 701193323Sed // the top of the stack. 702193323Sed moveToTop(Reg, I); 703193323Sed assert(StackTop > 0 && "Stack cannot be empty!"); 704193323Sed --StackTop; 705193323Sed pushReg(getFPReg(MI->getOperand(0))); 706193323Sed } else { 707193323Sed // If this is not the last use of the source register, _copy_ it to the top 708193323Sed // of the stack. 709193323Sed duplicateToTop(Reg, getFPReg(MI->getOperand(0)), I); 710193323Sed } 711193323Sed 712193323Sed // Change from the pseudo instruction to the concrete instruction. 713193323Sed MI->RemoveOperand(1); // Drop the source operand. 714193323Sed MI->RemoveOperand(0); // Drop the destination operand. 715193323Sed MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 716193323Sed} 717193323Sed 718193323Sed 719193323Sed//===----------------------------------------------------------------------===// 720193323Sed// Define tables of various ways to map pseudo instructions 721193323Sed// 722193323Sed 723193323Sed// ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i) 724193323Sedstatic const TableEntry ForwardST0Table[] = { 725193323Sed { X86::ADD_Fp32 , X86::ADD_FST0r }, 726193323Sed { X86::ADD_Fp64 , X86::ADD_FST0r }, 727193323Sed { X86::ADD_Fp80 , X86::ADD_FST0r }, 728193323Sed { X86::DIV_Fp32 , X86::DIV_FST0r }, 729193323Sed { X86::DIV_Fp64 , X86::DIV_FST0r }, 730193323Sed { X86::DIV_Fp80 , X86::DIV_FST0r }, 731193323Sed { X86::MUL_Fp32 , X86::MUL_FST0r }, 732193323Sed { X86::MUL_Fp64 , X86::MUL_FST0r }, 733193323Sed { X86::MUL_Fp80 , X86::MUL_FST0r }, 734193323Sed { X86::SUB_Fp32 , X86::SUB_FST0r }, 735193323Sed { X86::SUB_Fp64 , X86::SUB_FST0r }, 736193323Sed { X86::SUB_Fp80 , X86::SUB_FST0r }, 737193323Sed}; 738193323Sed 739193323Sed// ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0) 740193323Sedstatic const TableEntry ReverseST0Table[] = { 741193323Sed { X86::ADD_Fp32 , X86::ADD_FST0r }, // commutative 742193323Sed { X86::ADD_Fp64 , X86::ADD_FST0r }, // commutative 743193323Sed { X86::ADD_Fp80 , X86::ADD_FST0r }, // commutative 744193323Sed { X86::DIV_Fp32 , X86::DIVR_FST0r }, 745193323Sed { X86::DIV_Fp64 , X86::DIVR_FST0r }, 746193323Sed { X86::DIV_Fp80 , X86::DIVR_FST0r }, 747193323Sed { X86::MUL_Fp32 , X86::MUL_FST0r }, // commutative 748193323Sed { X86::MUL_Fp64 , X86::MUL_FST0r }, // commutative 749193323Sed { X86::MUL_Fp80 , X86::MUL_FST0r }, // commutative 750193323Sed { X86::SUB_Fp32 , X86::SUBR_FST0r }, 751193323Sed { X86::SUB_Fp64 , X86::SUBR_FST0r }, 752193323Sed { X86::SUB_Fp80 , X86::SUBR_FST0r }, 753193323Sed}; 754193323Sed 755193323Sed// ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i) 756193323Sedstatic const TableEntry ForwardSTiTable[] = { 757193323Sed { X86::ADD_Fp32 , X86::ADD_FrST0 }, // commutative 758193323Sed { X86::ADD_Fp64 , X86::ADD_FrST0 }, // commutative 759193323Sed { X86::ADD_Fp80 , X86::ADD_FrST0 }, // commutative 760193323Sed { X86::DIV_Fp32 , X86::DIVR_FrST0 }, 761193323Sed { X86::DIV_Fp64 , X86::DIVR_FrST0 }, 762193323Sed { X86::DIV_Fp80 , X86::DIVR_FrST0 }, 763193323Sed { X86::MUL_Fp32 , X86::MUL_FrST0 }, // commutative 764193323Sed { X86::MUL_Fp64 , X86::MUL_FrST0 }, // commutative 765193323Sed { X86::MUL_Fp80 , X86::MUL_FrST0 }, // commutative 766193323Sed { X86::SUB_Fp32 , X86::SUBR_FrST0 }, 767193323Sed { X86::SUB_Fp64 , X86::SUBR_FrST0 }, 768193323Sed { X86::SUB_Fp80 , X86::SUBR_FrST0 }, 769193323Sed}; 770193323Sed 771193323Sed// ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0) 772193323Sedstatic const TableEntry ReverseSTiTable[] = { 773193323Sed { X86::ADD_Fp32 , X86::ADD_FrST0 }, 774193323Sed { X86::ADD_Fp64 , X86::ADD_FrST0 }, 775193323Sed { X86::ADD_Fp80 , X86::ADD_FrST0 }, 776193323Sed { X86::DIV_Fp32 , X86::DIV_FrST0 }, 777193323Sed { X86::DIV_Fp64 , X86::DIV_FrST0 }, 778193323Sed { X86::DIV_Fp80 , X86::DIV_FrST0 }, 779193323Sed { X86::MUL_Fp32 , X86::MUL_FrST0 }, 780193323Sed { X86::MUL_Fp64 , X86::MUL_FrST0 }, 781193323Sed { X86::MUL_Fp80 , X86::MUL_FrST0 }, 782193323Sed { X86::SUB_Fp32 , X86::SUB_FrST0 }, 783193323Sed { X86::SUB_Fp64 , X86::SUB_FrST0 }, 784193323Sed { X86::SUB_Fp80 , X86::SUB_FrST0 }, 785193323Sed}; 786193323Sed 787193323Sed 788193323Sed/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual 789193323Sed/// instructions which need to be simplified and possibly transformed. 790193323Sed/// 791193323Sed/// Result: ST(0) = fsub ST(0), ST(i) 792193323Sed/// ST(i) = fsub ST(0), ST(i) 793193323Sed/// ST(0) = fsubr ST(0), ST(i) 794193323Sed/// ST(i) = fsubr ST(0), ST(i) 795193323Sed/// 796193323Sedvoid FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { 797193323Sed ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 798193323Sed ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 799193323Sed MachineInstr *MI = I; 800193323Sed 801193323Sed unsigned NumOperands = MI->getDesc().getNumOperands(); 802193323Sed assert(NumOperands == 3 && "Illegal TwoArgFP instruction!"); 803193323Sed unsigned Dest = getFPReg(MI->getOperand(0)); 804193323Sed unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 805193323Sed unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 806193323Sed bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); 807193323Sed bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 808193323Sed DebugLoc dl = MI->getDebugLoc(); 809193323Sed 810193323Sed unsigned TOS = getStackEntry(0); 811193323Sed 812193323Sed // One of our operands must be on the top of the stack. If neither is yet, we 813193323Sed // need to move one. 814193323Sed if (Op0 != TOS && Op1 != TOS) { // No operand at TOS? 815193323Sed // We can choose to move either operand to the top of the stack. If one of 816193323Sed // the operands is killed by this instruction, we want that one so that we 817193323Sed // can update right on top of the old version. 818193323Sed if (KillsOp0) { 819193323Sed moveToTop(Op0, I); // Move dead operand to TOS. 820193323Sed TOS = Op0; 821193323Sed } else if (KillsOp1) { 822193323Sed moveToTop(Op1, I); 823193323Sed TOS = Op1; 824193323Sed } else { 825193323Sed // All of the operands are live after this instruction executes, so we 826193323Sed // cannot update on top of any operand. Because of this, we must 827193323Sed // duplicate one of the stack elements to the top. It doesn't matter 828193323Sed // which one we pick. 829193323Sed // 830193323Sed duplicateToTop(Op0, Dest, I); 831193323Sed Op0 = TOS = Dest; 832193323Sed KillsOp0 = true; 833193323Sed } 834193323Sed } else if (!KillsOp0 && !KillsOp1) { 835193323Sed // If we DO have one of our operands at the top of the stack, but we don't 836193323Sed // have a dead operand, we must duplicate one of the operands to a new slot 837193323Sed // on the stack. 838193323Sed duplicateToTop(Op0, Dest, I); 839193323Sed Op0 = TOS = Dest; 840193323Sed KillsOp0 = true; 841193323Sed } 842193323Sed 843193323Sed // Now we know that one of our operands is on the top of the stack, and at 844193323Sed // least one of our operands is killed by this instruction. 845193323Sed assert((TOS == Op0 || TOS == Op1) && (KillsOp0 || KillsOp1) && 846193323Sed "Stack conditions not set up right!"); 847193323Sed 848193323Sed // We decide which form to use based on what is on the top of the stack, and 849193323Sed // which operand is killed by this instruction. 850193323Sed const TableEntry *InstTable; 851193323Sed bool isForward = TOS == Op0; 852193323Sed bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0); 853193323Sed if (updateST0) { 854193323Sed if (isForward) 855193323Sed InstTable = ForwardST0Table; 856193323Sed else 857193323Sed InstTable = ReverseST0Table; 858193323Sed } else { 859193323Sed if (isForward) 860193323Sed InstTable = ForwardSTiTable; 861193323Sed else 862193323Sed InstTable = ReverseSTiTable; 863193323Sed } 864193323Sed 865193323Sed int Opcode = Lookup(InstTable, array_lengthof(ForwardST0Table), 866193323Sed MI->getOpcode()); 867193323Sed assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!"); 868193323Sed 869193323Sed // NotTOS - The register which is not on the top of stack... 870193323Sed unsigned NotTOS = (TOS == Op0) ? Op1 : Op0; 871193323Sed 872193323Sed // Replace the old instruction with a new instruction 873193323Sed MBB->remove(I++); 874193323Sed I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS)); 875193323Sed 876193323Sed // If both operands are killed, pop one off of the stack in addition to 877193323Sed // overwriting the other one. 878193323Sed if (KillsOp0 && KillsOp1 && Op0 != Op1) { 879193323Sed assert(!updateST0 && "Should have updated other operand!"); 880193323Sed popStackAfter(I); // Pop the top of stack 881193323Sed } 882193323Sed 883193323Sed // Update stack information so that we know the destination register is now on 884193323Sed // the stack. 885193323Sed unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS); 886193323Sed assert(UpdatedSlot < StackTop && Dest < 7); 887193323Sed Stack[UpdatedSlot] = Dest; 888193323Sed RegMap[Dest] = UpdatedSlot; 889193323Sed MBB->getParent()->DeleteMachineInstr(MI); // Remove the old instruction 890193323Sed} 891193323Sed 892193323Sed/// handleCompareFP - Handle FUCOM and FUCOMI instructions, which have two FP 893193323Sed/// register arguments and no explicit destinations. 894193323Sed/// 895193323Sedvoid FPS::handleCompareFP(MachineBasicBlock::iterator &I) { 896193323Sed ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table); 897193323Sed ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable); 898193323Sed MachineInstr *MI = I; 899193323Sed 900193323Sed unsigned NumOperands = MI->getDesc().getNumOperands(); 901193323Sed assert(NumOperands == 2 && "Illegal FUCOM* instruction!"); 902193323Sed unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2)); 903193323Sed unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1)); 904193323Sed bool KillsOp0 = MI->killsRegister(X86::FP0+Op0); 905193323Sed bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 906193323Sed 907193323Sed // Make sure the first operand is on the top of stack, the other one can be 908193323Sed // anywhere. 909193323Sed moveToTop(Op0, I); 910193323Sed 911193323Sed // Change from the pseudo instruction to the concrete instruction. 912193323Sed MI->getOperand(0).setReg(getSTReg(Op1)); 913193323Sed MI->RemoveOperand(1); 914193323Sed MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 915193323Sed 916193323Sed // If any of the operands are killed by this instruction, free them. 917193323Sed if (KillsOp0) freeStackSlotAfter(I, Op0); 918193323Sed if (KillsOp1 && Op0 != Op1) freeStackSlotAfter(I, Op1); 919193323Sed} 920193323Sed 921193323Sed/// handleCondMovFP - Handle two address conditional move instructions. These 922193323Sed/// instructions move a st(i) register to st(0) iff a condition is true. These 923193323Sed/// instructions require that the first operand is at the top of the stack, but 924193323Sed/// otherwise don't modify the stack at all. 925193323Sedvoid FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { 926193323Sed MachineInstr *MI = I; 927193323Sed 928193323Sed unsigned Op0 = getFPReg(MI->getOperand(0)); 929193323Sed unsigned Op1 = getFPReg(MI->getOperand(2)); 930193323Sed bool KillsOp1 = MI->killsRegister(X86::FP0+Op1); 931193323Sed 932193323Sed // The first operand *must* be on the top of the stack. 933193323Sed moveToTop(Op0, I); 934193323Sed 935193323Sed // Change the second operand to the stack register that the operand is in. 936193323Sed // Change from the pseudo instruction to the concrete instruction. 937193323Sed MI->RemoveOperand(0); 938193323Sed MI->RemoveOperand(1); 939193323Sed MI->getOperand(0).setReg(getSTReg(Op1)); 940193323Sed MI->setDesc(TII->get(getConcreteOpcode(MI->getOpcode()))); 941193323Sed 942193323Sed // If we kill the second operand, make sure to pop it from the stack. 943193323Sed if (Op0 != Op1 && KillsOp1) { 944193323Sed // Get this value off of the register stack. 945193323Sed freeStackSlotAfter(I, Op1); 946193323Sed } 947193323Sed} 948193323Sed 949193323Sed 950193323Sed/// handleSpecialFP - Handle special instructions which behave unlike other 951193323Sed/// floating point instructions. This is primarily intended for use by pseudo 952193323Sed/// instructions. 953193323Sed/// 954193323Sedvoid FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { 955193323Sed MachineInstr *MI = I; 956193323Sed DebugLoc dl = MI->getDebugLoc(); 957193323Sed switch (MI->getOpcode()) { 958198090Srdivacky default: llvm_unreachable("Unknown SpecialFP instruction!"); 959193323Sed case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type! 960193323Sed case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type! 961193323Sed case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type! 962193323Sed assert(StackTop == 0 && "Stack should be empty after a call!"); 963193323Sed pushReg(getFPReg(MI->getOperand(0))); 964193323Sed break; 965193323Sed case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type! 966193323Sed case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type! 967193323Sed case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type! 968193323Sed // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm. 969193323Sed // The pattern we expect is: 970193323Sed // CALL 971193323Sed // FP1 = FpGET_ST0 972193323Sed // FP4 = FpGET_ST1 973193323Sed // 974193323Sed // At this point, we've pushed FP1 on the top of stack, so it should be 975193323Sed // present if it isn't dead. If it was dead, we already emitted a pop to 976193323Sed // remove it from the stack and StackTop = 0. 977193323Sed 978193323Sed // Push FP4 as top of stack next. 979193323Sed pushReg(getFPReg(MI->getOperand(0))); 980193323Sed 981193323Sed // If StackTop was 0 before we pushed our operand, then ST(0) must have been 982193323Sed // dead. In this case, the ST(1) value is the only thing that is live, so 983193323Sed // it should be on the TOS (after the pop that was emitted) and is. Just 984193323Sed // continue in this case. 985193323Sed if (StackTop == 1) 986193323Sed break; 987193323Sed 988193323Sed // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top 989193323Sed // elements so that our accounting is correct. 990193323Sed unsigned RegOnTop = getStackEntry(0); 991193323Sed unsigned RegNo = getStackEntry(1); 992193323Sed 993193323Sed // Swap the slots the regs are in. 994193323Sed std::swap(RegMap[RegNo], RegMap[RegOnTop]); 995193323Sed 996193323Sed // Swap stack slot contents. 997193323Sed assert(RegMap[RegOnTop] < StackTop); 998193323Sed std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); 999193323Sed break; 1000193323Sed } 1001193323Sed case X86::FpSET_ST0_32: 1002193323Sed case X86::FpSET_ST0_64: 1003195340Sed case X86::FpSET_ST0_80: { 1004195340Sed unsigned Op0 = getFPReg(MI->getOperand(0)); 1005195340Sed 1006194612Sed // FpSET_ST0_80 is generated by copyRegToReg for both function return 1007194612Sed // and inline assembly with the "st" constrain. In the latter case, 1008195340Sed // it is possible for ST(0) to be alive after this instruction. 1009195340Sed if (!MI->killsRegister(X86::FP0 + Op0)) { 1010195340Sed // Duplicate Op0 1011195340Sed duplicateToTop(0, 7 /*temp register*/, I); 1012195340Sed } else { 1013195340Sed moveToTop(Op0, I); 1014194612Sed } 1015193323Sed --StackTop; // "Forget" we have something on the top of stack! 1016193323Sed break; 1017195340Sed } 1018193323Sed case X86::FpSET_ST1_32: 1019193323Sed case X86::FpSET_ST1_64: 1020193323Sed case X86::FpSET_ST1_80: 1021193323Sed // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them. 1022193323Sed if (StackTop == 1) { 1023193323Sed BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1); 1024193323Sed NumFXCH++; 1025193323Sed StackTop = 0; 1026193323Sed break; 1027193323Sed } 1028193323Sed assert(StackTop == 2 && "Stack should have two element on it to return!"); 1029193323Sed --StackTop; // "Forget" we have something on the top of stack! 1030193323Sed break; 1031193323Sed case X86::MOV_Fp3232: 1032193323Sed case X86::MOV_Fp3264: 1033193323Sed case X86::MOV_Fp6432: 1034193323Sed case X86::MOV_Fp6464: 1035193323Sed case X86::MOV_Fp3280: 1036193323Sed case X86::MOV_Fp6480: 1037193323Sed case X86::MOV_Fp8032: 1038193323Sed case X86::MOV_Fp8064: 1039193323Sed case X86::MOV_Fp8080: { 1040193323Sed const MachineOperand &MO1 = MI->getOperand(1); 1041193323Sed unsigned SrcReg = getFPReg(MO1); 1042193323Sed 1043193323Sed const MachineOperand &MO0 = MI->getOperand(0); 1044193323Sed // These can be created due to inline asm. Two address pass can introduce 1045193323Sed // copies from RFP registers to virtual registers. 1046193323Sed if (MO0.getReg() == X86::ST0 && SrcReg == 0) { 1047193323Sed assert(MO1.isKill()); 1048193323Sed // Treat %ST0<def> = MOV_Fp8080 %FP0<kill> 1049193323Sed // like FpSET_ST0_80 %FP0<kill>, %ST0<imp-def> 1050193323Sed assert((StackTop == 1 || StackTop == 2) 1051193323Sed && "Stack should have one or two element on it to return!"); 1052193323Sed --StackTop; // "Forget" we have something on the top of stack! 1053193323Sed break; 1054193323Sed } else if (MO0.getReg() == X86::ST1 && SrcReg == 1) { 1055193323Sed assert(MO1.isKill()); 1056193323Sed // Treat %ST1<def> = MOV_Fp8080 %FP1<kill> 1057193323Sed // like FpSET_ST1_80 %FP0<kill>, %ST1<imp-def> 1058193323Sed // StackTop can be 1 if a FpSET_ST0_* was before this. Exchange them. 1059193323Sed if (StackTop == 1) { 1060193323Sed BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(X86::ST1); 1061193323Sed NumFXCH++; 1062193323Sed StackTop = 0; 1063193323Sed break; 1064193323Sed } 1065193323Sed assert(StackTop == 2 && "Stack should have two element on it to return!"); 1066193323Sed --StackTop; // "Forget" we have something on the top of stack! 1067193323Sed break; 1068193323Sed } 1069193323Sed 1070193323Sed unsigned DestReg = getFPReg(MO0); 1071193323Sed if (MI->killsRegister(X86::FP0+SrcReg)) { 1072193323Sed // If the input operand is killed, we can just change the owner of the 1073193323Sed // incoming stack slot into the result. 1074193323Sed unsigned Slot = getSlot(SrcReg); 1075193323Sed assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!"); 1076193323Sed Stack[Slot] = DestReg; 1077193323Sed RegMap[DestReg] = Slot; 1078193323Sed 1079193323Sed } else { 1080193323Sed // For FMOV we just duplicate the specified value to a new stack slot. 1081193323Sed // This could be made better, but would require substantial changes. 1082193323Sed duplicateToTop(SrcReg, DestReg, I); 1083193323Sed } 1084193323Sed } 1085193323Sed break; 1086203954Srdivacky case TargetOpcode::INLINEASM: { 1087193323Sed // The inline asm MachineInstr currently only *uses* FP registers for the 1088193323Sed // 'f' constraint. These should be turned into the current ST(x) register 1089193323Sed // in the machine instr. Also, any kills should be explicitly popped after 1090193323Sed // the inline asm. 1091193323Sed unsigned Kills[7]; 1092193323Sed unsigned NumKills = 0; 1093193323Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1094193323Sed MachineOperand &Op = MI->getOperand(i); 1095193323Sed if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1096193323Sed continue; 1097193323Sed assert(Op.isUse() && "Only handle inline asm uses right now"); 1098193323Sed 1099193323Sed unsigned FPReg = getFPReg(Op); 1100193323Sed Op.setReg(getSTReg(FPReg)); 1101193323Sed 1102193323Sed // If we kill this operand, make sure to pop it from the stack after the 1103193323Sed // asm. We just remember it for now, and pop them all off at the end in 1104193323Sed // a batch. 1105193323Sed if (Op.isKill()) 1106193323Sed Kills[NumKills++] = FPReg; 1107193323Sed } 1108193323Sed 1109193323Sed // If this asm kills any FP registers (is the last use of them) we must 1110193323Sed // explicitly emit pop instructions for them. Do this now after the asm has 1111193323Sed // executed so that the ST(x) numbers are not off (which would happen if we 1112193323Sed // did this inline with operand rewriting). 1113193323Sed // 1114193323Sed // Note: this might be a non-optimal pop sequence. We might be able to do 1115193323Sed // better by trying to pop in stack order or something. 1116193323Sed MachineBasicBlock::iterator InsertPt = MI; 1117193323Sed while (NumKills) 1118193323Sed freeStackSlotAfter(InsertPt, Kills[--NumKills]); 1119193323Sed 1120193323Sed // Don't delete the inline asm! 1121193323Sed return; 1122193323Sed } 1123193323Sed 1124193323Sed case X86::RET: 1125193323Sed case X86::RETI: 1126193323Sed // If RET has an FP register use operand, pass the first one in ST(0) and 1127193323Sed // the second one in ST(1). 1128193323Sed if (isStackEmpty()) return; // Quick check to see if any are possible. 1129193323Sed 1130193323Sed // Find the register operands. 1131193323Sed unsigned FirstFPRegOp = ~0U, SecondFPRegOp = ~0U; 1132193323Sed 1133193323Sed for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1134193323Sed MachineOperand &Op = MI->getOperand(i); 1135193323Sed if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 1136193323Sed continue; 1137193323Sed // FP Register uses must be kills unless there are two uses of the same 1138193323Sed // register, in which case only one will be a kill. 1139193323Sed assert(Op.isUse() && 1140193323Sed (Op.isKill() || // Marked kill. 1141193323Sed getFPReg(Op) == FirstFPRegOp || // Second instance. 1142193323Sed MI->killsRegister(Op.getReg())) && // Later use is marked kill. 1143193323Sed "Ret only defs operands, and values aren't live beyond it"); 1144193323Sed 1145193323Sed if (FirstFPRegOp == ~0U) 1146193323Sed FirstFPRegOp = getFPReg(Op); 1147193323Sed else { 1148193323Sed assert(SecondFPRegOp == ~0U && "More than two fp operands!"); 1149193323Sed SecondFPRegOp = getFPReg(Op); 1150193323Sed } 1151193323Sed 1152193323Sed // Remove the operand so that later passes don't see it. 1153193323Sed MI->RemoveOperand(i); 1154193323Sed --i, --e; 1155193323Sed } 1156193323Sed 1157193323Sed // There are only four possibilities here: 1158193323Sed // 1) we are returning a single FP value. In this case, it has to be in 1159193323Sed // ST(0) already, so just declare success by removing the value from the 1160193323Sed // FP Stack. 1161193323Sed if (SecondFPRegOp == ~0U) { 1162193323Sed // Assert that the top of stack contains the right FP register. 1163193323Sed assert(StackTop == 1 && FirstFPRegOp == getStackEntry(0) && 1164193323Sed "Top of stack not the right register for RET!"); 1165193323Sed 1166193323Sed // Ok, everything is good, mark the value as not being on the stack 1167193323Sed // anymore so that our assertion about the stack being empty at end of 1168193323Sed // block doesn't fire. 1169193323Sed StackTop = 0; 1170193323Sed return; 1171193323Sed } 1172193323Sed 1173193323Sed // Otherwise, we are returning two values: 1174193323Sed // 2) If returning the same value for both, we only have one thing in the FP 1175193323Sed // stack. Consider: RET FP1, FP1 1176193323Sed if (StackTop == 1) { 1177193323Sed assert(FirstFPRegOp == SecondFPRegOp && FirstFPRegOp == getStackEntry(0)&& 1178193323Sed "Stack misconfiguration for RET!"); 1179193323Sed 1180193323Sed // Duplicate the TOS so that we return it twice. Just pick some other FPx 1181193323Sed // register to hold it. 1182193323Sed unsigned NewReg = (FirstFPRegOp+1)%7; 1183193323Sed duplicateToTop(FirstFPRegOp, NewReg, MI); 1184193323Sed FirstFPRegOp = NewReg; 1185193323Sed } 1186193323Sed 1187193323Sed /// Okay we know we have two different FPx operands now: 1188193323Sed assert(StackTop == 2 && "Must have two values live!"); 1189193323Sed 1190193323Sed /// 3) If SecondFPRegOp is currently in ST(0) and FirstFPRegOp is currently 1191193323Sed /// in ST(1). In this case, emit an fxch. 1192193323Sed if (getStackEntry(0) == SecondFPRegOp) { 1193193323Sed assert(getStackEntry(1) == FirstFPRegOp && "Unknown regs live"); 1194193323Sed moveToTop(FirstFPRegOp, MI); 1195193323Sed } 1196193323Sed 1197193323Sed /// 4) Finally, FirstFPRegOp must be in ST(0) and SecondFPRegOp must be in 1198193323Sed /// ST(1). Just remove both from our understanding of the stack and return. 1199193323Sed assert(getStackEntry(0) == FirstFPRegOp && "Unknown regs live"); 1200193323Sed assert(getStackEntry(1) == SecondFPRegOp && "Unknown regs live"); 1201193323Sed StackTop = 0; 1202193323Sed return; 1203193323Sed } 1204193323Sed 1205193323Sed I = MBB->erase(I); // Remove the pseudo instruction 1206193323Sed --I; 1207193323Sed} 1208