X86FastISel.cpp revision 208599
1//===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the X86-specific support for the FastISel class. Much 11// of the target-specific code is generated by tablegen in the file 12// X86GenFastISel.inc, which is #included here. 13// 14//===----------------------------------------------------------------------===// 15 16#include "X86.h" 17#include "X86InstrBuilder.h" 18#include "X86RegisterInfo.h" 19#include "X86Subtarget.h" 20#include "X86TargetMachine.h" 21#include "llvm/CallingConv.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/GlobalVariable.h" 24#include "llvm/Instructions.h" 25#include "llvm/IntrinsicInst.h" 26#include "llvm/CodeGen/FastISel.h" 27#include "llvm/CodeGen/MachineConstantPool.h" 28#include "llvm/CodeGen/MachineFrameInfo.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/Support/CallSite.h" 31#include "llvm/Support/ErrorHandling.h" 32#include "llvm/Support/GetElementPtrTypeIterator.h" 33#include "llvm/Target/TargetOptions.h" 34using namespace llvm; 35 36namespace { 37 38class X86FastISel : public FastISel { 39 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 40 /// make the right decision when generating code for different targets. 41 const X86Subtarget *Subtarget; 42 43 /// StackPtr - Register used as the stack pointer. 44 /// 45 unsigned StackPtr; 46 47 /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 48 /// floating point ops. 49 /// When SSE is available, use it for f32 operations. 50 /// When SSE2 is available, use it for f64 operations. 51 bool X86ScalarSSEf64; 52 bool X86ScalarSSEf32; 53 54public: 55 explicit X86FastISel(MachineFunction &mf, 56 DenseMap<const Value *, unsigned> &vm, 57 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 58 DenseMap<const AllocaInst *, int> &am, 59 std::vector<std::pair<MachineInstr*, unsigned> > &pn 60#ifndef NDEBUG 61 , SmallSet<const Instruction *, 8> &cil 62#endif 63 ) 64 : FastISel(mf, vm, bm, am, pn 65#ifndef NDEBUG 66 , cil 67#endif 68 ) { 69 Subtarget = &TM.getSubtarget<X86Subtarget>(); 70 StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 71 X86ScalarSSEf64 = Subtarget->hasSSE2(); 72 X86ScalarSSEf32 = Subtarget->hasSSE1(); 73 } 74 75 virtual bool TargetSelectInstruction(const Instruction *I); 76 77#include "X86GenFastISel.inc" 78 79private: 80 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT); 81 82 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR); 83 84 bool X86FastEmitStore(EVT VT, const Value *Val, 85 const X86AddressMode &AM); 86 bool X86FastEmitStore(EVT VT, unsigned Val, 87 const X86AddressMode &AM); 88 89 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 90 unsigned &ResultReg); 91 92 bool X86SelectAddress(const Value *V, X86AddressMode &AM); 93 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM); 94 95 bool X86SelectLoad(const Instruction *I); 96 97 bool X86SelectStore(const Instruction *I); 98 99 bool X86SelectCmp(const Instruction *I); 100 101 bool X86SelectZExt(const Instruction *I); 102 103 bool X86SelectBranch(const Instruction *I); 104 105 bool X86SelectShift(const Instruction *I); 106 107 bool X86SelectSelect(const Instruction *I); 108 109 bool X86SelectTrunc(const Instruction *I); 110 111 bool X86SelectFPExt(const Instruction *I); 112 bool X86SelectFPTrunc(const Instruction *I); 113 114 bool X86SelectExtractValue(const Instruction *I); 115 116 bool X86VisitIntrinsicCall(const IntrinsicInst &I); 117 bool X86SelectCall(const Instruction *I); 118 119 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false); 120 121 const X86InstrInfo *getInstrInfo() const { 122 return getTargetMachine()->getInstrInfo(); 123 } 124 const X86TargetMachine *getTargetMachine() const { 125 return static_cast<const X86TargetMachine *>(&TM); 126 } 127 128 unsigned TargetMaterializeConstant(const Constant *C); 129 130 unsigned TargetMaterializeAlloca(const AllocaInst *C); 131 132 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 133 /// computed in an SSE register, not on the X87 floating point stack. 134 bool isScalarFPTypeInSSEReg(EVT VT) const { 135 return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 136 (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 137 } 138 139 bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false); 140}; 141 142} // end anonymous namespace. 143 144bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) { 145 VT = TLI.getValueType(Ty, /*HandleUnknown=*/true); 146 if (VT == MVT::Other || !VT.isSimple()) 147 // Unhandled type. Halt "fast" selection and bail. 148 return false; 149 150 // For now, require SSE/SSE2 for performing floating-point operations, 151 // since x87 requires additional work. 152 if (VT == MVT::f64 && !X86ScalarSSEf64) 153 return false; 154 if (VT == MVT::f32 && !X86ScalarSSEf32) 155 return false; 156 // Similarly, no f80 support yet. 157 if (VT == MVT::f80) 158 return false; 159 // We only handle legal types. For example, on x86-32 the instruction 160 // selector contains all of the 64-bit instructions from x86-64, 161 // under the assumption that i64 won't be used if the target doesn't 162 // support it. 163 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT); 164} 165 166#include "X86GenCallingConv.inc" 167 168/// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling 169/// convention. 170CCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC, 171 bool isTaillCall) { 172 if (Subtarget->is64Bit()) { 173 if (CC == CallingConv::GHC) 174 return CC_X86_64_GHC; 175 else if (Subtarget->isTargetWin64()) 176 return CC_X86_Win64_C; 177 else 178 return CC_X86_64_C; 179 } 180 181 if (CC == CallingConv::X86_FastCall) 182 return CC_X86_32_FastCall; 183 else if (CC == CallingConv::X86_ThisCall) 184 return CC_X86_32_ThisCall; 185 else if (CC == CallingConv::Fast) 186 return CC_X86_32_FastCC; 187 else if (CC == CallingConv::GHC) 188 return CC_X86_32_GHC; 189 else 190 return CC_X86_32_C; 191} 192 193/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT. 194/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV. 195/// Return true and the result register by reference if it is possible. 196bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, 197 unsigned &ResultReg) { 198 // Get opcode and regclass of the output for the given load instruction. 199 unsigned Opc = 0; 200 const TargetRegisterClass *RC = NULL; 201 switch (VT.getSimpleVT().SimpleTy) { 202 default: return false; 203 case MVT::i1: 204 case MVT::i8: 205 Opc = X86::MOV8rm; 206 RC = X86::GR8RegisterClass; 207 break; 208 case MVT::i16: 209 Opc = X86::MOV16rm; 210 RC = X86::GR16RegisterClass; 211 break; 212 case MVT::i32: 213 Opc = X86::MOV32rm; 214 RC = X86::GR32RegisterClass; 215 break; 216 case MVT::i64: 217 // Must be in x86-64 mode. 218 Opc = X86::MOV64rm; 219 RC = X86::GR64RegisterClass; 220 break; 221 case MVT::f32: 222 if (Subtarget->hasSSE1()) { 223 Opc = X86::MOVSSrm; 224 RC = X86::FR32RegisterClass; 225 } else { 226 Opc = X86::LD_Fp32m; 227 RC = X86::RFP32RegisterClass; 228 } 229 break; 230 case MVT::f64: 231 if (Subtarget->hasSSE2()) { 232 Opc = X86::MOVSDrm; 233 RC = X86::FR64RegisterClass; 234 } else { 235 Opc = X86::LD_Fp64m; 236 RC = X86::RFP64RegisterClass; 237 } 238 break; 239 case MVT::f80: 240 // No f80 support yet. 241 return false; 242 } 243 244 ResultReg = createResultReg(RC); 245 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 246 return true; 247} 248 249/// X86FastEmitStore - Emit a machine instruction to store a value Val of 250/// type VT. The address is either pre-computed, consisted of a base ptr, Ptr 251/// and a displacement offset, or a GlobalAddress, 252/// i.e. V. Return true if it is possible. 253bool 254X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, 255 const X86AddressMode &AM) { 256 // Get opcode and regclass of the output for the given store instruction. 257 unsigned Opc = 0; 258 switch (VT.getSimpleVT().SimpleTy) { 259 case MVT::f80: // No f80 support yet. 260 default: return false; 261 case MVT::i1: { 262 // Mask out all but lowest bit. 263 unsigned AndResult = createResultReg(X86::GR8RegisterClass); 264 BuildMI(MBB, DL, 265 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1); 266 Val = AndResult; 267 } 268 // FALLTHROUGH, handling i1 as i8. 269 case MVT::i8: Opc = X86::MOV8mr; break; 270 case MVT::i16: Opc = X86::MOV16mr; break; 271 case MVT::i32: Opc = X86::MOV32mr; break; 272 case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode. 273 case MVT::f32: 274 Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m; 275 break; 276 case MVT::f64: 277 Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m; 278 break; 279 } 280 281 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val); 282 return true; 283} 284 285bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val, 286 const X86AddressMode &AM) { 287 // Handle 'null' like i32/i64 0. 288 if (isa<ConstantPointerNull>(Val)) 289 Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext())); 290 291 // If this is a store of a simple constant, fold the constant into the store. 292 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) { 293 unsigned Opc = 0; 294 bool Signed = true; 295 switch (VT.getSimpleVT().SimpleTy) { 296 default: break; 297 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8. 298 case MVT::i8: Opc = X86::MOV8mi; break; 299 case MVT::i16: Opc = X86::MOV16mi; break; 300 case MVT::i32: Opc = X86::MOV32mi; break; 301 case MVT::i64: 302 // Must be a 32-bit sign extended value. 303 if ((int)CI->getSExtValue() == CI->getSExtValue()) 304 Opc = X86::MOV64mi32; 305 break; 306 } 307 308 if (Opc) { 309 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM) 310 .addImm(Signed ? (uint64_t) CI->getSExtValue() : 311 CI->getZExtValue()); 312 return true; 313 } 314 } 315 316 unsigned ValReg = getRegForValue(Val); 317 if (ValReg == 0) 318 return false; 319 320 return X86FastEmitStore(VT, ValReg, AM); 321} 322 323/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of 324/// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 325/// ISD::SIGN_EXTEND). 326bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, 327 unsigned Src, EVT SrcVT, 328 unsigned &ResultReg) { 329 unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, 330 Src, /*TODO: Kill=*/false); 331 332 if (RR != 0) { 333 ResultReg = RR; 334 return true; 335 } else 336 return false; 337} 338 339/// X86SelectAddress - Attempt to fill in an address from the given value. 340/// 341bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) { 342 const User *U = NULL; 343 unsigned Opcode = Instruction::UserOp1; 344 if (const Instruction *I = dyn_cast<Instruction>(V)) { 345 Opcode = I->getOpcode(); 346 U = I; 347 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 348 Opcode = C->getOpcode(); 349 U = C; 350 } 351 352 switch (Opcode) { 353 default: break; 354 case Instruction::BitCast: 355 // Look past bitcasts. 356 return X86SelectAddress(U->getOperand(0), AM); 357 358 case Instruction::IntToPtr: 359 // Look past no-op inttoptrs. 360 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 361 return X86SelectAddress(U->getOperand(0), AM); 362 break; 363 364 case Instruction::PtrToInt: 365 // Look past no-op ptrtoints. 366 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 367 return X86SelectAddress(U->getOperand(0), AM); 368 break; 369 370 case Instruction::Alloca: { 371 // Do static allocas. 372 const AllocaInst *A = cast<AllocaInst>(V); 373 DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A); 374 if (SI != StaticAllocaMap.end()) { 375 AM.BaseType = X86AddressMode::FrameIndexBase; 376 AM.Base.FrameIndex = SI->second; 377 return true; 378 } 379 break; 380 } 381 382 case Instruction::Add: { 383 // Adds of constants are common and easy enough. 384 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) { 385 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue(); 386 // They have to fit in the 32-bit signed displacement field though. 387 if (isInt<32>(Disp)) { 388 AM.Disp = (uint32_t)Disp; 389 return X86SelectAddress(U->getOperand(0), AM); 390 } 391 } 392 break; 393 } 394 395 case Instruction::GetElementPtr: { 396 X86AddressMode SavedAM = AM; 397 398 // Pattern-match simple GEPs. 399 uint64_t Disp = (int32_t)AM.Disp; 400 unsigned IndexReg = AM.IndexReg; 401 unsigned Scale = AM.Scale; 402 gep_type_iterator GTI = gep_type_begin(U); 403 // Iterate through the indices, folding what we can. Constants can be 404 // folded, and one dynamic index can be handled, if the scale is supported. 405 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); 406 i != e; ++i, ++GTI) { 407 const Value *Op = *i; 408 if (const StructType *STy = dyn_cast<StructType>(*GTI)) { 409 const StructLayout *SL = TD.getStructLayout(STy); 410 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 411 Disp += SL->getElementOffset(Idx); 412 } else { 413 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); 414 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 415 // Constant-offset addressing. 416 Disp += CI->getSExtValue() * S; 417 } else if (IndexReg == 0 && 418 (!AM.GV || !Subtarget->isPICStyleRIPRel()) && 419 (S == 1 || S == 2 || S == 4 || S == 8)) { 420 // Scaled-index addressing. 421 Scale = S; 422 IndexReg = getRegForGEPIndex(Op).first; 423 if (IndexReg == 0) 424 return false; 425 } else 426 // Unsupported. 427 goto unsupported_gep; 428 } 429 } 430 // Check for displacement overflow. 431 if (!isInt<32>(Disp)) 432 break; 433 // Ok, the GEP indices were covered by constant-offset and scaled-index 434 // addressing. Update the address state and move on to examining the base. 435 AM.IndexReg = IndexReg; 436 AM.Scale = Scale; 437 AM.Disp = (uint32_t)Disp; 438 if (X86SelectAddress(U->getOperand(0), AM)) 439 return true; 440 441 // If we couldn't merge the sub value into this addr mode, revert back to 442 // our address and just match the value instead of completely failing. 443 AM = SavedAM; 444 break; 445 unsupported_gep: 446 // Ok, the GEP indices weren't all covered. 447 break; 448 } 449 } 450 451 // Handle constant address. 452 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 453 // Can't handle alternate code models yet. 454 if (TM.getCodeModel() != CodeModel::Small) 455 return false; 456 457 // RIP-relative addresses can't have additional register operands. 458 if (Subtarget->isPICStyleRIPRel() && 459 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 460 return false; 461 462 // Can't handle TLS yet. 463 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 464 if (GVar->isThreadLocal()) 465 return false; 466 467 // Okay, we've committed to selecting this global. Set up the basic address. 468 AM.GV = GV; 469 470 // Allow the subtarget to classify the global. 471 unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM); 472 473 // If this reference is relative to the pic base, set it now. 474 if (isGlobalRelativeToPICBase(GVFlags)) { 475 // FIXME: How do we know Base.Reg is free?? 476 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF); 477 } 478 479 // Unless the ABI requires an extra load, return a direct reference to 480 // the global. 481 if (!isGlobalStubReference(GVFlags)) { 482 if (Subtarget->isPICStyleRIPRel()) { 483 // Use rip-relative addressing if we can. Above we verified that the 484 // base and index registers are unused. 485 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 486 AM.Base.Reg = X86::RIP; 487 } 488 AM.GVOpFlags = GVFlags; 489 return true; 490 } 491 492 // Ok, we need to do a load from a stub. If we've already loaded from this 493 // stub, reuse the loaded pointer, otherwise emit the load now. 494 DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V); 495 unsigned LoadReg; 496 if (I != LocalValueMap.end() && I->second != 0) { 497 LoadReg = I->second; 498 } else { 499 // Issue load from stub. 500 unsigned Opc = 0; 501 const TargetRegisterClass *RC = NULL; 502 X86AddressMode StubAM; 503 StubAM.Base.Reg = AM.Base.Reg; 504 StubAM.GV = GV; 505 StubAM.GVOpFlags = GVFlags; 506 507 if (TLI.getPointerTy() == MVT::i64) { 508 Opc = X86::MOV64rm; 509 RC = X86::GR64RegisterClass; 510 511 if (Subtarget->isPICStyleRIPRel()) 512 StubAM.Base.Reg = X86::RIP; 513 } else { 514 Opc = X86::MOV32rm; 515 RC = X86::GR32RegisterClass; 516 } 517 518 LoadReg = createResultReg(RC); 519 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM); 520 521 // Prevent loading GV stub multiple times in same MBB. 522 LocalValueMap[V] = LoadReg; 523 } 524 525 // Now construct the final address. Note that the Disp, Scale, 526 // and Index values may already be set here. 527 AM.Base.Reg = LoadReg; 528 AM.GV = 0; 529 return true; 530 } 531 532 // If all else fails, try to materialize the value in a register. 533 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 534 if (AM.Base.Reg == 0) { 535 AM.Base.Reg = getRegForValue(V); 536 return AM.Base.Reg != 0; 537 } 538 if (AM.IndexReg == 0) { 539 assert(AM.Scale == 1 && "Scale with no index!"); 540 AM.IndexReg = getRegForValue(V); 541 return AM.IndexReg != 0; 542 } 543 } 544 545 return false; 546} 547 548/// X86SelectCallAddress - Attempt to fill in an address from the given value. 549/// 550bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) { 551 const User *U = NULL; 552 unsigned Opcode = Instruction::UserOp1; 553 if (const Instruction *I = dyn_cast<Instruction>(V)) { 554 Opcode = I->getOpcode(); 555 U = I; 556 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 557 Opcode = C->getOpcode(); 558 U = C; 559 } 560 561 switch (Opcode) { 562 default: break; 563 case Instruction::BitCast: 564 // Look past bitcasts. 565 return X86SelectCallAddress(U->getOperand(0), AM); 566 567 case Instruction::IntToPtr: 568 // Look past no-op inttoptrs. 569 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 570 return X86SelectCallAddress(U->getOperand(0), AM); 571 break; 572 573 case Instruction::PtrToInt: 574 // Look past no-op ptrtoints. 575 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 576 return X86SelectCallAddress(U->getOperand(0), AM); 577 break; 578 } 579 580 // Handle constant address. 581 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 582 // Can't handle alternate code models yet. 583 if (TM.getCodeModel() != CodeModel::Small) 584 return false; 585 586 // RIP-relative addresses can't have additional register operands. 587 if (Subtarget->isPICStyleRIPRel() && 588 (AM.Base.Reg != 0 || AM.IndexReg != 0)) 589 return false; 590 591 // Can't handle TLS or DLLImport. 592 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 593 if (GVar->isThreadLocal() || GVar->hasDLLImportLinkage()) 594 return false; 595 596 // Okay, we've committed to selecting this global. Set up the basic address. 597 AM.GV = GV; 598 599 // No ABI requires an extra load for anything other than DLLImport, which 600 // we rejected above. Return a direct reference to the global. 601 if (Subtarget->isPICStyleRIPRel()) { 602 // Use rip-relative addressing if we can. Above we verified that the 603 // base and index registers are unused. 604 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 605 AM.Base.Reg = X86::RIP; 606 } else if (Subtarget->isPICStyleStubPIC()) { 607 AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET; 608 } else if (Subtarget->isPICStyleGOT()) { 609 AM.GVOpFlags = X86II::MO_GOTOFF; 610 } 611 612 return true; 613 } 614 615 // If all else fails, try to materialize the value in a register. 616 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 617 if (AM.Base.Reg == 0) { 618 AM.Base.Reg = getRegForValue(V); 619 return AM.Base.Reg != 0; 620 } 621 if (AM.IndexReg == 0) { 622 assert(AM.Scale == 1 && "Scale with no index!"); 623 AM.IndexReg = getRegForValue(V); 624 return AM.IndexReg != 0; 625 } 626 } 627 628 return false; 629} 630 631 632/// X86SelectStore - Select and emit code to implement store instructions. 633bool X86FastISel::X86SelectStore(const Instruction *I) { 634 EVT VT; 635 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true)) 636 return false; 637 638 X86AddressMode AM; 639 if (!X86SelectAddress(I->getOperand(1), AM)) 640 return false; 641 642 return X86FastEmitStore(VT, I->getOperand(0), AM); 643} 644 645/// X86SelectLoad - Select and emit code to implement load instructions. 646/// 647bool X86FastISel::X86SelectLoad(const Instruction *I) { 648 EVT VT; 649 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true)) 650 return false; 651 652 X86AddressMode AM; 653 if (!X86SelectAddress(I->getOperand(0), AM)) 654 return false; 655 656 unsigned ResultReg = 0; 657 if (X86FastEmitLoad(VT, AM, ResultReg)) { 658 UpdateValueMap(I, ResultReg); 659 return true; 660 } 661 return false; 662} 663 664static unsigned X86ChooseCmpOpcode(EVT VT) { 665 switch (VT.getSimpleVT().SimpleTy) { 666 default: return 0; 667 case MVT::i8: return X86::CMP8rr; 668 case MVT::i16: return X86::CMP16rr; 669 case MVT::i32: return X86::CMP32rr; 670 case MVT::i64: return X86::CMP64rr; 671 case MVT::f32: return X86::UCOMISSrr; 672 case MVT::f64: return X86::UCOMISDrr; 673 } 674} 675 676/// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS 677/// of the comparison, return an opcode that works for the compare (e.g. 678/// CMP32ri) otherwise return 0. 679static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) { 680 switch (VT.getSimpleVT().SimpleTy) { 681 // Otherwise, we can't fold the immediate into this comparison. 682 default: return 0; 683 case MVT::i8: return X86::CMP8ri; 684 case MVT::i16: return X86::CMP16ri; 685 case MVT::i32: return X86::CMP32ri; 686 case MVT::i64: 687 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext 688 // field. 689 if ((int)RHSC->getSExtValue() == RHSC->getSExtValue()) 690 return X86::CMP64ri32; 691 return 0; 692 } 693} 694 695bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, 696 EVT VT) { 697 unsigned Op0Reg = getRegForValue(Op0); 698 if (Op0Reg == 0) return false; 699 700 // Handle 'null' like i32/i64 0. 701 if (isa<ConstantPointerNull>(Op1)) 702 Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext())); 703 704 // We have two options: compare with register or immediate. If the RHS of 705 // the compare is an immediate that we can fold into this compare, use 706 // CMPri, otherwise use CMPrr. 707 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) { 708 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) { 709 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg) 710 .addImm(Op1C->getSExtValue()); 711 return true; 712 } 713 } 714 715 unsigned CompareOpc = X86ChooseCmpOpcode(VT); 716 if (CompareOpc == 0) return false; 717 718 unsigned Op1Reg = getRegForValue(Op1); 719 if (Op1Reg == 0) return false; 720 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg); 721 722 return true; 723} 724 725bool X86FastISel::X86SelectCmp(const Instruction *I) { 726 const CmpInst *CI = cast<CmpInst>(I); 727 728 EVT VT; 729 if (!isTypeLegal(I->getOperand(0)->getType(), VT)) 730 return false; 731 732 unsigned ResultReg = createResultReg(&X86::GR8RegClass); 733 unsigned SetCCOpc; 734 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 735 switch (CI->getPredicate()) { 736 case CmpInst::FCMP_OEQ: { 737 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 738 return false; 739 740 unsigned EReg = createResultReg(&X86::GR8RegClass); 741 unsigned NPReg = createResultReg(&X86::GR8RegClass); 742 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg); 743 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg); 744 BuildMI(MBB, DL, 745 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg); 746 UpdateValueMap(I, ResultReg); 747 return true; 748 } 749 case CmpInst::FCMP_UNE: { 750 if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 751 return false; 752 753 unsigned NEReg = createResultReg(&X86::GR8RegClass); 754 unsigned PReg = createResultReg(&X86::GR8RegClass); 755 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg); 756 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg); 757 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg); 758 UpdateValueMap(I, ResultReg); 759 return true; 760 } 761 case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 762 case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 763 case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break; 764 case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break; 765 case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 766 case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break; 767 case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break; 768 case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 769 case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break; 770 case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break; 771 case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 772 case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 773 774 case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 775 case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 776 case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 777 case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 778 case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 779 case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 780 case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break; 781 case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break; 782 case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break; 783 case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break; 784 default: 785 return false; 786 } 787 788 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 789 if (SwapArgs) 790 std::swap(Op0, Op1); 791 792 // Emit a compare of Op0/Op1. 793 if (!X86FastEmitCompare(Op0, Op1, VT)) 794 return false; 795 796 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg); 797 UpdateValueMap(I, ResultReg); 798 return true; 799} 800 801bool X86FastISel::X86SelectZExt(const Instruction *I) { 802 // Handle zero-extension from i1 to i8, which is common. 803 if (I->getType()->isIntegerTy(8) && 804 I->getOperand(0)->getType()->isIntegerTy(1)) { 805 unsigned ResultReg = getRegForValue(I->getOperand(0)); 806 if (ResultReg == 0) return false; 807 // Set the high bits to zero. 808 ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg, /*TODO: Kill=*/false); 809 if (ResultReg == 0) return false; 810 UpdateValueMap(I, ResultReg); 811 return true; 812 } 813 814 return false; 815} 816 817 818bool X86FastISel::X86SelectBranch(const Instruction *I) { 819 // Unconditional branches are selected by tablegen-generated code. 820 // Handle a conditional branch. 821 const BranchInst *BI = cast<BranchInst>(I); 822 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)]; 823 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)]; 824 825 // Fold the common case of a conditional branch with a comparison. 826 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 827 if (CI->hasOneUse()) { 828 EVT VT = TLI.getValueType(CI->getOperand(0)->getType()); 829 830 // Try to take advantage of fallthrough opportunities. 831 CmpInst::Predicate Predicate = CI->getPredicate(); 832 if (MBB->isLayoutSuccessor(TrueMBB)) { 833 std::swap(TrueMBB, FalseMBB); 834 Predicate = CmpInst::getInversePredicate(Predicate); 835 } 836 837 bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 838 unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA" 839 840 switch (Predicate) { 841 case CmpInst::FCMP_OEQ: 842 std::swap(TrueMBB, FalseMBB); 843 Predicate = CmpInst::FCMP_UNE; 844 // FALL THROUGH 845 case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 846 case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 847 case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 848 case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break; 849 case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break; 850 case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 851 case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break; 852 case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break; 853 case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 854 case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break; 855 case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break; 856 case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 857 case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 858 859 case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 860 case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 861 case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 862 case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 863 case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 864 case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 865 case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break; 866 case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break; 867 case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break; 868 case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break; 869 default: 870 return false; 871 } 872 873 const Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 874 if (SwapArgs) 875 std::swap(Op0, Op1); 876 877 // Emit a compare of the LHS and RHS, setting the flags. 878 if (!X86FastEmitCompare(Op0, Op1, VT)) 879 return false; 880 881 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB); 882 883 if (Predicate == CmpInst::FCMP_UNE) { 884 // X86 requires a second branch to handle UNE (and OEQ, 885 // which is mapped to UNE above). 886 BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB); 887 } 888 889 FastEmitBranch(FalseMBB); 890 MBB->addSuccessor(TrueMBB); 891 return true; 892 } 893 } else if (ExtractValueInst *EI = 894 dyn_cast<ExtractValueInst>(BI->getCondition())) { 895 // Check to see if the branch instruction is from an "arithmetic with 896 // overflow" intrinsic. The main way these intrinsics are used is: 897 // 898 // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) 899 // %sum = extractvalue { i32, i1 } %t, 0 900 // %obit = extractvalue { i32, i1 } %t, 1 901 // br i1 %obit, label %overflow, label %normal 902 // 903 // The %sum and %obit are converted in an ADD and a SETO/SETB before 904 // reaching the branch. Therefore, we search backwards through the MBB 905 // looking for the SETO/SETB instruction. If an instruction modifies the 906 // EFLAGS register before we reach the SETO/SETB instruction, then we can't 907 // convert the branch into a JO/JB instruction. 908 if (const IntrinsicInst *CI = 909 dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){ 910 if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow || 911 CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) { 912 const MachineInstr *SetMI = 0; 913 unsigned Reg = lookUpRegForValue(EI); 914 915 for (MachineBasicBlock::const_reverse_iterator 916 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) { 917 const MachineInstr &MI = *RI; 918 919 if (MI.definesRegister(Reg)) { 920 unsigned Src, Dst, SrcSR, DstSR; 921 922 if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) { 923 Reg = Src; 924 continue; 925 } 926 927 SetMI = &MI; 928 break; 929 } 930 931 const TargetInstrDesc &TID = MI.getDesc(); 932 if (TID.hasUnmodeledSideEffects() || 933 TID.hasImplicitDefOfPhysReg(X86::EFLAGS)) 934 break; 935 } 936 937 if (SetMI) { 938 unsigned OpCode = SetMI->getOpcode(); 939 940 if (OpCode == X86::SETOr || OpCode == X86::SETBr) { 941 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? 942 X86::JO_4 : X86::JB_4)) 943 .addMBB(TrueMBB); 944 FastEmitBranch(FalseMBB); 945 MBB->addSuccessor(TrueMBB); 946 return true; 947 } 948 } 949 } 950 } 951 } 952 953 // Otherwise do a clumsy setcc and re-test it. 954 unsigned OpReg = getRegForValue(BI->getCondition()); 955 if (OpReg == 0) return false; 956 957 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg); 958 BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB); 959 FastEmitBranch(FalseMBB); 960 MBB->addSuccessor(TrueMBB); 961 return true; 962} 963 964bool X86FastISel::X86SelectShift(const Instruction *I) { 965 unsigned CReg = 0, OpReg = 0, OpImm = 0; 966 const TargetRegisterClass *RC = NULL; 967 if (I->getType()->isIntegerTy(8)) { 968 CReg = X86::CL; 969 RC = &X86::GR8RegClass; 970 switch (I->getOpcode()) { 971 case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break; 972 case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break; 973 case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break; 974 default: return false; 975 } 976 } else if (I->getType()->isIntegerTy(16)) { 977 CReg = X86::CX; 978 RC = &X86::GR16RegClass; 979 switch (I->getOpcode()) { 980 case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break; 981 case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break; 982 case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break; 983 default: return false; 984 } 985 } else if (I->getType()->isIntegerTy(32)) { 986 CReg = X86::ECX; 987 RC = &X86::GR32RegClass; 988 switch (I->getOpcode()) { 989 case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break; 990 case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break; 991 case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break; 992 default: return false; 993 } 994 } else if (I->getType()->isIntegerTy(64)) { 995 CReg = X86::RCX; 996 RC = &X86::GR64RegClass; 997 switch (I->getOpcode()) { 998 case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break; 999 case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break; 1000 case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break; 1001 default: return false; 1002 } 1003 } else { 1004 return false; 1005 } 1006 1007 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 1008 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 1009 return false; 1010 1011 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 1012 if (Op0Reg == 0) return false; 1013 1014 // Fold immediate in shl(x,3). 1015 if (const ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 1016 unsigned ResultReg = createResultReg(RC); 1017 BuildMI(MBB, DL, TII.get(OpImm), 1018 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff); 1019 UpdateValueMap(I, ResultReg); 1020 return true; 1021 } 1022 1023 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1024 if (Op1Reg == 0) return false; 1025 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC, DL); 1026 1027 // The shift instruction uses X86::CL. If we defined a super-register 1028 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what 1029 // we're doing here. 1030 if (CReg != X86::CL) 1031 BuildMI(MBB, DL, TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL) 1032 .addReg(CReg).addImm(X86::sub_8bit); 1033 1034 unsigned ResultReg = createResultReg(RC); 1035 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg); 1036 UpdateValueMap(I, ResultReg); 1037 return true; 1038} 1039 1040bool X86FastISel::X86SelectSelect(const Instruction *I) { 1041 EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 1042 if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 1043 return false; 1044 1045 unsigned Opc = 0; 1046 const TargetRegisterClass *RC = NULL; 1047 if (VT.getSimpleVT() == MVT::i16) { 1048 Opc = X86::CMOVE16rr; 1049 RC = &X86::GR16RegClass; 1050 } else if (VT.getSimpleVT() == MVT::i32) { 1051 Opc = X86::CMOVE32rr; 1052 RC = &X86::GR32RegClass; 1053 } else if (VT.getSimpleVT() == MVT::i64) { 1054 Opc = X86::CMOVE64rr; 1055 RC = &X86::GR64RegClass; 1056 } else { 1057 return false; 1058 } 1059 1060 unsigned Op0Reg = getRegForValue(I->getOperand(0)); 1061 if (Op0Reg == 0) return false; 1062 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1063 if (Op1Reg == 0) return false; 1064 unsigned Op2Reg = getRegForValue(I->getOperand(2)); 1065 if (Op2Reg == 0) return false; 1066 1067 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg); 1068 unsigned ResultReg = createResultReg(RC); 1069 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg); 1070 UpdateValueMap(I, ResultReg); 1071 return true; 1072} 1073 1074bool X86FastISel::X86SelectFPExt(const Instruction *I) { 1075 // fpext from float to double. 1076 if (Subtarget->hasSSE2() && 1077 I->getType()->isDoubleTy()) { 1078 const Value *V = I->getOperand(0); 1079 if (V->getType()->isFloatTy()) { 1080 unsigned OpReg = getRegForValue(V); 1081 if (OpReg == 0) return false; 1082 unsigned ResultReg = createResultReg(X86::FR64RegisterClass); 1083 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg); 1084 UpdateValueMap(I, ResultReg); 1085 return true; 1086 } 1087 } 1088 1089 return false; 1090} 1091 1092bool X86FastISel::X86SelectFPTrunc(const Instruction *I) { 1093 if (Subtarget->hasSSE2()) { 1094 if (I->getType()->isFloatTy()) { 1095 const Value *V = I->getOperand(0); 1096 if (V->getType()->isDoubleTy()) { 1097 unsigned OpReg = getRegForValue(V); 1098 if (OpReg == 0) return false; 1099 unsigned ResultReg = createResultReg(X86::FR32RegisterClass); 1100 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg); 1101 UpdateValueMap(I, ResultReg); 1102 return true; 1103 } 1104 } 1105 } 1106 1107 return false; 1108} 1109 1110bool X86FastISel::X86SelectTrunc(const Instruction *I) { 1111 if (Subtarget->is64Bit()) 1112 // All other cases should be handled by the tblgen generated code. 1113 return false; 1114 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1115 EVT DstVT = TLI.getValueType(I->getType()); 1116 1117 // This code only handles truncation to byte right now. 1118 if (DstVT != MVT::i8 && DstVT != MVT::i1) 1119 // All other cases should be handled by the tblgen generated code. 1120 return false; 1121 if (SrcVT != MVT::i16 && SrcVT != MVT::i32) 1122 // All other cases should be handled by the tblgen generated code. 1123 return false; 1124 1125 unsigned InputReg = getRegForValue(I->getOperand(0)); 1126 if (!InputReg) 1127 // Unhandled operand. Halt "fast" selection and bail. 1128 return false; 1129 1130 // First issue a copy to GR16_ABCD or GR32_ABCD. 1131 unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr; 1132 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) 1133 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass; 1134 unsigned CopyReg = createResultReg(CopyRC); 1135 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg); 1136 1137 // Then issue an extract_subreg. 1138 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, 1139 CopyReg, /*Kill=*/true, 1140 X86::sub_8bit); 1141 if (!ResultReg) 1142 return false; 1143 1144 UpdateValueMap(I, ResultReg); 1145 return true; 1146} 1147 1148bool X86FastISel::X86SelectExtractValue(const Instruction *I) { 1149 const ExtractValueInst *EI = cast<ExtractValueInst>(I); 1150 const Value *Agg = EI->getAggregateOperand(); 1151 1152 if (const IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) { 1153 switch (CI->getIntrinsicID()) { 1154 default: break; 1155 case Intrinsic::sadd_with_overflow: 1156 case Intrinsic::uadd_with_overflow: 1157 // Cheat a little. We know that the registers for "add" and "seto" are 1158 // allocated sequentially. However, we only keep track of the register 1159 // for "add" in the value map. Use extractvalue's index to get the 1160 // correct register for "seto". 1161 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin()); 1162 return true; 1163 } 1164 } 1165 1166 return false; 1167} 1168 1169bool X86FastISel::X86VisitIntrinsicCall(const IntrinsicInst &I) { 1170 // FIXME: Handle more intrinsics. 1171 switch (I.getIntrinsicID()) { 1172 default: return false; 1173 case Intrinsic::stackprotector: { 1174 // Emit code inline code to store the stack guard onto the stack. 1175 EVT PtrTy = TLI.getPointerTy(); 1176 1177 const Value *Op1 = I.getOperand(1); // The guard's value. 1178 const AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2)); 1179 1180 // Grab the frame index. 1181 X86AddressMode AM; 1182 if (!X86SelectAddress(Slot, AM)) return false; 1183 1184 if (!X86FastEmitStore(PtrTy, Op1, AM)) return false; 1185 1186 return true; 1187 } 1188 case Intrinsic::objectsize: { 1189 ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2)); 1190 const Type *Ty = I.getCalledFunction()->getReturnType(); 1191 1192 assert(CI && "Non-constant type in Intrinsic::objectsize?"); 1193 1194 EVT VT; 1195 if (!isTypeLegal(Ty, VT)) 1196 return false; 1197 1198 unsigned OpC = 0; 1199 if (VT == MVT::i32) 1200 OpC = X86::MOV32ri; 1201 else if (VT == MVT::i64) 1202 OpC = X86::MOV64ri; 1203 else 1204 return false; 1205 1206 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 1207 BuildMI(MBB, DL, TII.get(OpC), ResultReg). 1208 addImm(CI->getZExtValue() == 0 ? -1ULL : 0); 1209 UpdateValueMap(&I, ResultReg); 1210 return true; 1211 } 1212 case Intrinsic::dbg_declare: { 1213 const DbgDeclareInst *DI = cast<DbgDeclareInst>(&I); 1214 X86AddressMode AM; 1215 assert(DI->getAddress() && "Null address should be checked earlier!"); 1216 if (!X86SelectAddress(DI->getAddress(), AM)) 1217 return false; 1218 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 1219 // FIXME may need to add RegState::Debug to any registers produced, 1220 // although ESP/EBP should be the only ones at the moment. 1221 addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0). 1222 addMetadata(DI->getVariable()); 1223 return true; 1224 } 1225 case Intrinsic::trap: { 1226 BuildMI(MBB, DL, TII.get(X86::TRAP)); 1227 return true; 1228 } 1229 case Intrinsic::sadd_with_overflow: 1230 case Intrinsic::uadd_with_overflow: { 1231 // Replace "add with overflow" intrinsics with an "add" instruction followed 1232 // by a seto/setc instruction. Later on, when the "extractvalue" 1233 // instructions are encountered, we use the fact that two registers were 1234 // created sequentially to get the correct registers for the "sum" and the 1235 // "overflow bit". 1236 const Function *Callee = I.getCalledFunction(); 1237 const Type *RetTy = 1238 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0)); 1239 1240 EVT VT; 1241 if (!isTypeLegal(RetTy, VT)) 1242 return false; 1243 1244 const Value *Op1 = I.getOperand(1); 1245 const Value *Op2 = I.getOperand(2); 1246 unsigned Reg1 = getRegForValue(Op1); 1247 unsigned Reg2 = getRegForValue(Op2); 1248 1249 if (Reg1 == 0 || Reg2 == 0) 1250 // FIXME: Handle values *not* in registers. 1251 return false; 1252 1253 unsigned OpC = 0; 1254 if (VT == MVT::i32) 1255 OpC = X86::ADD32rr; 1256 else if (VT == MVT::i64) 1257 OpC = X86::ADD64rr; 1258 else 1259 return false; 1260 1261 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 1262 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2); 1263 unsigned DestReg1 = UpdateValueMap(&I, ResultReg); 1264 1265 // If the add with overflow is an intra-block value then we just want to 1266 // create temporaries for it like normal. If it is a cross-block value then 1267 // UpdateValueMap will return the cross-block register used. Since we 1268 // *really* want the value to be live in the register pair known by 1269 // UpdateValueMap, we have to use DestReg1+1 as the destination register in 1270 // the cross block case. In the non-cross-block case, we should just make 1271 // another register for the value. 1272 if (DestReg1 != ResultReg) 1273 ResultReg = DestReg1+1; 1274 else 1275 ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8)); 1276 1277 unsigned Opc = X86::SETBr; 1278 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow) 1279 Opc = X86::SETOr; 1280 BuildMI(MBB, DL, TII.get(Opc), ResultReg); 1281 return true; 1282 } 1283 } 1284} 1285 1286bool X86FastISel::X86SelectCall(const Instruction *I) { 1287 const CallInst *CI = cast<CallInst>(I); 1288 const Value *Callee = I->getOperand(0); 1289 1290 // Can't handle inline asm yet. 1291 if (isa<InlineAsm>(Callee)) 1292 return false; 1293 1294 // Handle intrinsic calls. 1295 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI)) 1296 return X86VisitIntrinsicCall(*II); 1297 1298 // Handle only C and fastcc calling conventions for now. 1299 ImmutableCallSite CS(CI); 1300 CallingConv::ID CC = CS.getCallingConv(); 1301 if (CC != CallingConv::C && 1302 CC != CallingConv::Fast && 1303 CC != CallingConv::X86_FastCall) 1304 return false; 1305 1306 // fastcc with -tailcallopt is intended to provide a guaranteed 1307 // tail call optimization. Fastisel doesn't know how to do that. 1308 if (CC == CallingConv::Fast && GuaranteedTailCallOpt) 1309 return false; 1310 1311 // Let SDISel handle vararg functions. 1312 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 1313 const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 1314 if (FTy->isVarArg()) 1315 return false; 1316 1317 // Handle *simple* calls for now. 1318 const Type *RetTy = CS.getType(); 1319 EVT RetVT; 1320 if (RetTy->isVoidTy()) 1321 RetVT = MVT::isVoid; 1322 else if (!isTypeLegal(RetTy, RetVT, true)) 1323 return false; 1324 1325 // Materialize callee address in a register. FIXME: GV address can be 1326 // handled with a CALLpcrel32 instead. 1327 X86AddressMode CalleeAM; 1328 if (!X86SelectCallAddress(Callee, CalleeAM)) 1329 return false; 1330 unsigned CalleeOp = 0; 1331 const GlobalValue *GV = 0; 1332 if (CalleeAM.GV != 0) { 1333 GV = CalleeAM.GV; 1334 } else if (CalleeAM.Base.Reg != 0) { 1335 CalleeOp = CalleeAM.Base.Reg; 1336 } else 1337 return false; 1338 1339 // Allow calls which produce i1 results. 1340 bool AndToI1 = false; 1341 if (RetVT == MVT::i1) { 1342 RetVT = MVT::i8; 1343 AndToI1 = true; 1344 } 1345 1346 // Deal with call operands first. 1347 SmallVector<const Value *, 8> ArgVals; 1348 SmallVector<unsigned, 8> Args; 1349 SmallVector<EVT, 8> ArgVTs; 1350 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 1351 Args.reserve(CS.arg_size()); 1352 ArgVals.reserve(CS.arg_size()); 1353 ArgVTs.reserve(CS.arg_size()); 1354 ArgFlags.reserve(CS.arg_size()); 1355 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 1356 i != e; ++i) { 1357 unsigned Arg = getRegForValue(*i); 1358 if (Arg == 0) 1359 return false; 1360 ISD::ArgFlagsTy Flags; 1361 unsigned AttrInd = i - CS.arg_begin() + 1; 1362 if (CS.paramHasAttr(AttrInd, Attribute::SExt)) 1363 Flags.setSExt(); 1364 if (CS.paramHasAttr(AttrInd, Attribute::ZExt)) 1365 Flags.setZExt(); 1366 1367 // FIXME: Only handle *easy* calls for now. 1368 if (CS.paramHasAttr(AttrInd, Attribute::InReg) || 1369 CS.paramHasAttr(AttrInd, Attribute::StructRet) || 1370 CS.paramHasAttr(AttrInd, Attribute::Nest) || 1371 CS.paramHasAttr(AttrInd, Attribute::ByVal)) 1372 return false; 1373 1374 const Type *ArgTy = (*i)->getType(); 1375 EVT ArgVT; 1376 if (!isTypeLegal(ArgTy, ArgVT)) 1377 return false; 1378 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 1379 Flags.setOrigAlign(OriginalAlignment); 1380 1381 Args.push_back(Arg); 1382 ArgVals.push_back(*i); 1383 ArgVTs.push_back(ArgVT); 1384 ArgFlags.push_back(Flags); 1385 } 1386 1387 // Analyze operands of the call, assigning locations to each operand. 1388 SmallVector<CCValAssign, 16> ArgLocs; 1389 CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext()); 1390 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC)); 1391 1392 // Get a count of how many bytes are to be pushed on the stack. 1393 unsigned NumBytes = CCInfo.getNextStackOffset(); 1394 1395 // Issue CALLSEQ_START 1396 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode(); 1397 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes); 1398 1399 // Process argument: walk the register/memloc assignments, inserting 1400 // copies / loads. 1401 SmallVector<unsigned, 4> RegArgs; 1402 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1403 CCValAssign &VA = ArgLocs[i]; 1404 unsigned Arg = Args[VA.getValNo()]; 1405 EVT ArgVT = ArgVTs[VA.getValNo()]; 1406 1407 // Promote the value if needed. 1408 switch (VA.getLocInfo()) { 1409 default: llvm_unreachable("Unknown loc info!"); 1410 case CCValAssign::Full: break; 1411 case CCValAssign::SExt: { 1412 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1413 Arg, ArgVT, Arg); 1414 assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted; 1415 Emitted = true; 1416 ArgVT = VA.getLocVT(); 1417 break; 1418 } 1419 case CCValAssign::ZExt: { 1420 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1421 Arg, ArgVT, Arg); 1422 assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted; 1423 Emitted = true; 1424 ArgVT = VA.getLocVT(); 1425 break; 1426 } 1427 case CCValAssign::AExt: { 1428 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), 1429 Arg, ArgVT, Arg); 1430 if (!Emitted) 1431 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 1432 Arg, ArgVT, Arg); 1433 if (!Emitted) 1434 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 1435 Arg, ArgVT, Arg); 1436 1437 assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted; 1438 ArgVT = VA.getLocVT(); 1439 break; 1440 } 1441 case CCValAssign::BCvt: { 1442 unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(), 1443 ISD::BIT_CONVERT, Arg, /*TODO: Kill=*/false); 1444 assert(BC != 0 && "Failed to emit a bitcast!"); 1445 Arg = BC; 1446 ArgVT = VA.getLocVT(); 1447 break; 1448 } 1449 } 1450 1451 if (VA.isRegLoc()) { 1452 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT); 1453 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(), 1454 Arg, RC, RC, DL); 1455 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1456 Emitted = true; 1457 RegArgs.push_back(VA.getLocReg()); 1458 } else { 1459 unsigned LocMemOffset = VA.getLocMemOffset(); 1460 X86AddressMode AM; 1461 AM.Base.Reg = StackPtr; 1462 AM.Disp = LocMemOffset; 1463 const Value *ArgVal = ArgVals[VA.getValNo()]; 1464 1465 // If this is a really simple value, emit this with the Value* version of 1466 // X86FastEmitStore. If it isn't simple, we don't want to do this, as it 1467 // can cause us to reevaluate the argument. 1468 if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) 1469 X86FastEmitStore(ArgVT, ArgVal, AM); 1470 else 1471 X86FastEmitStore(ArgVT, Arg, AM); 1472 } 1473 } 1474 1475 // ELF / PIC requires GOT in the EBX register before function calls via PLT 1476 // GOT pointer. 1477 if (Subtarget->isPICStyleGOT()) { 1478 TargetRegisterClass *RC = X86::GR32RegisterClass; 1479 unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF); 1480 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC, 1481 DL); 1482 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1483 Emitted = true; 1484 } 1485 1486 // Issue the call. 1487 MachineInstrBuilder MIB; 1488 if (CalleeOp) { 1489 // Register-indirect call. 1490 unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r; 1491 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp); 1492 1493 } else { 1494 // Direct call. 1495 assert(GV && "Not a direct call"); 1496 unsigned CallOpc = 1497 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32; 1498 1499 // See if we need any target-specific flags on the GV operand. 1500 unsigned char OpFlags = 0; 1501 1502 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 1503 // external symbols most go through the PLT in PIC mode. If the symbol 1504 // has hidden or protected visibility, or if it is static or local, then 1505 // we don't need to use the PLT - we can directly call it. 1506 if (Subtarget->isTargetELF() && 1507 TM.getRelocationModel() == Reloc::PIC_ && 1508 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 1509 OpFlags = X86II::MO_PLT; 1510 } else if (Subtarget->isPICStyleStubAny() && 1511 (GV->isDeclaration() || GV->isWeakForLinker()) && 1512 Subtarget->getDarwinVers() < 9) { 1513 // PC-relative references to external symbols should go through $stub, 1514 // unless we're building with the leopard linker or later, which 1515 // automatically synthesizes these stubs. 1516 OpFlags = X86II::MO_DARWIN_STUB; 1517 } 1518 1519 1520 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags); 1521 } 1522 1523 // Add an implicit use GOT pointer in EBX. 1524 if (Subtarget->isPICStyleGOT()) 1525 MIB.addReg(X86::EBX); 1526 1527 // Add implicit physical register uses to the call. 1528 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 1529 MIB.addReg(RegArgs[i]); 1530 1531 // Issue CALLSEQ_END 1532 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode(); 1533 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0); 1534 1535 // Now handle call return value (if any). 1536 if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) { 1537 SmallVector<CCValAssign, 16> RVLocs; 1538 CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); 1539 CCInfo.AnalyzeCallResult(RetVT, RetCC_X86); 1540 1541 // Copy all of the result registers out of their specified physreg. 1542 assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); 1543 EVT CopyVT = RVLocs[0].getValVT(); 1544 TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); 1545 TargetRegisterClass *SrcRC = DstRC; 1546 1547 // If this is a call to a function that returns an fp value on the x87 fp 1548 // stack, but where we prefer to use the value in xmm registers, copy it 1549 // out as F80 and use a truncate to move it from fp stack reg to xmm reg. 1550 if ((RVLocs[0].getLocReg() == X86::ST0 || 1551 RVLocs[0].getLocReg() == X86::ST1) && 1552 isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { 1553 CopyVT = MVT::f80; 1554 SrcRC = X86::RSTRegisterClass; 1555 DstRC = X86::RFP80RegisterClass; 1556 } 1557 1558 unsigned ResultReg = createResultReg(DstRC); 1559 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 1560 RVLocs[0].getLocReg(), DstRC, SrcRC, DL); 1561 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 1562 Emitted = true; 1563 if (CopyVT != RVLocs[0].getValVT()) { 1564 // Round the F80 the right size, which also moves to the appropriate xmm 1565 // register. This is accomplished by storing the F80 value in memory and 1566 // then loading it back. Ewww... 1567 EVT ResVT = RVLocs[0].getValVT(); 1568 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; 1569 unsigned MemSize = ResVT.getSizeInBits()/8; 1570 int FI = MFI.CreateStackObject(MemSize, MemSize, false); 1571 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg); 1572 DstRC = ResVT == MVT::f32 1573 ? X86::FR32RegisterClass : X86::FR64RegisterClass; 1574 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; 1575 ResultReg = createResultReg(DstRC); 1576 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI); 1577 } 1578 1579 if (AndToI1) { 1580 // Mask out all but lowest bit for some call which produces an i1. 1581 unsigned AndResult = createResultReg(X86::GR8RegisterClass); 1582 BuildMI(MBB, DL, 1583 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1); 1584 ResultReg = AndResult; 1585 } 1586 1587 UpdateValueMap(I, ResultReg); 1588 } 1589 1590 return true; 1591} 1592 1593 1594bool 1595X86FastISel::TargetSelectInstruction(const Instruction *I) { 1596 switch (I->getOpcode()) { 1597 default: break; 1598 case Instruction::Load: 1599 return X86SelectLoad(I); 1600 case Instruction::Store: 1601 return X86SelectStore(I); 1602 case Instruction::ICmp: 1603 case Instruction::FCmp: 1604 return X86SelectCmp(I); 1605 case Instruction::ZExt: 1606 return X86SelectZExt(I); 1607 case Instruction::Br: 1608 return X86SelectBranch(I); 1609 case Instruction::Call: 1610 return X86SelectCall(I); 1611 case Instruction::LShr: 1612 case Instruction::AShr: 1613 case Instruction::Shl: 1614 return X86SelectShift(I); 1615 case Instruction::Select: 1616 return X86SelectSelect(I); 1617 case Instruction::Trunc: 1618 return X86SelectTrunc(I); 1619 case Instruction::FPExt: 1620 return X86SelectFPExt(I); 1621 case Instruction::FPTrunc: 1622 return X86SelectFPTrunc(I); 1623 case Instruction::ExtractValue: 1624 return X86SelectExtractValue(I); 1625 case Instruction::IntToPtr: // Deliberate fall-through. 1626 case Instruction::PtrToInt: { 1627 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 1628 EVT DstVT = TLI.getValueType(I->getType()); 1629 if (DstVT.bitsGT(SrcVT)) 1630 return X86SelectZExt(I); 1631 if (DstVT.bitsLT(SrcVT)) 1632 return X86SelectTrunc(I); 1633 unsigned Reg = getRegForValue(I->getOperand(0)); 1634 if (Reg == 0) return false; 1635 UpdateValueMap(I, Reg); 1636 return true; 1637 } 1638 } 1639 1640 return false; 1641} 1642 1643unsigned X86FastISel::TargetMaterializeConstant(const Constant *C) { 1644 EVT VT; 1645 if (!isTypeLegal(C->getType(), VT)) 1646 return false; 1647 1648 // Get opcode and regclass of the output for the given load instruction. 1649 unsigned Opc = 0; 1650 const TargetRegisterClass *RC = NULL; 1651 switch (VT.getSimpleVT().SimpleTy) { 1652 default: return false; 1653 case MVT::i8: 1654 Opc = X86::MOV8rm; 1655 RC = X86::GR8RegisterClass; 1656 break; 1657 case MVT::i16: 1658 Opc = X86::MOV16rm; 1659 RC = X86::GR16RegisterClass; 1660 break; 1661 case MVT::i32: 1662 Opc = X86::MOV32rm; 1663 RC = X86::GR32RegisterClass; 1664 break; 1665 case MVT::i64: 1666 // Must be in x86-64 mode. 1667 Opc = X86::MOV64rm; 1668 RC = X86::GR64RegisterClass; 1669 break; 1670 case MVT::f32: 1671 if (Subtarget->hasSSE1()) { 1672 Opc = X86::MOVSSrm; 1673 RC = X86::FR32RegisterClass; 1674 } else { 1675 Opc = X86::LD_Fp32m; 1676 RC = X86::RFP32RegisterClass; 1677 } 1678 break; 1679 case MVT::f64: 1680 if (Subtarget->hasSSE2()) { 1681 Opc = X86::MOVSDrm; 1682 RC = X86::FR64RegisterClass; 1683 } else { 1684 Opc = X86::LD_Fp64m; 1685 RC = X86::RFP64RegisterClass; 1686 } 1687 break; 1688 case MVT::f80: 1689 // No f80 support yet. 1690 return false; 1691 } 1692 1693 // Materialize addresses with LEA instructions. 1694 if (isa<GlobalValue>(C)) { 1695 X86AddressMode AM; 1696 if (X86SelectAddress(C, AM)) { 1697 if (TLI.getPointerTy() == MVT::i32) 1698 Opc = X86::LEA32r; 1699 else 1700 Opc = X86::LEA64r; 1701 unsigned ResultReg = createResultReg(RC); 1702 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 1703 return ResultReg; 1704 } 1705 return 0; 1706 } 1707 1708 // MachineConstantPool wants an explicit alignment. 1709 unsigned Align = TD.getPrefTypeAlignment(C->getType()); 1710 if (Align == 0) { 1711 // Alignment of vector types. FIXME! 1712 Align = TD.getTypeAllocSize(C->getType()); 1713 } 1714 1715 // x86-32 PIC requires a PIC base register for constant pools. 1716 unsigned PICBase = 0; 1717 unsigned char OpFlag = 0; 1718 if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic 1719 OpFlag = X86II::MO_PIC_BASE_OFFSET; 1720 PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 1721 } else if (Subtarget->isPICStyleGOT()) { 1722 OpFlag = X86II::MO_GOTOFF; 1723 PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 1724 } else if (Subtarget->isPICStyleRIPRel() && 1725 TM.getCodeModel() == CodeModel::Small) { 1726 PICBase = X86::RIP; 1727 } 1728 1729 // Create the load from the constant pool. 1730 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align); 1731 unsigned ResultReg = createResultReg(RC); 1732 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), 1733 MCPOffset, PICBase, OpFlag); 1734 1735 return ResultReg; 1736} 1737 1738unsigned X86FastISel::TargetMaterializeAlloca(const AllocaInst *C) { 1739 // Fail on dynamic allocas. At this point, getRegForValue has already 1740 // checked its CSE maps, so if we're here trying to handle a dynamic 1741 // alloca, we're not going to succeed. X86SelectAddress has a 1742 // check for dynamic allocas, because it's called directly from 1743 // various places, but TargetMaterializeAlloca also needs a check 1744 // in order to avoid recursion between getRegForValue, 1745 // X86SelectAddrss, and TargetMaterializeAlloca. 1746 if (!StaticAllocaMap.count(C)) 1747 return 0; 1748 1749 X86AddressMode AM; 1750 if (!X86SelectAddress(C, AM)) 1751 return 0; 1752 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 1753 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); 1754 unsigned ResultReg = createResultReg(RC); 1755 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 1756 return ResultReg; 1757} 1758 1759namespace llvm { 1760 llvm::FastISel *X86::createFastISel(MachineFunction &mf, 1761 DenseMap<const Value *, unsigned> &vm, 1762 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 1763 DenseMap<const AllocaInst *, int> &am, 1764 std::vector<std::pair<MachineInstr*, unsigned> > &pn 1765#ifndef NDEBUG 1766 , SmallSet<const Instruction *, 8> &cil 1767#endif 1768 ) { 1769 return new X86FastISel(mf, vm, bm, am, pn 1770#ifndef NDEBUG 1771 , cil 1772#endif 1773 ); 1774 } 1775} 1776