X86FastISel.cpp revision 206274
156893Sfenner//===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===// 298524Sfenner// 398524Sfenner// The LLVM Compiler Infrastructure 498524Sfenner// 598524Sfenner// This file is distributed under the University of Illinois Open Source 698524Sfenner// License. See LICENSE.TXT for details. 798524Sfenner// 8127668Sbms//===----------------------------------------------------------------------===// 998524Sfenner// 1098524Sfenner// This file defines the X86-specific support for the FastISel class. Much 1198524Sfenner// of the target-specific code is generated by tablegen in the file 1298524Sfenner// X86GenFastISel.inc, which is #included here. 1398524Sfenner// 1498524Sfenner//===----------------------------------------------------------------------===// 1598524Sfenner 1698524Sfenner#include "X86.h" 1798524Sfenner#include "X86InstrBuilder.h" 18127668Sbms#include "X86ISelLowering.h" 1998524Sfenner#include "X86RegisterInfo.h" 2098524Sfenner#include "X86Subtarget.h" 2198524Sfenner#include "X86TargetMachine.h" 2298524Sfenner#include "llvm/CallingConv.h" 2398524Sfenner#include "llvm/DerivedTypes.h" 2456893Sfenner#include "llvm/GlobalVariable.h" 2556893Sfenner#include "llvm/Instructions.h" 2656893Sfenner#include "llvm/IntrinsicInst.h" 2756893Sfenner#include "llvm/CodeGen/FastISel.h" 2856893Sfenner#include "llvm/CodeGen/MachineConstantPool.h" 2956893Sfenner#include "llvm/CodeGen/MachineFrameInfo.h" 3056893Sfenner#include "llvm/CodeGen/MachineRegisterInfo.h" 3156893Sfenner#include "llvm/Support/CallSite.h" 3256893Sfenner#include "llvm/Support/ErrorHandling.h" 3356893Sfenner#include "llvm/Support/GetElementPtrTypeIterator.h" 3456893Sfenner#include "llvm/Target/TargetOptions.h" 3556893Sfennerusing namespace llvm; 36127668Sbms 37214478Srpaulonamespace { 3856893Sfenner 3956893Sfennerclass X86FastISel : public FastISel { 4056893Sfenner /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 4156893Sfenner /// make the right decision when generating code for different targets. 4256893Sfenner const X86Subtarget *Subtarget; 4356893Sfenner 4456893Sfenner /// StackPtr - Register used as the stack pointer. 4575115Sfenner /// 4656893Sfenner unsigned StackPtr; 47127668Sbms 4856893Sfenner /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 4956893Sfenner /// floating point ops. 5056893Sfenner /// When SSE is available, use it for f32 operations. 5175115Sfenner /// When SSE2 is available, use it for f64 operations. 5256893Sfenner bool X86ScalarSSEf64; 5356893Sfenner bool X86ScalarSSEf32; 5456893Sfenner 5575115Sfennerpublic: 5675115Sfenner explicit X86FastISel(MachineFunction &mf, 5756893Sfenner DenseMap<const Value *, unsigned> &vm, 5856893Sfenner DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 5956893Sfenner DenseMap<const AllocaInst *, int> &am 6056893Sfenner#ifndef NDEBUG 6156893Sfenner , SmallSet<Instruction*, 8> &cil 6256893Sfenner#endif 6356893Sfenner ) 6456893Sfenner : FastISel(mf, vm, bm, am 6556893Sfenner#ifndef NDEBUG 6656893Sfenner , cil 6756893Sfenner#endif 6856893Sfenner ) { 6956893Sfenner Subtarget = &TM.getSubtarget<X86Subtarget>(); 7056893Sfenner StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 7198524Sfenner X86ScalarSSEf64 = Subtarget->hasSSE2(); 7298524Sfenner X86ScalarSSEf32 = Subtarget->hasSSE1(); 7398524Sfenner } 74127668Sbms 7598524Sfenner virtual bool TargetSelectInstruction(Instruction *I); 7698524Sfenner 7798524Sfenner#include "X86GenFastISel.inc" 7898524Sfenner 7998524Sfennerprivate: 8098524Sfenner bool X86FastEmitCompare(Value *LHS, Value *RHS, EVT VT); 8198524Sfenner 8298524Sfenner bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR); 8356893Sfenner 8456893Sfenner bool X86FastEmitStore(EVT VT, Value *Val, 8556893Sfenner const X86AddressMode &AM); 8656893Sfenner bool X86FastEmitStore(EVT VT, unsigned Val, 8756893Sfenner const X86AddressMode &AM); 8856893Sfenner 8956893Sfenner bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 9056893Sfenner unsigned &ResultReg); 9156893Sfenner 9256893Sfenner bool X86SelectAddress(Value *V, X86AddressMode &AM); 9356893Sfenner bool X86SelectCallAddress(Value *V, X86AddressMode &AM); 9456893Sfenner 9556893Sfenner bool X86SelectLoad(Instruction *I); 9656893Sfenner 9756893Sfenner bool X86SelectStore(Instruction *I); 9856893Sfenner 9956893Sfenner bool X86SelectCmp(Instruction *I); 10056893Sfenner 10156893Sfenner bool X86SelectZExt(Instruction *I); 10256893Sfenner 10356893Sfenner bool X86SelectBranch(Instruction *I); 10456893Sfenner 10556893Sfenner bool X86SelectShift(Instruction *I); 10656893Sfenner 10756893Sfenner bool X86SelectSelect(Instruction *I); 10856893Sfenner 10956893Sfenner bool X86SelectTrunc(Instruction *I); 11056893Sfenner 11156893Sfenner bool X86SelectFPExt(Instruction *I); 11256893Sfenner bool X86SelectFPTrunc(Instruction *I); 11356893Sfenner 11456893Sfenner bool X86SelectExtractValue(Instruction *I); 11556893Sfenner 11656893Sfenner bool X86VisitIntrinsicCall(IntrinsicInst &I); 11756893Sfenner bool X86SelectCall(Instruction *I); 11856893Sfenner 11956893Sfenner CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false); 12098524Sfenner 121190207Srpaulo const X86InstrInfo *getInstrInfo() const { 122190207Srpaulo return getTargetMachine()->getInstrInfo(); 123190207Srpaulo } 124190207Srpaulo const X86TargetMachine *getTargetMachine() const { 125190207Srpaulo return static_cast<const X86TargetMachine *>(&TM); 126190207Srpaulo } 12756893Sfenner 12856893Sfenner unsigned TargetMaterializeConstant(Constant *C); 12956893Sfenner 13056893Sfenner unsigned TargetMaterializeAlloca(AllocaInst *C); 13156893Sfenner 13256893Sfenner /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is 13356893Sfenner /// computed in an SSE register, not on the X87 floating point stack. 13456893Sfenner bool isScalarFPTypeInSSEReg(EVT VT) const { 13556893Sfenner return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 13656893Sfenner (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 13756893Sfenner } 13856893Sfenner 13956893Sfenner bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false); 14056893Sfenner}; 14156893Sfenner 14298524Sfenner} // end anonymous namespace. 14398524Sfenner 14498524Sfennerbool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) { 14598524Sfenner VT = TLI.getValueType(Ty, /*HandleUnknown=*/true); 146190207Srpaulo if (VT == MVT::Other || !VT.isSimple()) 147190207Srpaulo // Unhandled type. Halt "fast" selection and bail. 148190207Srpaulo return false; 14956893Sfenner 15056893Sfenner // For now, require SSE/SSE2 for performing floating-point operations, 15156893Sfenner // since x87 requires additional work. 15256893Sfenner if (VT == MVT::f64 && !X86ScalarSSEf64) 15356893Sfenner return false; 15456893Sfenner if (VT == MVT::f32 && !X86ScalarSSEf32) 15556893Sfenner return false; 15656893Sfenner // Similarly, no f80 support yet. 15756893Sfenner if (VT == MVT::f80) 15856893Sfenner return false; 15956893Sfenner // We only handle legal types. For example, on x86-32 the instruction 16056893Sfenner // selector contains all of the 64-bit instructions from x86-64, 16156893Sfenner // under the assumption that i64 won't be used if the target doesn't 16256893Sfenner // support it. 16356893Sfenner return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT); 16456893Sfenner} 16556893Sfenner 16656893Sfenner#include "X86GenCallingConv.inc" 16756893Sfenner 16856893Sfenner/// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling 16956893Sfenner/// convention. 17056893SfennerCCAssignFn *X86FastISel::CCAssignFnForCall(CallingConv::ID CC, 17156893Sfenner bool isTaillCall) { 17256893Sfenner if (Subtarget->is64Bit()) { 17356893Sfenner if (CC == CallingConv::GHC) 17498524Sfenner return CC_X86_64_GHC; 175190207Srpaulo else if (Subtarget->isTargetWin64()) 17656893Sfenner return CC_X86_Win64_C; 17756893Sfenner else 17856893Sfenner return CC_X86_64_C; 17956893Sfenner } 18056893Sfenner 18156893Sfenner if (CC == CallingConv::X86_FastCall) 18256893Sfenner return CC_X86_32_FastCall; 18356893Sfenner else if (CC == CallingConv::Fast) 18456893Sfenner return CC_X86_32_FastCC; 18556893Sfenner else if (CC == CallingConv::GHC) 18656893Sfenner return CC_X86_32_GHC; 18756893Sfenner else 18856893Sfenner return CC_X86_32_C; 18956893Sfenner} 19056893Sfenner 19156893Sfenner/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT. 19256893Sfenner/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV. 19356893Sfenner/// Return true and the result register by reference if it is possible. 19456893Sfennerbool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, 19556893Sfenner unsigned &ResultReg) { 19656893Sfenner // Get opcode and regclass of the output for the given load instruction. 19756893Sfenner unsigned Opc = 0; 19856893Sfenner const TargetRegisterClass *RC = NULL; 19956893Sfenner switch (VT.getSimpleVT().SimpleTy) { 20056893Sfenner default: return false; 20156893Sfenner case MVT::i1: 20256893Sfenner case MVT::i8: 20356893Sfenner Opc = X86::MOV8rm; 20456893Sfenner RC = X86::GR8RegisterClass; 20556893Sfenner break; 20656893Sfenner case MVT::i16: 20756893Sfenner Opc = X86::MOV16rm; 20856893Sfenner RC = X86::GR16RegisterClass; 20956893Sfenner break; 21056893Sfenner case MVT::i32: 21156893Sfenner Opc = X86::MOV32rm; 21256893Sfenner RC = X86::GR32RegisterClass; 21398524Sfenner break; 21456893Sfenner case MVT::i64: 21556893Sfenner // Must be in x86-64 mode. 21656893Sfenner Opc = X86::MOV64rm; 21756893Sfenner RC = X86::GR64RegisterClass; 21856893Sfenner break; 21956893Sfenner case MVT::f32: 22056893Sfenner if (Subtarget->hasSSE1()) { 22156893Sfenner Opc = X86::MOVSSrm; 22256893Sfenner RC = X86::FR32RegisterClass; 22356893Sfenner } else { 22456893Sfenner Opc = X86::LD_Fp32m; 22556893Sfenner RC = X86::RFP32RegisterClass; 22656893Sfenner } 22756893Sfenner break; 22856893Sfenner case MVT::f64: 22956893Sfenner if (Subtarget->hasSSE2()) { 23056893Sfenner Opc = X86::MOVSDrm; 23156893Sfenner RC = X86::FR64RegisterClass; 23256893Sfenner } else { 23356893Sfenner Opc = X86::LD_Fp64m; 23456893Sfenner RC = X86::RFP64RegisterClass; 23556893Sfenner } 23656893Sfenner break; 23756893Sfenner case MVT::f80: 23856893Sfenner // No f80 support yet. 23956893Sfenner return false; 24056893Sfenner } 24156893Sfenner 24256893Sfenner ResultReg = createResultReg(RC); 24356893Sfenner addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 24456893Sfenner return true; 24556893Sfenner} 24656893Sfenner 24756893Sfenner/// X86FastEmitStore - Emit a machine instruction to store a value Val of 24856893Sfenner/// type VT. The address is either pre-computed, consisted of a base ptr, Ptr 24956893Sfenner/// and a displacement offset, or a GlobalAddress, 25056893Sfenner/// i.e. V. Return true if it is possible. 25156893Sfennerbool 25256893SfennerX86FastISel::X86FastEmitStore(EVT VT, unsigned Val, 25356893Sfenner const X86AddressMode &AM) { 25456893Sfenner // Get opcode and regclass of the output for the given store instruction. 25556893Sfenner unsigned Opc = 0; 25656893Sfenner switch (VT.getSimpleVT().SimpleTy) { 25756893Sfenner case MVT::f80: // No f80 support yet. 25856893Sfenner default: return false; 25956893Sfenner case MVT::i1: { 26056893Sfenner // Mask out all but lowest bit. 26156893Sfenner unsigned AndResult = createResultReg(X86::GR8RegisterClass); 26256893Sfenner BuildMI(MBB, DL, 26356893Sfenner TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1); 26456893Sfenner Val = AndResult; 26556893Sfenner } 26656893Sfenner // FALLTHROUGH, handling i1 as i8. 26756893Sfenner case MVT::i8: Opc = X86::MOV8mr; break; 26856893Sfenner case MVT::i16: Opc = X86::MOV16mr; break; 269190207Srpaulo case MVT::i32: Opc = X86::MOV32mr; break; 270190207Srpaulo case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode. 271190207Srpaulo case MVT::f32: 27256893Sfenner Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m; 27356893Sfenner break; 27456893Sfenner case MVT::f64: 27556893Sfenner Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m; 27656893Sfenner break; 27756893Sfenner } 27856893Sfenner 27956893Sfenner addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val); 28056893Sfenner return true; 28156893Sfenner} 28256893Sfenner 28356893Sfennerbool X86FastISel::X86FastEmitStore(EVT VT, Value *Val, 28456893Sfenner const X86AddressMode &AM) { 28556893Sfenner // Handle 'null' like i32/i64 0. 28656893Sfenner if (isa<ConstantPointerNull>(Val)) 28756893Sfenner Val = Constant::getNullValue(TD.getIntPtrType(Val->getContext())); 28856893Sfenner 28956893Sfenner // If this is a store of a simple constant, fold the constant into the store. 29056893Sfenner if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) { 29156893Sfenner unsigned Opc = 0; 29256893Sfenner bool Signed = true; 29356893Sfenner switch (VT.getSimpleVT().SimpleTy) { 29456893Sfenner default: break; 29556893Sfenner case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8. 29656893Sfenner case MVT::i8: Opc = X86::MOV8mi; break; 29756893Sfenner case MVT::i16: Opc = X86::MOV16mi; break; 29856893Sfenner case MVT::i32: Opc = X86::MOV32mi; break; 29956893Sfenner case MVT::i64: 30056893Sfenner // Must be a 32-bit sign extended value. 30156893Sfenner if ((int)CI->getSExtValue() == CI->getSExtValue()) 30256893Sfenner Opc = X86::MOV64mi32; 30356893Sfenner break; 30456893Sfenner } 30556893Sfenner 30656893Sfenner if (Opc) { 30756893Sfenner addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM) 30856893Sfenner .addImm(Signed ? CI->getSExtValue() : 30956893Sfenner CI->getZExtValue()); 31056893Sfenner return true; 31198524Sfenner } 31298524Sfenner } 31356893Sfenner 31456893Sfenner unsigned ValReg = getRegForValue(Val); 31556893Sfenner if (ValReg == 0) 31656893Sfenner return false; 31756893Sfenner 31856893Sfenner return X86FastEmitStore(VT, ValReg, AM); 31956893Sfenner} 32056893Sfenner 32156893Sfenner/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of 32256893Sfenner/// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. 323190207Srpaulo/// ISD::SIGN_EXTEND). 324190207Srpaulobool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, 32556893Sfenner unsigned Src, EVT SrcVT, 32656893Sfenner unsigned &ResultReg) { 32756893Sfenner unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); 32856893Sfenner 32956893Sfenner if (RR != 0) { 33056893Sfenner ResultReg = RR; 33156893Sfenner return true; 33256893Sfenner } else 33356893Sfenner return false; 33456893Sfenner} 33556893Sfenner 33656893Sfenner/// X86SelectAddress - Attempt to fill in an address from the given value. 33756893Sfenner/// 33856893Sfennerbool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) { 33956893Sfenner User *U = NULL; 34056893Sfenner unsigned Opcode = Instruction::UserOp1; 34156893Sfenner if (Instruction *I = dyn_cast<Instruction>(V)) { 34256893Sfenner Opcode = I->getOpcode(); 343190207Srpaulo U = I; 34456893Sfenner } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 34556893Sfenner Opcode = C->getOpcode(); 34656893Sfenner U = C; 34756893Sfenner } 34856893Sfenner 34956893Sfenner switch (Opcode) { 35056893Sfenner default: break; 35156893Sfenner case Instruction::BitCast: 35256893Sfenner // Look past bitcasts. 35356893Sfenner return X86SelectAddress(U->getOperand(0), AM); 35456893Sfenner 35556893Sfenner case Instruction::IntToPtr: 35656893Sfenner // Look past no-op inttoptrs. 35756893Sfenner if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 35856893Sfenner return X86SelectAddress(U->getOperand(0), AM); 35956893Sfenner break; 36056893Sfenner 361127668Sbms case Instruction::PtrToInt: 36256893Sfenner // Look past no-op ptrtoints. 36375115Sfenner if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 36475115Sfenner return X86SelectAddress(U->getOperand(0), AM); 36575115Sfenner break; 36675115Sfenner 36775115Sfenner case Instruction::Alloca: { 36875115Sfenner // Do static allocas. 36975115Sfenner const AllocaInst *A = cast<AllocaInst>(V); 37075115Sfenner DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A); 37175115Sfenner if (SI != StaticAllocaMap.end()) { 37275115Sfenner AM.BaseType = X86AddressMode::FrameIndexBase; 37375115Sfenner AM.Base.FrameIndex = SI->second; 37475115Sfenner return true; 37575115Sfenner } 37675115Sfenner break; 37775115Sfenner } 37875115Sfenner 37975115Sfenner case Instruction::Add: { 38056893Sfenner // Adds of constants are common and easy enough. 38175115Sfenner if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) { 38275115Sfenner uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue(); 38375115Sfenner // They have to fit in the 32-bit signed displacement field though. 38475115Sfenner if (isInt<32>(Disp)) { 38575115Sfenner AM.Disp = (uint32_t)Disp; 38675115Sfenner return X86SelectAddress(U->getOperand(0), AM); 38775115Sfenner } 38875115Sfenner } 38975115Sfenner break; 39075115Sfenner } 39175115Sfenner 39275115Sfenner case Instruction::GetElementPtr: { 393127668Sbms X86AddressMode SavedAM = AM; 39475115Sfenner 39575115Sfenner // Pattern-match simple GEPs. 39675115Sfenner uint64_t Disp = (int32_t)AM.Disp; 39775115Sfenner unsigned IndexReg = AM.IndexReg; 39856893Sfenner unsigned Scale = AM.Scale; 39956893Sfenner gep_type_iterator GTI = gep_type_begin(U); 40056893Sfenner // Iterate through the indices, folding what we can. Constants can be 40156893Sfenner // folded, and one dynamic index can be handled, if the scale is supported. 40256893Sfenner for (User::op_iterator i = U->op_begin() + 1, e = U->op_end(); 40356893Sfenner i != e; ++i, ++GTI) { 40456893Sfenner Value *Op = *i; 40556893Sfenner if (const StructType *STy = dyn_cast<StructType>(*GTI)) { 40656893Sfenner const StructLayout *SL = TD.getStructLayout(STy); 40756893Sfenner unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 40856893Sfenner Disp += SL->getElementOffset(Idx); 40956893Sfenner } else { 41056893Sfenner uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); 41156893Sfenner if (ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 41256893Sfenner // Constant-offset addressing. 41356893Sfenner Disp += CI->getSExtValue() * S; 41456893Sfenner } else if (IndexReg == 0 && 41556893Sfenner (!AM.GV || !Subtarget->isPICStyleRIPRel()) && 41656893Sfenner (S == 1 || S == 2 || S == 4 || S == 8)) { 417127668Sbms // Scaled-index addressing. 41856893Sfenner Scale = S; 41956893Sfenner IndexReg = getRegForGEPIndex(Op); 42056893Sfenner if (IndexReg == 0) 42156893Sfenner return false; 42256893Sfenner } else 42375115Sfenner // Unsupported. 42456893Sfenner goto unsupported_gep; 42556893Sfenner } 42656893Sfenner } 42756893Sfenner // Check for displacement overflow. 42856893Sfenner if (!isInt<32>(Disp)) 42956893Sfenner break; 43056893Sfenner // Ok, the GEP indices were covered by constant-offset and scaled-index 43156893Sfenner // addressing. Update the address state and move on to examining the base. 43256893Sfenner AM.IndexReg = IndexReg; 43356893Sfenner AM.Scale = Scale; 43456893Sfenner AM.Disp = (uint32_t)Disp; 43556893Sfenner if (X86SelectAddress(U->getOperand(0), AM)) 436127668Sbms return true; 43756893Sfenner 43856893Sfenner // If we couldn't merge the sub value into this addr mode, revert back to 43975115Sfenner // our address and just match the value instead of completely failing. 44075115Sfenner AM = SavedAM; 44156893Sfenner break; 44256893Sfenner unsupported_gep: 44356893Sfenner // Ok, the GEP indices weren't all covered. 44456893Sfenner break; 44556893Sfenner } 44656893Sfenner } 44756893Sfenner 44856893Sfenner // Handle constant address. 44956893Sfenner if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 45056893Sfenner // Can't handle alternate code models yet. 45156893Sfenner if (TM.getCodeModel() != CodeModel::Small) 45256893Sfenner return false; 45356893Sfenner 45456893Sfenner // RIP-relative addresses can't have additional register operands. 45556893Sfenner if (Subtarget->isPICStyleRIPRel() && 456127668Sbms (AM.Base.Reg != 0 || AM.IndexReg != 0)) 45756893Sfenner return false; 45856893Sfenner 45956893Sfenner // Can't handle TLS yet. 46056893Sfenner if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 46156893Sfenner if (GVar->isThreadLocal()) 46256893Sfenner return false; 46356893Sfenner 46456893Sfenner // Okay, we've committed to selecting this global. Set up the basic address. 46575115Sfenner AM.GV = GV; 46656893Sfenner 46775115Sfenner // Allow the subtarget to classify the global. 46875115Sfenner unsigned char GVFlags = Subtarget->ClassifyGlobalReference(GV, TM); 46975115Sfenner 47075115Sfenner // If this reference is relative to the pic base, set it now. 47175115Sfenner if (isGlobalRelativeToPICBase(GVFlags)) { 47275115Sfenner // FIXME: How do we know Base.Reg is free?? 47375115Sfenner AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF); 47475115Sfenner } 47575115Sfenner 47675115Sfenner // Unless the ABI requires an extra load, return a direct reference to 47756893Sfenner // the global. 47856893Sfenner if (!isGlobalStubReference(GVFlags)) { 47956893Sfenner if (Subtarget->isPICStyleRIPRel()) { 48075115Sfenner // Use rip-relative addressing if we can. Above we verified that the 48175115Sfenner // base and index registers are unused. 48275115Sfenner assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 48375115Sfenner AM.Base.Reg = X86::RIP; 48498524Sfenner } 48598524Sfenner AM.GVOpFlags = GVFlags; 48698524Sfenner return true; 48775115Sfenner } 48875115Sfenner 48975115Sfenner // Ok, we need to do a load from a stub. If we've already loaded from this 49075115Sfenner // stub, reuse the loaded pointer, otherwise emit the load now. 49175115Sfenner DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V); 49275115Sfenner unsigned LoadReg; 49375115Sfenner if (I != LocalValueMap.end() && I->second != 0) { 49456893Sfenner LoadReg = I->second; 49556893Sfenner } else { 49656893Sfenner // Issue load from stub. 49756893Sfenner unsigned Opc = 0; 49856893Sfenner const TargetRegisterClass *RC = NULL; 49956893Sfenner X86AddressMode StubAM; 50056893Sfenner StubAM.Base.Reg = AM.Base.Reg; 50156893Sfenner StubAM.GV = GV; 50256893Sfenner StubAM.GVOpFlags = GVFlags; 50356893Sfenner 50456893Sfenner if (TLI.getPointerTy() == MVT::i64) { 50556893Sfenner Opc = X86::MOV64rm; 50656893Sfenner RC = X86::GR64RegisterClass; 507127668Sbms 50875115Sfenner if (Subtarget->isPICStyleRIPRel()) 50956893Sfenner StubAM.Base.Reg = X86::RIP; 51056893Sfenner } else { 51156893Sfenner Opc = X86::MOV32rm; 51256893Sfenner RC = X86::GR32RegisterClass; 51356893Sfenner } 51456893Sfenner 51556893Sfenner LoadReg = createResultReg(RC); 516127668Sbms addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM); 51756893Sfenner 51856893Sfenner // Prevent loading GV stub multiple times in same MBB. 51956893Sfenner LocalValueMap[V] = LoadReg; 52056893Sfenner } 52156893Sfenner 52256893Sfenner // Now construct the final address. Note that the Disp, Scale, 52356893Sfenner // and Index values may already be set here. 52456893Sfenner AM.Base.Reg = LoadReg; 52556893Sfenner AM.GV = 0; 52656893Sfenner return true; 52756893Sfenner } 52856893Sfenner 52956893Sfenner // If all else fails, try to materialize the value in a register. 53056893Sfenner if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 53156893Sfenner if (AM.Base.Reg == 0) { 53256893Sfenner AM.Base.Reg = getRegForValue(V); 53356893Sfenner return AM.Base.Reg != 0; 53456893Sfenner } 53556893Sfenner if (AM.IndexReg == 0) { 53656893Sfenner assert(AM.Scale == 1 && "Scale with no index!"); 53756893Sfenner AM.IndexReg = getRegForValue(V); 53856893Sfenner return AM.IndexReg != 0; 53956893Sfenner } 54056893Sfenner } 54156893Sfenner 54256893Sfenner return false; 543127668Sbms} 54456893Sfenner 54556893Sfenner/// X86SelectCallAddress - Attempt to fill in an address from the given value. 54656893Sfenner/// 54756893Sfennerbool X86FastISel::X86SelectCallAddress(Value *V, X86AddressMode &AM) { 54856893Sfenner User *U = NULL; 54956893Sfenner unsigned Opcode = Instruction::UserOp1; 55056893Sfenner if (Instruction *I = dyn_cast<Instruction>(V)) { 55156893Sfenner Opcode = I->getOpcode(); 55275115Sfenner U = I; 55356893Sfenner } else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { 55456893Sfenner Opcode = C->getOpcode(); 55556893Sfenner U = C; 55656893Sfenner } 55756893Sfenner 55856893Sfenner switch (Opcode) { 55956893Sfenner default: break; 56056893Sfenner case Instruction::BitCast: 56156893Sfenner // Look past bitcasts. 56256893Sfenner return X86SelectCallAddress(U->getOperand(0), AM); 56356893Sfenner 56456893Sfenner case Instruction::IntToPtr: 56556893Sfenner // Look past no-op inttoptrs. 56656893Sfenner if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 56756893Sfenner return X86SelectCallAddress(U->getOperand(0), AM); 56856893Sfenner break; 56956893Sfenner 57056893Sfenner case Instruction::PtrToInt: 57156893Sfenner // Look past no-op ptrtoints. 57256893Sfenner if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 57356893Sfenner return X86SelectCallAddress(U->getOperand(0), AM); 57456893Sfenner break; 57556893Sfenner } 57656893Sfenner 57756893Sfenner // Handle constant address. 57856893Sfenner if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) { 57956893Sfenner // Can't handle alternate code models yet. 58056893Sfenner if (TM.getCodeModel() != CodeModel::Small) 58156893Sfenner return false; 58256893Sfenner 58356893Sfenner // RIP-relative addresses can't have additional register operands. 58475115Sfenner if (Subtarget->isPICStyleRIPRel() && 58575115Sfenner (AM.Base.Reg != 0 || AM.IndexReg != 0)) 58675115Sfenner return false; 58775115Sfenner 58875115Sfenner // Can't handle TLS or DLLImport. 58956893Sfenner if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) 59075115Sfenner if (GVar->isThreadLocal() || GVar->hasDLLImportLinkage()) 59175115Sfenner return false; 59275115Sfenner 59375115Sfenner // Okay, we've committed to selecting this global. Set up the basic address. 59456893Sfenner AM.GV = GV; 59556893Sfenner 59656893Sfenner // No ABI requires an extra load for anything other than DLLImport, which 59756893Sfenner // we rejected above. Return a direct reference to the global. 59856893Sfenner if (Subtarget->isPICStyleRIPRel()) { 59956893Sfenner // Use rip-relative addressing if we can. Above we verified that the 60056893Sfenner // base and index registers are unused. 60156893Sfenner assert(AM.Base.Reg == 0 && AM.IndexReg == 0); 602127668Sbms AM.Base.Reg = X86::RIP; 60356893Sfenner } else if (Subtarget->isPICStyleStubPIC()) { 60456893Sfenner AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET; 60556893Sfenner } else if (Subtarget->isPICStyleGOT()) { 60656893Sfenner AM.GVOpFlags = X86II::MO_GOTOFF; 607127668Sbms } 60856893Sfenner 60956893Sfenner return true; 61056893Sfenner } 61156893Sfenner 61256893Sfenner // If all else fails, try to materialize the value in a register. 61356893Sfenner if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { 614127668Sbms if (AM.Base.Reg == 0) { 61556893Sfenner AM.Base.Reg = getRegForValue(V); 61656893Sfenner return AM.Base.Reg != 0; 61756893Sfenner } 61856893Sfenner if (AM.IndexReg == 0) { 61956893Sfenner assert(AM.Scale == 1 && "Scale with no index!"); 62075115Sfenner AM.IndexReg = getRegForValue(V); 62156893Sfenner return AM.IndexReg != 0; 62256893Sfenner } 62356893Sfenner } 62456893Sfenner 62556893Sfenner return false; 62656893Sfenner} 62756893Sfenner 62856893Sfenner 62956893Sfenner/// X86SelectStore - Select and emit code to implement store instructions. 63056893Sfennerbool X86FastISel::X86SelectStore(Instruction* I) { 63156893Sfenner EVT VT; 63256893Sfenner if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true)) 63356893Sfenner return false; 63456893Sfenner 63556893Sfenner X86AddressMode AM; 63656893Sfenner if (!X86SelectAddress(I->getOperand(1), AM)) 63756893Sfenner return false; 63856893Sfenner 63956893Sfenner return X86FastEmitStore(VT, I->getOperand(0), AM); 64056893Sfenner} 64156893Sfenner 64256893Sfenner/// X86SelectLoad - Select and emit code to implement load instructions. 64356893Sfenner/// 64456893Sfennerbool X86FastISel::X86SelectLoad(Instruction *I) { 64556893Sfenner EVT VT; 646127668Sbms if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true)) 64756893Sfenner return false; 64856893Sfenner 64956893Sfenner X86AddressMode AM; 65056893Sfenner if (!X86SelectAddress(I->getOperand(0), AM)) 65156893Sfenner return false; 65256893Sfenner 65356893Sfenner unsigned ResultReg = 0; 65456893Sfenner if (X86FastEmitLoad(VT, AM, ResultReg)) { 65556893Sfenner UpdateValueMap(I, ResultReg); 65656893Sfenner return true; 65756893Sfenner } 65856893Sfenner return false; 65956893Sfenner} 66056893Sfenner 66156893Sfennerstatic unsigned X86ChooseCmpOpcode(EVT VT) { 66256893Sfenner switch (VT.getSimpleVT().SimpleTy) { 66356893Sfenner default: return 0; 66456893Sfenner case MVT::i8: return X86::CMP8rr; 66556893Sfenner case MVT::i16: return X86::CMP16rr; 66656893Sfenner case MVT::i32: return X86::CMP32rr; 66756893Sfenner case MVT::i64: return X86::CMP64rr; 66856893Sfenner case MVT::f32: return X86::UCOMISSrr; 66975115Sfenner case MVT::f64: return X86::UCOMISDrr; 67075115Sfenner } 67156893Sfenner} 67275115Sfenner 67356893Sfenner/// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS 67475115Sfenner/// of the comparison, return an opcode that works for the compare (e.g. 67556893Sfenner/// CMP32ri) otherwise return 0. 67656893Sfennerstatic unsigned X86ChooseCmpImmediateOpcode(EVT VT, ConstantInt *RHSC) { 67756893Sfenner switch (VT.getSimpleVT().SimpleTy) { 67856893Sfenner // Otherwise, we can't fold the immediate into this comparison. 67980231Sfenner default: return 0; 68075115Sfenner case MVT::i8: return X86::CMP8ri; 68180231Sfenner case MVT::i16: return X86::CMP16ri; 68298524Sfenner case MVT::i32: return X86::CMP32ri; 68380231Sfenner case MVT::i64: 68456893Sfenner // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext 68580231Sfenner // field. 68680231Sfenner if ((int)RHSC->getSExtValue() == RHSC->getSExtValue()) 68780231Sfenner return X86::CMP64ri32; 68880231Sfenner return 0; 68956893Sfenner } 69056893Sfenner} 69156893Sfenner 69256893Sfennerbool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, EVT VT) { 69375115Sfenner unsigned Op0Reg = getRegForValue(Op0); 69475115Sfenner if (Op0Reg == 0) return false; 69556893Sfenner 69656893Sfenner // Handle 'null' like i32/i64 0. 69756893Sfenner if (isa<ConstantPointerNull>(Op1)) 69856893Sfenner Op1 = Constant::getNullValue(TD.getIntPtrType(Op0->getContext())); 69956893Sfenner 70075115Sfenner // We have two options: compare with register or immediate. If the RHS of 70175115Sfenner // the compare is an immediate that we can fold into this compare, use 70256893Sfenner // CMPri, otherwise use CMPrr. 70356893Sfenner if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) { 70456893Sfenner if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) { 70556893Sfenner BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg) 706190207Srpaulo .addImm(Op1C->getSExtValue()); 707190207Srpaulo return true; 708190207Srpaulo } 709190207Srpaulo } 710190207Srpaulo 711190207Srpaulo unsigned CompareOpc = X86ChooseCmpOpcode(VT); 712190207Srpaulo if (CompareOpc == 0) return false; 71356893Sfenner 71475115Sfenner unsigned Op1Reg = getRegForValue(Op1); 71575115Sfenner if (Op1Reg == 0) return false; 71656893Sfenner BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg); 71756893Sfenner 71856893Sfenner return true; 71956893Sfenner} 72056893Sfenner 72156893Sfennerbool X86FastISel::X86SelectCmp(Instruction *I) { 72256893Sfenner CmpInst *CI = cast<CmpInst>(I); 72375115Sfenner 72475115Sfenner EVT VT; 72556893Sfenner if (!isTypeLegal(I->getOperand(0)->getType(), VT)) 726127668Sbms return false; 72756893Sfenner 72875115Sfenner unsigned ResultReg = createResultReg(&X86::GR8RegClass); 729127668Sbms unsigned SetCCOpc; 73075115Sfenner bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 731127668Sbms switch (CI->getPredicate()) { 73275115Sfenner case CmpInst::FCMP_OEQ: { 733127668Sbms if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 73475115Sfenner return false; 735127668Sbms 73656893Sfenner unsigned EReg = createResultReg(&X86::GR8RegClass); 737127668Sbms unsigned NPReg = createResultReg(&X86::GR8RegClass); 73856893Sfenner BuildMI(MBB, DL, TII.get(X86::SETEr), EReg); 73956893Sfenner BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg); 74056893Sfenner BuildMI(MBB, DL, 74175115Sfenner TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg); 74275115Sfenner UpdateValueMap(I, ResultReg); 74356893Sfenner return true; 74475115Sfenner } 74556893Sfenner case CmpInst::FCMP_UNE: { 74656893Sfenner if (!X86FastEmitCompare(CI->getOperand(0), CI->getOperand(1), VT)) 74756893Sfenner return false; 74856893Sfenner 74956893Sfenner unsigned NEReg = createResultReg(&X86::GR8RegClass); 75075115Sfenner unsigned PReg = createResultReg(&X86::GR8RegClass); 75175115Sfenner BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg); 75256893Sfenner BuildMI(MBB, DL, TII.get(X86::SETPr), PReg); 75356893Sfenner BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg); 75475115Sfenner UpdateValueMap(I, ResultReg); 75556893Sfenner return true; 75656893Sfenner } 75775115Sfenner case CmpInst::FCMP_OGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 75856893Sfenner case CmpInst::FCMP_OGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 75956893Sfenner case CmpInst::FCMP_OLT: SwapArgs = true; SetCCOpc = X86::SETAr; break; 76056893Sfenner case CmpInst::FCMP_OLE: SwapArgs = true; SetCCOpc = X86::SETAEr; break; 76175115Sfenner case CmpInst::FCMP_ONE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 76256893Sfenner case CmpInst::FCMP_ORD: SwapArgs = false; SetCCOpc = X86::SETNPr; break; 76356893Sfenner case CmpInst::FCMP_UNO: SwapArgs = false; SetCCOpc = X86::SETPr; break; 76456893Sfenner case CmpInst::FCMP_UEQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 76556893Sfenner case CmpInst::FCMP_UGT: SwapArgs = true; SetCCOpc = X86::SETBr; break; 76656893Sfenner case CmpInst::FCMP_UGE: SwapArgs = true; SetCCOpc = X86::SETBEr; break; 76756893Sfenner case CmpInst::FCMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 76856893Sfenner case CmpInst::FCMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 76956893Sfenner 77056893Sfenner case CmpInst::ICMP_EQ: SwapArgs = false; SetCCOpc = X86::SETEr; break; 771111726Sfenner case CmpInst::ICMP_NE: SwapArgs = false; SetCCOpc = X86::SETNEr; break; 772111726Sfenner case CmpInst::ICMP_UGT: SwapArgs = false; SetCCOpc = X86::SETAr; break; 77356893Sfenner case CmpInst::ICMP_UGE: SwapArgs = false; SetCCOpc = X86::SETAEr; break; 77498524Sfenner case CmpInst::ICMP_ULT: SwapArgs = false; SetCCOpc = X86::SETBr; break; 77598524Sfenner case CmpInst::ICMP_ULE: SwapArgs = false; SetCCOpc = X86::SETBEr; break; 77698524Sfenner case CmpInst::ICMP_SGT: SwapArgs = false; SetCCOpc = X86::SETGr; break; 77756893Sfenner case CmpInst::ICMP_SGE: SwapArgs = false; SetCCOpc = X86::SETGEr; break; 77898524Sfenner case CmpInst::ICMP_SLT: SwapArgs = false; SetCCOpc = X86::SETLr; break; 779111726Sfenner case CmpInst::ICMP_SLE: SwapArgs = false; SetCCOpc = X86::SETLEr; break; 78056893Sfenner default: 78156893Sfenner return false; 78298524Sfenner } 78380231Sfenner 78480231Sfenner Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 78580231Sfenner if (SwapArgs) 78656893Sfenner std::swap(Op0, Op1); 78756893Sfenner 788190207Srpaulo // Emit a compare of Op0/Op1. 789190207Srpaulo if (!X86FastEmitCompare(Op0, Op1, VT)) 790190207Srpaulo return false; 791190207Srpaulo 792190207Srpaulo BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg); 793190207Srpaulo UpdateValueMap(I, ResultReg); 794190207Srpaulo return true; 795190207Srpaulo} 796190207Srpaulo 797190207Srpaulobool X86FastISel::X86SelectZExt(Instruction *I) { 798190207Srpaulo // Handle zero-extension from i1 to i8, which is common. 79956893Sfenner if (I->getType()->isIntegerTy(8) && 80056893Sfenner I->getOperand(0)->getType()->isIntegerTy(1)) { 80156893Sfenner unsigned ResultReg = getRegForValue(I->getOperand(0)); 80256893Sfenner if (ResultReg == 0) return false; 80375115Sfenner // Set the high bits to zero. 80456893Sfenner ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg); 80556893Sfenner if (ResultReg == 0) return false; 80656893Sfenner UpdateValueMap(I, ResultReg); 80756893Sfenner return true; 80856893Sfenner } 809127668Sbms 81056893Sfenner return false; 81156893Sfenner} 812127668Sbms 81356893Sfenner 81456893Sfennerbool X86FastISel::X86SelectBranch(Instruction *I) { 81556893Sfenner // Unconditional branches are selected by tablegen-generated code. 81656893Sfenner // Handle a conditional branch. 81756893Sfenner BranchInst *BI = cast<BranchInst>(I); 81856893Sfenner MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)]; 81956893Sfenner MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)]; 82056893Sfenner 82175115Sfenner // Fold the common case of a conditional branch with a comparison. 82256893Sfenner if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 82356893Sfenner if (CI->hasOneUse()) { 82456893Sfenner EVT VT = TLI.getValueType(CI->getOperand(0)->getType()); 82556893Sfenner 82656893Sfenner // Try to take advantage of fallthrough opportunities. 82756893Sfenner CmpInst::Predicate Predicate = CI->getPredicate(); 82856893Sfenner if (MBB->isLayoutSuccessor(TrueMBB)) { 82956893Sfenner std::swap(TrueMBB, FalseMBB); 83056893Sfenner Predicate = CmpInst::getInversePredicate(Predicate); 83156893Sfenner } 83256893Sfenner 83356893Sfenner bool SwapArgs; // false -> compare Op0, Op1. true -> compare Op1, Op0. 83456893Sfenner unsigned BranchOpc; // Opcode to jump on, e.g. "X86::JA" 83556893Sfenner 83656893Sfenner switch (Predicate) { 83756893Sfenner case CmpInst::FCMP_OEQ: 83856893Sfenner std::swap(TrueMBB, FalseMBB); 83956893Sfenner Predicate = CmpInst::FCMP_UNE; 84056893Sfenner // FALL THROUGH 84156893Sfenner case CmpInst::FCMP_UNE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 84256893Sfenner case CmpInst::FCMP_OGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 84356893Sfenner case CmpInst::FCMP_OGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 84456893Sfenner case CmpInst::FCMP_OLT: SwapArgs = true; BranchOpc = X86::JA_4; break; 84556893Sfenner case CmpInst::FCMP_OLE: SwapArgs = true; BranchOpc = X86::JAE_4; break; 84656893Sfenner case CmpInst::FCMP_ONE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 84756893Sfenner case CmpInst::FCMP_ORD: SwapArgs = false; BranchOpc = X86::JNP_4; break; 84856893Sfenner case CmpInst::FCMP_UNO: SwapArgs = false; BranchOpc = X86::JP_4; break; 84956893Sfenner case CmpInst::FCMP_UEQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 85056893Sfenner case CmpInst::FCMP_UGT: SwapArgs = true; BranchOpc = X86::JB_4; break; 85156893Sfenner case CmpInst::FCMP_UGE: SwapArgs = true; BranchOpc = X86::JBE_4; break; 85256893Sfenner case CmpInst::FCMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 85356893Sfenner case CmpInst::FCMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 85456893Sfenner 85556893Sfenner case CmpInst::ICMP_EQ: SwapArgs = false; BranchOpc = X86::JE_4; break; 85656893Sfenner case CmpInst::ICMP_NE: SwapArgs = false; BranchOpc = X86::JNE_4; break; 85756893Sfenner case CmpInst::ICMP_UGT: SwapArgs = false; BranchOpc = X86::JA_4; break; 85856893Sfenner case CmpInst::ICMP_UGE: SwapArgs = false; BranchOpc = X86::JAE_4; break; 85956893Sfenner case CmpInst::ICMP_ULT: SwapArgs = false; BranchOpc = X86::JB_4; break; 86056893Sfenner case CmpInst::ICMP_ULE: SwapArgs = false; BranchOpc = X86::JBE_4; break; 86156893Sfenner case CmpInst::ICMP_SGT: SwapArgs = false; BranchOpc = X86::JG_4; break; 86256893Sfenner case CmpInst::ICMP_SGE: SwapArgs = false; BranchOpc = X86::JGE_4; break; 86356893Sfenner case CmpInst::ICMP_SLT: SwapArgs = false; BranchOpc = X86::JL_4; break; 86456893Sfenner case CmpInst::ICMP_SLE: SwapArgs = false; BranchOpc = X86::JLE_4; break; 86556893Sfenner default: 86656893Sfenner return false; 86756893Sfenner } 86856893Sfenner 86956893Sfenner Value *Op0 = CI->getOperand(0), *Op1 = CI->getOperand(1); 87075115Sfenner if (SwapArgs) 87156893Sfenner std::swap(Op0, Op1); 87275115Sfenner 87375115Sfenner // Emit a compare of the LHS and RHS, setting the flags. 87456893Sfenner if (!X86FastEmitCompare(Op0, Op1, VT)) 87575115Sfenner return false; 87675115Sfenner 87775115Sfenner BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB); 87856893Sfenner 87975115Sfenner if (Predicate == CmpInst::FCMP_UNE) { 88056893Sfenner // X86 requires a second branch to handle UNE (and OEQ, 88156893Sfenner // which is mapped to UNE above). 88256893Sfenner BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB); 88356893Sfenner } 88456893Sfenner 88556893Sfenner FastEmitBranch(FalseMBB); 88656893Sfenner MBB->addSuccessor(TrueMBB); 88756893Sfenner return true; 88856893Sfenner } 88956893Sfenner } else if (ExtractValueInst *EI = 89056893Sfenner dyn_cast<ExtractValueInst>(BI->getCondition())) { 89156893Sfenner // Check to see if the branch instruction is from an "arithmetic with 89256893Sfenner // overflow" intrinsic. The main way these intrinsics are used is: 89356893Sfenner // 89456893Sfenner // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) 89556893Sfenner // %sum = extractvalue { i32, i1 } %t, 0 89656893Sfenner // %obit = extractvalue { i32, i1 } %t, 1 89756893Sfenner // br i1 %obit, label %overflow, label %normal 89856893Sfenner // 89956893Sfenner // The %sum and %obit are converted in an ADD and a SETO/SETB before 90056893Sfenner // reaching the branch. Therefore, we search backwards through the MBB 90156893Sfenner // looking for the SETO/SETB instruction. If an instruction modifies the 90256893Sfenner // EFLAGS register before we reach the SETO/SETB instruction, then we can't 90356893Sfenner // convert the branch into a JO/JB instruction. 90456893Sfenner if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(EI->getAggregateOperand())){ 90556893Sfenner if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow || 90656893Sfenner CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) { 90756893Sfenner const MachineInstr *SetMI = 0; 90856893Sfenner unsigned Reg = lookUpRegForValue(EI); 90956893Sfenner 91056893Sfenner for (MachineBasicBlock::const_reverse_iterator 91156893Sfenner RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) { 91256893Sfenner const MachineInstr &MI = *RI; 91356893Sfenner 91456893Sfenner if (MI.modifiesRegister(Reg)) { 91556893Sfenner unsigned Src, Dst, SrcSR, DstSR; 91656893Sfenner 91756893Sfenner if (getInstrInfo()->isMoveInstr(MI, Src, Dst, SrcSR, DstSR)) { 91856893Sfenner Reg = Src; 91956893Sfenner continue; 92056893Sfenner } 92156893Sfenner 92256893Sfenner SetMI = &MI; 92356893Sfenner break; 92456893Sfenner } 92556893Sfenner 926190207Srpaulo const TargetInstrDesc &TID = MI.getDesc(); 92756893Sfenner if (TID.hasUnmodeledSideEffects() || 92856893Sfenner TID.hasImplicitDefOfPhysReg(X86::EFLAGS)) 92975115Sfenner break; 93075115Sfenner } 93156893Sfenner 93256893Sfenner if (SetMI) { 93356893Sfenner unsigned OpCode = SetMI->getOpcode(); 93456893Sfenner 93556893Sfenner if (OpCode == X86::SETOr || OpCode == X86::SETBr) { 93656893Sfenner BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ? 93756893Sfenner X86::JO_4 : X86::JB_4)) 93856893Sfenner .addMBB(TrueMBB); 93956893Sfenner FastEmitBranch(FalseMBB); 94056893Sfenner MBB->addSuccessor(TrueMBB); 941190207Srpaulo return true; 942190207Srpaulo } 943190207Srpaulo } 944190207Srpaulo } 945190207Srpaulo } 946190207Srpaulo } 947190207Srpaulo 948190207Srpaulo // Otherwise do a clumsy setcc and re-test it. 949190207Srpaulo unsigned OpReg = getRegForValue(BI->getCondition()); 950190207Srpaulo if (OpReg == 0) return false; 951190207Srpaulo 952190207Srpaulo BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg); 953190207Srpaulo BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB); 954190207Srpaulo FastEmitBranch(FalseMBB); 955190207Srpaulo MBB->addSuccessor(TrueMBB); 956190207Srpaulo return true; 957190207Srpaulo} 958190207Srpaulo 959190207Srpaulobool X86FastISel::X86SelectShift(Instruction *I) { 960190207Srpaulo unsigned CReg = 0, OpReg = 0, OpImm = 0; 96156893Sfenner const TargetRegisterClass *RC = NULL; 96256893Sfenner if (I->getType()->isIntegerTy(8)) { 96356893Sfenner CReg = X86::CL; 96456893Sfenner RC = &X86::GR8RegClass; 96556893Sfenner switch (I->getOpcode()) { 96656893Sfenner case Instruction::LShr: OpReg = X86::SHR8rCL; OpImm = X86::SHR8ri; break; 96756893Sfenner case Instruction::AShr: OpReg = X86::SAR8rCL; OpImm = X86::SAR8ri; break; 96856893Sfenner case Instruction::Shl: OpReg = X86::SHL8rCL; OpImm = X86::SHL8ri; break; 96956893Sfenner default: return false; 97056893Sfenner } 97156893Sfenner } else if (I->getType()->isIntegerTy(16)) { 97256893Sfenner CReg = X86::CX; 97356893Sfenner RC = &X86::GR16RegClass; 97456893Sfenner switch (I->getOpcode()) { 97556893Sfenner case Instruction::LShr: OpReg = X86::SHR16rCL; OpImm = X86::SHR16ri; break; 97656893Sfenner case Instruction::AShr: OpReg = X86::SAR16rCL; OpImm = X86::SAR16ri; break; 97756893Sfenner case Instruction::Shl: OpReg = X86::SHL16rCL; OpImm = X86::SHL16ri; break; 97856893Sfenner default: return false; 97956893Sfenner } 98056893Sfenner } else if (I->getType()->isIntegerTy(32)) { 981127668Sbms CReg = X86::ECX; 98256893Sfenner RC = &X86::GR32RegClass; 98356893Sfenner switch (I->getOpcode()) { 98456893Sfenner case Instruction::LShr: OpReg = X86::SHR32rCL; OpImm = X86::SHR32ri; break; 98556893Sfenner case Instruction::AShr: OpReg = X86::SAR32rCL; OpImm = X86::SAR32ri; break; 98656893Sfenner case Instruction::Shl: OpReg = X86::SHL32rCL; OpImm = X86::SHL32ri; break; 98756893Sfenner default: return false; 98856893Sfenner } 98956893Sfenner } else if (I->getType()->isIntegerTy(64)) { 99056893Sfenner CReg = X86::RCX; 99156893Sfenner RC = &X86::GR64RegClass; 99256893Sfenner switch (I->getOpcode()) { 99356893Sfenner case Instruction::LShr: OpReg = X86::SHR64rCL; OpImm = X86::SHR64ri; break; 99456893Sfenner case Instruction::AShr: OpReg = X86::SAR64rCL; OpImm = X86::SAR64ri; break; 99556893Sfenner case Instruction::Shl: OpReg = X86::SHL64rCL; OpImm = X86::SHL64ri; break; 99656893Sfenner default: return false; 99756893Sfenner } 99856893Sfenner } else { 99975115Sfenner return false; 100056893Sfenner } 100156893Sfenner 100256893Sfenner EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 100375115Sfenner if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 100475115Sfenner return false; 100575115Sfenner 100656893Sfenner unsigned Op0Reg = getRegForValue(I->getOperand(0)); 100775115Sfenner if (Op0Reg == 0) return false; 100875115Sfenner 100975115Sfenner // Fold immediate in shl(x,3). 101056893Sfenner if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { 101175115Sfenner unsigned ResultReg = createResultReg(RC); 101256893Sfenner BuildMI(MBB, DL, TII.get(OpImm), 101356893Sfenner ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff); 101456893Sfenner UpdateValueMap(I, ResultReg); 101556893Sfenner return true; 101656893Sfenner } 101756893Sfenner 101856893Sfenner unsigned Op1Reg = getRegForValue(I->getOperand(1)); 101956893Sfenner if (Op1Reg == 0) return false; 102056893Sfenner TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC); 102156893Sfenner 102256893Sfenner // The shift instruction uses X86::CL. If we defined a super-register 102356893Sfenner // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what 102456893Sfenner // we're doing here. 102556893Sfenner if (CReg != X86::CL) 102656893Sfenner BuildMI(MBB, DL, TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL) 102756893Sfenner .addReg(CReg).addImm(X86::SUBREG_8BIT); 102856893Sfenner 102975115Sfenner unsigned ResultReg = createResultReg(RC); 103075115Sfenner BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg); 103175115Sfenner UpdateValueMap(I, ResultReg); 1032127668Sbms return true; 1033127668Sbms} 1034127668Sbms 1035127668Sbmsbool X86FastISel::X86SelectSelect(Instruction *I) { 1036127668Sbms EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); 1037127668Sbms if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) 103875115Sfenner return false; 103975115Sfenner 104075115Sfenner unsigned Opc = 0; 104175115Sfenner const TargetRegisterClass *RC = NULL; 104256893Sfenner if (VT.getSimpleVT() == MVT::i16) { 104356893Sfenner Opc = X86::CMOVE16rr; 104456893Sfenner RC = &X86::GR16RegClass; 104556893Sfenner } else if (VT.getSimpleVT() == MVT::i32) { 104656893Sfenner Opc = X86::CMOVE32rr; 104756893Sfenner RC = &X86::GR32RegClass; 104856893Sfenner } else if (VT.getSimpleVT() == MVT::i64) { 104956893Sfenner Opc = X86::CMOVE64rr; 105056893Sfenner RC = &X86::GR64RegClass; 105156893Sfenner } else { 105256893Sfenner return false; 105356893Sfenner } 105456893Sfenner 105556893Sfenner unsigned Op0Reg = getRegForValue(I->getOperand(0)); 105656893Sfenner if (Op0Reg == 0) return false; 1057127668Sbms unsigned Op1Reg = getRegForValue(I->getOperand(1)); 105856893Sfenner if (Op1Reg == 0) return false; 105956893Sfenner unsigned Op2Reg = getRegForValue(I->getOperand(2)); 106056893Sfenner if (Op2Reg == 0) return false; 106156893Sfenner 106256893Sfenner BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg); 106356893Sfenner unsigned ResultReg = createResultReg(RC); 106456893Sfenner BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg); 106575115Sfenner UpdateValueMap(I, ResultReg); 106656893Sfenner return true; 106756893Sfenner} 106856893Sfenner 106975115Sfennerbool X86FastISel::X86SelectFPExt(Instruction *I) { 1070172683Smlaier // fpext from float to double. 107156893Sfenner if (Subtarget->hasSSE2() && 107275115Sfenner I->getType()->isDoubleTy()) { 107375115Sfenner Value *V = I->getOperand(0); 107475115Sfenner if (V->getType()->isFloatTy()) { 107556893Sfenner unsigned OpReg = getRegForValue(V); 107675115Sfenner if (OpReg == 0) return false; 1077127668Sbms unsigned ResultReg = createResultReg(X86::FR64RegisterClass); 107856893Sfenner BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg); 107956893Sfenner UpdateValueMap(I, ResultReg); 108056893Sfenner return true; 108175115Sfenner } 108256893Sfenner } 108356893Sfenner 108456893Sfenner return false; 108556893Sfenner} 108656893Sfenner 108756893Sfennerbool X86FastISel::X86SelectFPTrunc(Instruction *I) { 108856893Sfenner if (Subtarget->hasSSE2()) { 108956893Sfenner if (I->getType()->isFloatTy()) { 109056893Sfenner Value *V = I->getOperand(0); 109156893Sfenner if (V->getType()->isDoubleTy()) { 109256893Sfenner unsigned OpReg = getRegForValue(V); 109356893Sfenner if (OpReg == 0) return false; 109456893Sfenner unsigned ResultReg = createResultReg(X86::FR32RegisterClass); 109556893Sfenner BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg); 109656893Sfenner UpdateValueMap(I, ResultReg); 109756893Sfenner return true; 109856893Sfenner } 109956893Sfenner } 110056893Sfenner } 110156893Sfenner 110256893Sfenner return false; 110356893Sfenner} 1104172683Smlaier 1105172683Smlaierbool X86FastISel::X86SelectTrunc(Instruction *I) { 110675115Sfenner if (Subtarget->is64Bit()) 110756893Sfenner // All other cases should be handled by the tblgen generated code. 110880231Sfenner return false; 1109111726Sfenner EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 111080231Sfenner EVT DstVT = TLI.getValueType(I->getType()); 111156893Sfenner 111256893Sfenner // This code only handles truncation to byte right now. 111356893Sfenner if (DstVT != MVT::i8 && DstVT != MVT::i1) 111475115Sfenner // All other cases should be handled by the tblgen generated code. 111556893Sfenner return false; 111656893Sfenner if (SrcVT != MVT::i16 && SrcVT != MVT::i32) 111756893Sfenner // All other cases should be handled by the tblgen generated code. 1118172683Smlaier return false; 1119172683Smlaier 112075115Sfenner unsigned InputReg = getRegForValue(I->getOperand(0)); 112156893Sfenner if (!InputReg) 112280231Sfenner // Unhandled operand. Halt "fast" selection and bail. 1123111726Sfenner return false; 112480231Sfenner 112556893Sfenner // First issue a copy to GR16_ABCD or GR32_ABCD. 112656893Sfenner unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr; 112756893Sfenner const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) 112875115Sfenner ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass; 112956893Sfenner unsigned CopyReg = createResultReg(CopyRC); 113075115Sfenner BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg); 113175115Sfenner 113275115Sfenner // Then issue an extract_subreg. 113375115Sfenner unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, 113456893Sfenner CopyReg, X86::SUBREG_8BIT); 113556893Sfenner if (!ResultReg) 113656893Sfenner return false; 113756893Sfenner 113856893Sfenner UpdateValueMap(I, ResultReg); 113956893Sfenner return true; 114056893Sfenner} 114156893Sfenner 114256893Sfennerbool X86FastISel::X86SelectExtractValue(Instruction *I) { 114356893Sfenner ExtractValueInst *EI = cast<ExtractValueInst>(I); 114456893Sfenner Value *Agg = EI->getAggregateOperand(); 114556893Sfenner 114656893Sfenner if (IntrinsicInst *CI = dyn_cast<IntrinsicInst>(Agg)) { 114756893Sfenner switch (CI->getIntrinsicID()) { 1148127668Sbms default: break; 114956893Sfenner case Intrinsic::sadd_with_overflow: 115056893Sfenner case Intrinsic::uadd_with_overflow: 1151127668Sbms // Cheat a little. We know that the registers for "add" and "seto" are 115256893Sfenner // allocated sequentially. However, we only keep track of the register 115356893Sfenner // for "add" in the value map. Use extractvalue's index to get the 115456893Sfenner // correct register for "seto". 115556893Sfenner UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin()); 115656893Sfenner return true; 115756893Sfenner } 115856893Sfenner } 115956893Sfenner 116075115Sfenner return false; 116156893Sfenner} 116256893Sfenner 116356893Sfennerbool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) { 116456893Sfenner // FIXME: Handle more intrinsics. 116556893Sfenner switch (I.getIntrinsicID()) { 116656893Sfenner default: return false; 116756893Sfenner case Intrinsic::stackprotector: { 116856893Sfenner // Emit code inline code to store the stack guard onto the stack. 116956893Sfenner EVT PtrTy = TLI.getPointerTy(); 117056893Sfenner 117156893Sfenner Value *Op1 = I.getOperand(1); // The guard's value. 117256893Sfenner AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2)); 117356893Sfenner 117456893Sfenner // Grab the frame index. 117575115Sfenner X86AddressMode AM; 117675115Sfenner if (!X86SelectAddress(Slot, AM)) return false; 117756893Sfenner 117856893Sfenner if (!X86FastEmitStore(PtrTy, Op1, AM)) return false; 117956893Sfenner 118056893Sfenner return true; 118156893Sfenner } 118256893Sfenner case Intrinsic::objectsize: { 118356893Sfenner ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(2)); 118456893Sfenner const Type *Ty = I.getCalledFunction()->getReturnType(); 118556893Sfenner 118656893Sfenner assert(CI && "Non-constant type in Intrinsic::objectsize?"); 118756893Sfenner 118875115Sfenner EVT VT; 118956893Sfenner if (!isTypeLegal(Ty, VT)) 119056893Sfenner return false; 119156893Sfenner 119256893Sfenner unsigned OpC = 0; 119356893Sfenner if (VT == MVT::i32) 119456893Sfenner OpC = X86::MOV32ri; 119556893Sfenner else if (VT == MVT::i64) 119656893Sfenner OpC = X86::MOV64ri; 119756893Sfenner else 119856893Sfenner return false; 119975115Sfenner 120075115Sfenner unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 120156893Sfenner BuildMI(MBB, DL, TII.get(OpC), ResultReg). 120256893Sfenner addImm(CI->getZExtValue() == 0 ? -1ULL : 0); 120356893Sfenner UpdateValueMap(&I, ResultReg); 120456893Sfenner return true; 120556893Sfenner } 120656893Sfenner case Intrinsic::dbg_declare: { 120756893Sfenner DbgDeclareInst *DI = cast<DbgDeclareInst>(&I); 120856893Sfenner X86AddressMode AM; 120956893Sfenner assert(DI->getAddress() && "Null address should be checked earlier!"); 121056893Sfenner if (!X86SelectAddress(DI->getAddress(), AM)) 121156893Sfenner return false; 121256893Sfenner const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); 121356893Sfenner // FIXME may need to add RegState::Debug to any registers produced, 121456893Sfenner // although ESP/EBP should be the only ones at the moment. 121556893Sfenner addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0). 121656893Sfenner addMetadata(DI->getVariable()); 121756893Sfenner return true; 121856893Sfenner } 121956893Sfenner case Intrinsic::trap: { 122056893Sfenner BuildMI(MBB, DL, TII.get(X86::TRAP)); 122156893Sfenner return true; 122256893Sfenner } 122356893Sfenner case Intrinsic::sadd_with_overflow: 122456893Sfenner case Intrinsic::uadd_with_overflow: { 122556893Sfenner // Replace "add with overflow" intrinsics with an "add" instruction followed 122656893Sfenner // by a seto/setc instruction. Later on, when the "extractvalue" 122756893Sfenner // instructions are encountered, we use the fact that two registers were 122856893Sfenner // created sequentially to get the correct registers for the "sum" and the 1229127668Sbms // "overflow bit". 123056893Sfenner const Function *Callee = I.getCalledFunction(); 123156893Sfenner const Type *RetTy = 123256893Sfenner cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0)); 123356893Sfenner 123456893Sfenner EVT VT; 123556893Sfenner if (!isTypeLegal(RetTy, VT)) 123656893Sfenner return false; 123756893Sfenner 1238127668Sbms Value *Op1 = I.getOperand(1); 123956893Sfenner Value *Op2 = I.getOperand(2); 124056893Sfenner unsigned Reg1 = getRegForValue(Op1); 124156893Sfenner unsigned Reg2 = getRegForValue(Op2); 124256893Sfenner 124356893Sfenner if (Reg1 == 0 || Reg2 == 0) 124456893Sfenner // FIXME: Handle values *not* in registers. 124556893Sfenner return false; 124656893Sfenner 124756893Sfenner unsigned OpC = 0; 124856893Sfenner if (VT == MVT::i32) 124956893Sfenner OpC = X86::ADD32rr; 125056893Sfenner else if (VT == MVT::i64) 125156893Sfenner OpC = X86::ADD64rr; 125256893Sfenner else 125356893Sfenner return false; 125456893Sfenner 125556893Sfenner unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); 125656893Sfenner BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2); 125756893Sfenner unsigned DestReg1 = UpdateValueMap(&I, ResultReg); 125856893Sfenner 125956893Sfenner // If the add with overflow is an intra-block value then we just want to 126056893Sfenner // create temporaries for it like normal. If it is a cross-block value then 126156893Sfenner // UpdateValueMap will return the cross-block register used. Since we 126256893Sfenner // *really* want the value to be live in the register pair known by 126356893Sfenner // UpdateValueMap, we have to use DestReg1+1 as the destination register in 126456893Sfenner // the cross block case. In the non-cross-block case, we should just make 126556893Sfenner // another register for the value. 126656893Sfenner if (DestReg1 != ResultReg) 126756893Sfenner ResultReg = DestReg1+1; 126856893Sfenner else 126956893Sfenner ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8)); 127056893Sfenner 127156893Sfenner unsigned Opc = X86::SETBr; 127256893Sfenner if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow) 127356893Sfenner Opc = X86::SETOr; 127456893Sfenner BuildMI(MBB, DL, TII.get(Opc), ResultReg); 127556893Sfenner return true; 127656893Sfenner } 127756893Sfenner } 127856893Sfenner} 1279127668Sbms 128056893Sfennerbool X86FastISel::X86SelectCall(Instruction *I) { 128156893Sfenner CallInst *CI = cast<CallInst>(I); 1282127668Sbms Value *Callee = I->getOperand(0); 128356893Sfenner 128456893Sfenner // Can't handle inline asm yet. 128556893Sfenner if (isa<InlineAsm>(Callee)) 128656893Sfenner return false; 128756893Sfenner 128856893Sfenner // Handle intrinsic calls. 128956893Sfenner if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI)) 129056893Sfenner return X86VisitIntrinsicCall(*II); 129175115Sfenner 129256893Sfenner // Handle only C and fastcc calling conventions for now. 129356893Sfenner CallSite CS(CI); 129456893Sfenner CallingConv::ID CC = CS.getCallingConv(); 129556893Sfenner if (CC != CallingConv::C && 1296127668Sbms CC != CallingConv::Fast && 129756893Sfenner CC != CallingConv::X86_FastCall) 129856893Sfenner return false; 129956893Sfenner 130056893Sfenner // fastcc with -tailcallopt is intended to provide a guaranteed 130156893Sfenner // tail call optimization. Fastisel doesn't know how to do that. 130256893Sfenner if (CC == CallingConv::Fast && GuaranteedTailCallOpt) 130356893Sfenner return false; 130456893Sfenner 130556893Sfenner // Let SDISel handle vararg functions. 130656893Sfenner const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 130756893Sfenner const FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 130856893Sfenner if (FTy->isVarArg()) 130956893Sfenner return false; 131056893Sfenner 131156893Sfenner // Handle *simple* calls for now. 131256893Sfenner const Type *RetTy = CS.getType(); 131356893Sfenner EVT RetVT; 131456893Sfenner if (RetTy->isVoidTy()) 131556893Sfenner RetVT = MVT::isVoid; 131656893Sfenner else if (!isTypeLegal(RetTy, RetVT, true)) 131756893Sfenner return false; 131856893Sfenner 131956893Sfenner // Materialize callee address in a register. FIXME: GV address can be 132056893Sfenner // handled with a CALLpcrel32 instead. 132156893Sfenner X86AddressMode CalleeAM; 132256893Sfenner if (!X86SelectCallAddress(Callee, CalleeAM)) 132356893Sfenner return false; 1324190207Srpaulo unsigned CalleeOp = 0; 132556893Sfenner GlobalValue *GV = 0; 132656893Sfenner if (CalleeAM.GV != 0) { 132756893Sfenner GV = CalleeAM.GV; 132856893Sfenner } else if (CalleeAM.Base.Reg != 0) { 132956893Sfenner CalleeOp = CalleeAM.Base.Reg; 133056893Sfenner } else 133156893Sfenner return false; 133256893Sfenner 133356893Sfenner // Allow calls which produce i1 results. 133456893Sfenner bool AndToI1 = false; 133556893Sfenner if (RetVT == MVT::i1) { 133656893Sfenner RetVT = MVT::i8; 133756893Sfenner AndToI1 = true; 133856893Sfenner } 133956893Sfenner 134056893Sfenner // Deal with call operands first. 134156893Sfenner SmallVector<Value*, 8> ArgVals; 134256893Sfenner SmallVector<unsigned, 8> Args; 134375115Sfenner SmallVector<EVT, 8> ArgVTs; 134475115Sfenner SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 134556893Sfenner Args.reserve(CS.arg_size()); 134656893Sfenner ArgVals.reserve(CS.arg_size()); 134756893Sfenner ArgVTs.reserve(CS.arg_size()); 134856893Sfenner ArgFlags.reserve(CS.arg_size()); 134956893Sfenner for (CallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 135056893Sfenner i != e; ++i) { 135156893Sfenner unsigned Arg = getRegForValue(*i); 135256893Sfenner if (Arg == 0) 135356893Sfenner return false; 135456893Sfenner ISD::ArgFlagsTy Flags; 135556893Sfenner unsigned AttrInd = i - CS.arg_begin() + 1; 135656893Sfenner if (CS.paramHasAttr(AttrInd, Attribute::SExt)) 135756893Sfenner Flags.setSExt(); 135856893Sfenner if (CS.paramHasAttr(AttrInd, Attribute::ZExt)) 135956893Sfenner Flags.setZExt(); 136056893Sfenner 136156893Sfenner // FIXME: Only handle *easy* calls for now. 136256893Sfenner if (CS.paramHasAttr(AttrInd, Attribute::InReg) || 136356893Sfenner CS.paramHasAttr(AttrInd, Attribute::StructRet) || 136456893Sfenner CS.paramHasAttr(AttrInd, Attribute::Nest) || 136575115Sfenner CS.paramHasAttr(AttrInd, Attribute::ByVal)) 136675115Sfenner return false; 136756893Sfenner 136856893Sfenner const Type *ArgTy = (*i)->getType(); 136956893Sfenner EVT ArgVT; 137056893Sfenner if (!isTypeLegal(ArgTy, ArgVT)) 137156893Sfenner return false; 137256893Sfenner unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 137356893Sfenner Flags.setOrigAlign(OriginalAlignment); 137456893Sfenner 137556893Sfenner Args.push_back(Arg); 137656893Sfenner ArgVals.push_back(*i); 137756893Sfenner ArgVTs.push_back(ArgVT); 137856893Sfenner ArgFlags.push_back(Flags); 137956893Sfenner } 138056893Sfenner 138156893Sfenner // Analyze operands of the call, assigning locations to each operand. 138256893Sfenner SmallVector<CCValAssign, 16> ArgLocs; 138356893Sfenner CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext()); 138456893Sfenner CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC)); 138556893Sfenner 138656893Sfenner // Get a count of how many bytes are to be pushed on the stack. 138756893Sfenner unsigned NumBytes = CCInfo.getNextStackOffset(); 138856893Sfenner 138956893Sfenner // Issue CALLSEQ_START 139056893Sfenner unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode(); 139156893Sfenner BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes); 139256893Sfenner 139356893Sfenner // Process argument: walk the register/memloc assignments, inserting 139456893Sfenner // copies / loads. 139556893Sfenner SmallVector<unsigned, 4> RegArgs; 139656893Sfenner for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 139756893Sfenner CCValAssign &VA = ArgLocs[i]; 139856893Sfenner unsigned Arg = Args[VA.getValNo()]; 139956893Sfenner EVT ArgVT = ArgVTs[VA.getValNo()]; 140056893Sfenner 140156893Sfenner // Promote the value if needed. 140256893Sfenner switch (VA.getLocInfo()) { 140356893Sfenner default: llvm_unreachable("Unknown loc info!"); 140456893Sfenner case CCValAssign::Full: break; 140556893Sfenner case CCValAssign::SExt: { 140656893Sfenner bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 140756893Sfenner Arg, ArgVT, Arg); 140856893Sfenner assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted; 140956893Sfenner Emitted = true; 141056893Sfenner ArgVT = VA.getLocVT(); 141156893Sfenner break; 141256893Sfenner } 141356893Sfenner case CCValAssign::ZExt: { 141456893Sfenner bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 141556893Sfenner Arg, ArgVT, Arg); 141656893Sfenner assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted; 141756893Sfenner Emitted = true; 141856893Sfenner ArgVT = VA.getLocVT(); 141956893Sfenner break; 142056893Sfenner } 142156893Sfenner case CCValAssign::AExt: { 1422127668Sbms bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), 142356893Sfenner Arg, ArgVT, Arg); 142456893Sfenner if (!Emitted) 142556893Sfenner Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), 142656893Sfenner Arg, ArgVT, Arg); 142756893Sfenner if (!Emitted) 142856893Sfenner Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), 142956893Sfenner Arg, ArgVT, Arg); 143056893Sfenner 143156893Sfenner assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted; 143256893Sfenner ArgVT = VA.getLocVT(); 143356893Sfenner break; 143456893Sfenner } 143556893Sfenner case CCValAssign::BCvt: { 143656893Sfenner unsigned BC = FastEmit_r(ArgVT.getSimpleVT(), VA.getLocVT().getSimpleVT(), 143756893Sfenner ISD::BIT_CONVERT, Arg); 143856893Sfenner assert(BC != 0 && "Failed to emit a bitcast!"); 143956893Sfenner Arg = BC; 144056893Sfenner ArgVT = VA.getLocVT(); 144156893Sfenner break; 144256893Sfenner } 144356893Sfenner } 144456893Sfenner 144556893Sfenner if (VA.isRegLoc()) { 144656893Sfenner TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT); 144756893Sfenner bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(), 144856893Sfenner Arg, RC, RC); 144956893Sfenner assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 145056893Sfenner Emitted = true; 145156893Sfenner RegArgs.push_back(VA.getLocReg()); 145256893Sfenner } else { 145356893Sfenner unsigned LocMemOffset = VA.getLocMemOffset(); 145475115Sfenner X86AddressMode AM; 145575115Sfenner AM.Base.Reg = StackPtr; 145656893Sfenner AM.Disp = LocMemOffset; 145756893Sfenner Value *ArgVal = ArgVals[VA.getValNo()]; 145856893Sfenner 145956893Sfenner // If this is a really simple value, emit this with the Value* version of 146056893Sfenner // X86FastEmitStore. If it isn't simple, we don't want to do this, as it 146156893Sfenner // can cause us to reevaluate the argument. 146256893Sfenner if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) 146356893Sfenner X86FastEmitStore(ArgVT, ArgVal, AM); 146456893Sfenner else 146556893Sfenner X86FastEmitStore(ArgVT, Arg, AM); 146675115Sfenner } 146775115Sfenner } 146856893Sfenner 146956893Sfenner // ELF / PIC requires GOT in the EBX register before function calls via PLT 147056893Sfenner // GOT pointer. 147156893Sfenner if (Subtarget->isPICStyleGOT()) { 147256893Sfenner TargetRegisterClass *RC = X86::GR32RegisterClass; 147356893Sfenner unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF); 147456893Sfenner bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC); 147556893Sfenner assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 147656893Sfenner Emitted = true; 147756893Sfenner } 147856893Sfenner 147956893Sfenner // Issue the call. 148056893Sfenner MachineInstrBuilder MIB; 148156893Sfenner if (CalleeOp) { 148256893Sfenner // Register-indirect call. 148356893Sfenner unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r; 148456893Sfenner MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp); 148556893Sfenner 148656893Sfenner } else { 148756893Sfenner // Direct call. 148856893Sfenner assert(GV && "Not a direct call"); 148956893Sfenner unsigned CallOpc = 149056893Sfenner Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32; 149175115Sfenner 149275115Sfenner // See if we need any target-specific flags on the GV operand. 149356893Sfenner unsigned char OpFlags = 0; 149456893Sfenner 149556893Sfenner // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 149656893Sfenner // external symbols most go through the PLT in PIC mode. If the symbol 149756893Sfenner // has hidden or protected visibility, or if it is static or local, then 149856893Sfenner // we don't need to use the PLT - we can directly call it. 149956893Sfenner if (Subtarget->isTargetELF() && 150056893Sfenner TM.getRelocationModel() == Reloc::PIC_ && 150156893Sfenner GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 150256893Sfenner OpFlags = X86II::MO_PLT; 150356893Sfenner } else if (Subtarget->isPICStyleStubAny() && 150456893Sfenner (GV->isDeclaration() || GV->isWeakForLinker()) && 150556893Sfenner Subtarget->getDarwinVers() < 9) { 150656893Sfenner // PC-relative references to external symbols should go through $stub, 150756893Sfenner // unless we're building with the leopard linker or later, which 150856893Sfenner // automatically synthesizes these stubs. 150956893Sfenner OpFlags = X86II::MO_DARWIN_STUB; 151056893Sfenner } 151156893Sfenner 151256893Sfenner 151356893Sfenner MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags); 151456893Sfenner } 151556893Sfenner 151656893Sfenner // Add an implicit use GOT pointer in EBX. 151756893Sfenner if (Subtarget->isPICStyleGOT()) 151856893Sfenner MIB.addReg(X86::EBX); 151956893Sfenner 152056893Sfenner // Add implicit physical register uses to the call. 152156893Sfenner for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 152256893Sfenner MIB.addReg(RegArgs[i]); 152356893Sfenner 152456893Sfenner // Issue CALLSEQ_END 152556893Sfenner unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode(); 152656893Sfenner BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0); 152756893Sfenner 152856893Sfenner // Now handle call return value (if any). 152956893Sfenner if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) { 153056893Sfenner SmallVector<CCValAssign, 16> RVLocs; 153156893Sfenner CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); 153256893Sfenner CCInfo.AnalyzeCallResult(RetVT, RetCC_X86); 153356893Sfenner 1534127668Sbms // Copy all of the result registers out of their specified physreg. 153556893Sfenner assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); 153656893Sfenner EVT CopyVT = RVLocs[0].getValVT(); 1537127668Sbms TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); 153856893Sfenner TargetRegisterClass *SrcRC = DstRC; 153956893Sfenner 154056893Sfenner // If this is a call to a function that returns an fp value on the x87 fp 154156893Sfenner // stack, but where we prefer to use the value in xmm registers, copy it 154256893Sfenner // out as F80 and use a truncate to move it from fp stack reg to xmm reg. 154356893Sfenner if ((RVLocs[0].getLocReg() == X86::ST0 || 154456893Sfenner RVLocs[0].getLocReg() == X86::ST1) && 154556893Sfenner isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { 154675115Sfenner CopyVT = MVT::f80; 154756893Sfenner SrcRC = X86::RSTRegisterClass; 154856893Sfenner DstRC = X86::RFP80RegisterClass; 154956893Sfenner } 155056893Sfenner 1551127668Sbms unsigned ResultReg = createResultReg(DstRC); 155256893Sfenner bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, 155356893Sfenner RVLocs[0].getLocReg(), DstRC, SrcRC); 155456893Sfenner assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted; 155556893Sfenner Emitted = true; 155656893Sfenner if (CopyVT != RVLocs[0].getValVT()) { 155756893Sfenner // Round the F80 the right size, which also moves to the appropriate xmm 155856893Sfenner // register. This is accomplished by storing the F80 value in memory and 155956893Sfenner // then loading it back. Ewww... 156056893Sfenner EVT ResVT = RVLocs[0].getValVT(); 156156893Sfenner unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; 156256893Sfenner unsigned MemSize = ResVT.getSizeInBits()/8; 156356893Sfenner int FI = MFI.CreateStackObject(MemSize, MemSize, false); 156456893Sfenner addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg); 156556893Sfenner DstRC = ResVT == MVT::f32 156656893Sfenner ? X86::FR32RegisterClass : X86::FR64RegisterClass; 156756893Sfenner Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; 156856893Sfenner ResultReg = createResultReg(DstRC); 156956893Sfenner addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI); 157056893Sfenner } 157156893Sfenner 157256893Sfenner if (AndToI1) { 157356893Sfenner // Mask out all but lowest bit for some call which produces an i1. 157456893Sfenner unsigned AndResult = createResultReg(X86::GR8RegisterClass); 157575115Sfenner BuildMI(MBB, DL, 157675115Sfenner TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1); 157756893Sfenner ResultReg = AndResult; 157856893Sfenner } 157956893Sfenner 158056893Sfenner UpdateValueMap(I, ResultReg); 158156893Sfenner } 158256893Sfenner 158356893Sfenner return true; 158456893Sfenner} 158556893Sfenner 158656893Sfenner 158756893Sfennerbool 158856893SfennerX86FastISel::TargetSelectInstruction(Instruction *I) { 158956893Sfenner switch (I->getOpcode()) { 159056893Sfenner default: break; 159156893Sfenner case Instruction::Load: 159256893Sfenner return X86SelectLoad(I); 159356893Sfenner case Instruction::Store: 159456893Sfenner return X86SelectStore(I); 159575115Sfenner case Instruction::ICmp: 159675115Sfenner case Instruction::FCmp: 159756893Sfenner return X86SelectCmp(I); 159856893Sfenner case Instruction::ZExt: 159956893Sfenner return X86SelectZExt(I); 160056893Sfenner case Instruction::Br: 160156893Sfenner return X86SelectBranch(I); 160256893Sfenner case Instruction::Call: 160356893Sfenner return X86SelectCall(I); 160456893Sfenner case Instruction::LShr: 160556893Sfenner case Instruction::AShr: 160656893Sfenner case Instruction::Shl: 160756893Sfenner return X86SelectShift(I); 160856893Sfenner case Instruction::Select: 160956893Sfenner return X86SelectSelect(I); 161056893Sfenner case Instruction::Trunc: 161156893Sfenner return X86SelectTrunc(I); 161256893Sfenner case Instruction::FPExt: 161356893Sfenner return X86SelectFPExt(I); 161456893Sfenner case Instruction::FPTrunc: 161556893Sfenner return X86SelectFPTrunc(I); 161656893Sfenner case Instruction::ExtractValue: 161756893Sfenner return X86SelectExtractValue(I); 161856893Sfenner case Instruction::IntToPtr: // Deliberate fall-through. 161956893Sfenner case Instruction::PtrToInt: { 162056893Sfenner EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); 162156893Sfenner EVT DstVT = TLI.getValueType(I->getType()); 162256893Sfenner if (DstVT.bitsGT(SrcVT)) 162356893Sfenner return X86SelectZExt(I); 162456893Sfenner if (DstVT.bitsLT(SrcVT)) 162556893Sfenner return X86SelectTrunc(I); 162656893Sfenner unsigned Reg = getRegForValue(I->getOperand(0)); 1627127668Sbms if (Reg == 0) return false; 162856893Sfenner UpdateValueMap(I, Reg); 162956893Sfenner return true; 163056893Sfenner } 163156893Sfenner } 163256893Sfenner 163356893Sfenner return false; 163456893Sfenner} 163556893Sfenner 163656893Sfennerunsigned X86FastISel::TargetMaterializeConstant(Constant *C) { 163756893Sfenner EVT VT; 163856893Sfenner if (!isTypeLegal(C->getType(), VT)) 163956893Sfenner return false; 164056893Sfenner 164156893Sfenner // Get opcode and regclass of the output for the given load instruction. 164256893Sfenner unsigned Opc = 0; 164356893Sfenner const TargetRegisterClass *RC = NULL; 164456893Sfenner switch (VT.getSimpleVT().SimpleTy) { 164556893Sfenner default: return false; 164656893Sfenner case MVT::i8: 164756893Sfenner Opc = X86::MOV8rm; 164856893Sfenner RC = X86::GR8RegisterClass; 164956893Sfenner break; 165056893Sfenner case MVT::i16: 165156893Sfenner Opc = X86::MOV16rm; 165256893Sfenner RC = X86::GR16RegisterClass; 165356893Sfenner break; 165456893Sfenner case MVT::i32: 165556893Sfenner Opc = X86::MOV32rm; 165656893Sfenner RC = X86::GR32RegisterClass; 165756893Sfenner break; 165856893Sfenner case MVT::i64: 165956893Sfenner // Must be in x86-64 mode. 166056893Sfenner Opc = X86::MOV64rm; 166156893Sfenner RC = X86::GR64RegisterClass; 166256893Sfenner break; 166356893Sfenner case MVT::f32: 166475115Sfenner if (Subtarget->hasSSE1()) { 166556893Sfenner Opc = X86::MOVSSrm; 166656893Sfenner RC = X86::FR32RegisterClass; 166775115Sfenner } else { 166875115Sfenner Opc = X86::LD_Fp32m; 166956893Sfenner RC = X86::RFP32RegisterClass; 167056893Sfenner } 167156893Sfenner break; 167256893Sfenner case MVT::f64: 167375115Sfenner if (Subtarget->hasSSE2()) { 167456893Sfenner Opc = X86::MOVSDrm; 167556893Sfenner RC = X86::FR64RegisterClass; 1676127668Sbms } else { 167756893Sfenner Opc = X86::LD_Fp64m; 167856893Sfenner RC = X86::RFP64RegisterClass; 167956893Sfenner } 168056893Sfenner break; 168175115Sfenner case MVT::f80: 168275115Sfenner // No f80 support yet. 168356893Sfenner return false; 168456893Sfenner } 168556893Sfenner 168656893Sfenner // Materialize addresses with LEA instructions. 168756893Sfenner if (isa<GlobalValue>(C)) { 168856893Sfenner X86AddressMode AM; 168975115Sfenner if (X86SelectAddress(C, AM)) { 169056893Sfenner if (TLI.getPointerTy() == MVT::i32) 169156893Sfenner Opc = X86::LEA32r; 169256893Sfenner else 169356893Sfenner Opc = X86::LEA64r; 169456893Sfenner unsigned ResultReg = createResultReg(RC); 169556893Sfenner addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 169656893Sfenner return ResultReg; 169756893Sfenner } 169856893Sfenner return 0; 169956893Sfenner } 170056893Sfenner 170156893Sfenner // MachineConstantPool wants an explicit alignment. 170256893Sfenner unsigned Align = TD.getPrefTypeAlignment(C->getType()); 170356893Sfenner if (Align == 0) { 170456893Sfenner // Alignment of vector types. FIXME! 170556893Sfenner Align = TD.getTypeAllocSize(C->getType()); 170656893Sfenner } 170756893Sfenner 170856893Sfenner // x86-32 PIC requires a PIC base register for constant pools. 170956893Sfenner unsigned PICBase = 0; 171056893Sfenner unsigned char OpFlag = 0; 171156893Sfenner if (Subtarget->isPICStyleStubPIC()) { // Not dynamic-no-pic 171256893Sfenner OpFlag = X86II::MO_PIC_BASE_OFFSET; 171356893Sfenner PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 171475115Sfenner } else if (Subtarget->isPICStyleGOT()) { 171575115Sfenner OpFlag = X86II::MO_GOTOFF; 171656893Sfenner PICBase = getInstrInfo()->getGlobalBaseReg(&MF); 171756893Sfenner } else if (Subtarget->isPICStyleRIPRel() && 171856893Sfenner TM.getCodeModel() == CodeModel::Small) { 171956893Sfenner PICBase = X86::RIP; 172075115Sfenner } 172156893Sfenner 172256893Sfenner // Create the load from the constant pool. 1723127668Sbms unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align); 172456893Sfenner unsigned ResultReg = createResultReg(RC); 172556893Sfenner addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), 172656893Sfenner MCPOffset, PICBase, OpFlag); 172756893Sfenner 172875115Sfenner return ResultReg; 172975115Sfenner} 173056893Sfenner 173156893Sfennerunsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) { 173256893Sfenner // Fail on dynamic allocas. At this point, getRegForValue has already 173356893Sfenner // checked its CSE maps, so if we're here trying to handle a dynamic 173456893Sfenner // alloca, we're not going to succeed. X86SelectAddress has a 173556893Sfenner // check for dynamic allocas, because it's called directly from 173675115Sfenner // various places, but TargetMaterializeAlloca also needs a check 173756893Sfenner // in order to avoid recursion between getRegForValue, 173856893Sfenner // X86SelectAddrss, and TargetMaterializeAlloca. 173956893Sfenner if (!StaticAllocaMap.count(C)) 174056893Sfenner return 0; 174156893Sfenner 174256893Sfenner X86AddressMode AM; 174356893Sfenner if (!X86SelectAddress(C, AM)) 174456893Sfenner return 0; 174556893Sfenner unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 174656893Sfenner TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); 174756893Sfenner unsigned ResultReg = createResultReg(RC); 174856893Sfenner addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM); 174956893Sfenner return ResultReg; 175056893Sfenner} 175175115Sfenner 175275115Sfennernamespace llvm { 175356893Sfenner llvm::FastISel *X86::createFastISel(MachineFunction &mf, 175456893Sfenner DenseMap<const Value *, unsigned> &vm, 175556893Sfenner DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, 175656893Sfenner DenseMap<const AllocaInst *, int> &am 175756893Sfenner#ifndef NDEBUG 175856893Sfenner , SmallSet<Instruction*, 8> &cil 175956893Sfenner#endif 176056893Sfenner ) { 176175115Sfenner return new X86FastISel(mf, vm, bm, am 176256893Sfenner#ifndef NDEBUG 176356893Sfenner , cil 176456893Sfenner#endif 176575115Sfenner ); 176656893Sfenner } 176756893Sfenner} 176856893Sfenner