X86CodeEmitter.cpp revision 239462
1234353Sdim//===-- X86CodeEmitter.cpp - Convert X86 code to machine code -------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the pass that transforms the X86 machine instructions into 11193323Sed// relocatable machine code. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#define DEBUG_TYPE "x86-emitter" 16193323Sed#include "X86InstrInfo.h" 17193323Sed#include "X86JITInfo.h" 18193323Sed#include "X86Subtarget.h" 19193323Sed#include "X86TargetMachine.h" 20193323Sed#include "X86Relocations.h" 21193323Sed#include "X86.h" 22198892Srdivacky#include "llvm/LLVMContext.h" 23193323Sed#include "llvm/PassManager.h" 24193323Sed#include "llvm/CodeGen/JITCodeEmitter.h" 25193323Sed#include "llvm/CodeGen/MachineFunctionPass.h" 26193323Sed#include "llvm/CodeGen/MachineInstr.h" 27193323Sed#include "llvm/CodeGen/MachineModuleInfo.h" 28193323Sed#include "llvm/CodeGen/Passes.h" 29193323Sed#include "llvm/Function.h" 30193323Sed#include "llvm/ADT/Statistic.h" 31198090Srdivacky#include "llvm/MC/MCCodeEmitter.h" 32198090Srdivacky#include "llvm/MC/MCExpr.h" 33198090Srdivacky#include "llvm/MC/MCInst.h" 34193323Sed#include "llvm/Support/Debug.h" 35198090Srdivacky#include "llvm/Support/ErrorHandling.h" 36198090Srdivacky#include "llvm/Support/raw_ostream.h" 37193323Sed#include "llvm/Target/TargetOptions.h" 38193323Sedusing namespace llvm; 39193323Sed 40193323SedSTATISTIC(NumEmitted, "Number of machine instructions emitted"); 41193323Sed 42193323Sednamespace { 43198090Srdivacky template<class CodeEmitter> 44198892Srdivacky class Emitter : public MachineFunctionPass { 45193323Sed const X86InstrInfo *II; 46193323Sed const TargetData *TD; 47193323Sed X86TargetMachine &TM; 48193323Sed CodeEmitter &MCE; 49205218Srdivacky MachineModuleInfo *MMI; 50193323Sed intptr_t PICBaseOffset; 51193323Sed bool Is64BitMode; 52193323Sed bool IsPIC; 53193323Sed public: 54193323Sed static char ID; 55193323Sed explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce) 56239462Sdim : MachineFunctionPass(ID), II(0), TD(0), TM(tm), 57193323Sed MCE(mce), PICBaseOffset(0), Is64BitMode(false), 58193323Sed IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 59193323Sed Emitter(X86TargetMachine &tm, CodeEmitter &mce, 60193323Sed const X86InstrInfo &ii, const TargetData &td, bool is64) 61239462Sdim : MachineFunctionPass(ID), II(&ii), TD(&td), TM(tm), 62193323Sed MCE(mce), PICBaseOffset(0), Is64BitMode(is64), 63193323Sed IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 64193323Sed 65193323Sed bool runOnMachineFunction(MachineFunction &MF); 66193323Sed 67193323Sed virtual const char *getPassName() const { 68193323Sed return "X86 Machine Code Emitter"; 69193323Sed } 70193323Sed 71239462Sdim void emitOpcodePrefix(uint64_t TSFlags, int MemOperand, 72239462Sdim const MachineInstr &MI, 73239462Sdim const MCInstrDesc *Desc) const; 74239462Sdim 75239462Sdim void emitVEXOpcodePrefix(uint64_t TSFlags, int MemOperand, 76239462Sdim const MachineInstr &MI, 77239462Sdim const MCInstrDesc *Desc) const; 78239462Sdim 79239462Sdim void emitSegmentOverridePrefix(uint64_t TSFlags, 80239462Sdim int MemOperand, 81239462Sdim const MachineInstr &MI) const; 82239462Sdim 83224145Sdim void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc); 84239462Sdim 85193323Sed void getAnalysisUsage(AnalysisUsage &AU) const { 86198090Srdivacky AU.setPreservesAll(); 87193323Sed AU.addRequired<MachineModuleInfo>(); 88193323Sed MachineFunctionPass::getAnalysisUsage(AU); 89193323Sed } 90193323Sed 91193323Sed private: 92193323Sed void emitPCRelativeBlockAddress(MachineBasicBlock *MBB); 93207618Srdivacky void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 94193323Sed intptr_t Disp = 0, intptr_t PCAdj = 0, 95199481Srdivacky bool Indirect = false); 96193323Sed void emitExternalSymbolAddress(const char *ES, unsigned Reloc); 97193323Sed void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0, 98193323Sed intptr_t PCAdj = 0); 99193323Sed void emitJumpTableAddress(unsigned JTI, unsigned Reloc, 100193323Sed intptr_t PCAdj = 0); 101193323Sed 102193323Sed void emitDisplacementField(const MachineOperand *RelocOp, int DispVal, 103198090Srdivacky intptr_t Adj = 0, bool IsPCRel = true); 104193323Sed 105193323Sed void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField); 106193323Sed void emitRegModRMByte(unsigned RegOpcodeField); 107193323Sed void emitSIBByte(unsigned SS, unsigned Index, unsigned Base); 108193323Sed void emitConstant(uint64_t Val, unsigned Size); 109193323Sed 110193323Sed void emitMemModRMByte(const MachineInstr &MI, 111193323Sed unsigned Op, unsigned RegOpcodeField, 112193323Sed intptr_t PCAdj = 0); 113193323Sed }; 114193323Sed 115193323Sedtemplate<class CodeEmitter> 116193323Sed char Emitter<CodeEmitter>::ID = 0; 117198090Srdivacky} // end anonymous namespace. 118193323Sed 119193323Sed/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code 120193323Sed/// to the specified templated MachineCodeEmitter object. 121198090SrdivackyFunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM, 122198090Srdivacky JITCodeEmitter &JCE) { 123193323Sed return new Emitter<JITCodeEmitter>(TM, JCE); 124193323Sed} 125193323Sed 126193323Sedtemplate<class CodeEmitter> 127193323Sedbool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) { 128205218Srdivacky MMI = &getAnalysis<MachineModuleInfo>(); 129205218Srdivacky MCE.setModuleInfo(MMI); 130239462Sdim 131193323Sed II = TM.getInstrInfo(); 132193323Sed TD = TM.getTargetData(); 133193323Sed Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit(); 134193323Sed IsPIC = TM.getRelocationModel() == Reloc::PIC_; 135239462Sdim 136193323Sed do { 137239462Sdim DEBUG(dbgs() << "JITTing function '" 138198090Srdivacky << MF.getFunction()->getName() << "'\n"); 139193323Sed MCE.startFunction(MF); 140239462Sdim for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 141193323Sed MBB != E; ++MBB) { 142193323Sed MCE.StartMachineBasicBlock(MBB); 143218893Sdim for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 144193323Sed I != E; ++I) { 145224145Sdim const MCInstrDesc &Desc = I->getDesc(); 146193323Sed emitInstruction(*I, &Desc); 147193323Sed // MOVPC32r is basically a call plus a pop instruction. 148193323Sed if (Desc.getOpcode() == X86::MOVPC32r) 149193323Sed emitInstruction(*I, &II->get(X86::POP32r)); 150210299Sed ++NumEmitted; // Keep track of the # of mi's emitted 151193323Sed } 152193323Sed } 153193323Sed } while (MCE.finishFunction(MF)); 154193323Sed 155193323Sed return false; 156193323Sed} 157193323Sed 158212904Sdim/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64 159212904Sdim/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 160212904Sdim/// size, and 3) use of X86-64 extended registers. 161212904Sdimstatic unsigned determineREX(const MachineInstr &MI) { 162212904Sdim unsigned REX = 0; 163224145Sdim const MCInstrDesc &Desc = MI.getDesc(); 164239462Sdim 165212904Sdim // Pseudo instructions do not need REX prefix byte. 166212904Sdim if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) 167212904Sdim return 0; 168212904Sdim if (Desc.TSFlags & X86II::REX_W) 169212904Sdim REX |= 1 << 3; 170239462Sdim 171212904Sdim unsigned NumOps = Desc.getNumOperands(); 172212904Sdim if (NumOps) { 173212904Sdim bool isTwoAddr = NumOps > 1 && 174239462Sdim Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; 175239462Sdim 176212904Sdim // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 177212904Sdim unsigned i = isTwoAddr ? 1 : 0; 178212904Sdim for (unsigned e = NumOps; i != e; ++i) { 179212904Sdim const MachineOperand& MO = MI.getOperand(i); 180212904Sdim if (MO.isReg()) { 181212904Sdim unsigned Reg = MO.getReg(); 182226633Sdim if (X86II::isX86_64NonExtLowByteReg(Reg)) 183212904Sdim REX |= 0x40; 184212904Sdim } 185212904Sdim } 186239462Sdim 187212904Sdim switch (Desc.TSFlags & X86II::FormMask) { 188212904Sdim case X86II::MRMInitReg: 189212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 190212904Sdim REX |= (1 << 0) | (1 << 2); 191212904Sdim break; 192212904Sdim case X86II::MRMSrcReg: { 193212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 194212904Sdim REX |= 1 << 2; 195212904Sdim i = isTwoAddr ? 2 : 1; 196212904Sdim for (unsigned e = NumOps; i != e; ++i) { 197212904Sdim const MachineOperand& MO = MI.getOperand(i); 198212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MO)) 199212904Sdim REX |= 1 << 0; 200212904Sdim } 201212904Sdim break; 202212904Sdim } 203212904Sdim case X86II::MRMSrcMem: { 204212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 205212904Sdim REX |= 1 << 2; 206212904Sdim unsigned Bit = 0; 207212904Sdim i = isTwoAddr ? 2 : 1; 208212904Sdim for (; i != NumOps; ++i) { 209212904Sdim const MachineOperand& MO = MI.getOperand(i); 210212904Sdim if (MO.isReg()) { 211212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MO)) 212212904Sdim REX |= 1 << Bit; 213212904Sdim Bit++; 214212904Sdim } 215212904Sdim } 216212904Sdim break; 217212904Sdim } 218212904Sdim case X86II::MRM0m: case X86II::MRM1m: 219212904Sdim case X86II::MRM2m: case X86II::MRM3m: 220212904Sdim case X86II::MRM4m: case X86II::MRM5m: 221212904Sdim case X86II::MRM6m: case X86II::MRM7m: 222212904Sdim case X86II::MRMDestMem: { 223212904Sdim unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); 224212904Sdim i = isTwoAddr ? 1 : 0; 225212904Sdim if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e))) 226212904Sdim REX |= 1 << 2; 227212904Sdim unsigned Bit = 0; 228212904Sdim for (; i != e; ++i) { 229212904Sdim const MachineOperand& MO = MI.getOperand(i); 230212904Sdim if (MO.isReg()) { 231212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MO)) 232212904Sdim REX |= 1 << Bit; 233212904Sdim Bit++; 234212904Sdim } 235212904Sdim } 236212904Sdim break; 237212904Sdim } 238212904Sdim default: { 239212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 240212904Sdim REX |= 1 << 0; 241212904Sdim i = isTwoAddr ? 2 : 1; 242212904Sdim for (unsigned e = NumOps; i != e; ++i) { 243212904Sdim const MachineOperand& MO = MI.getOperand(i); 244212904Sdim if (X86InstrInfo::isX86_64ExtendedReg(MO)) 245212904Sdim REX |= 1 << 2; 246212904Sdim } 247212904Sdim break; 248212904Sdim } 249212904Sdim } 250212904Sdim } 251212904Sdim return REX; 252212904Sdim} 253212904Sdim 254212904Sdim 255193323Sed/// emitPCRelativeBlockAddress - This method keeps track of the information 256193323Sed/// necessary to resolve the address of this block later and emits a dummy 257193323Sed/// value. 258193323Sed/// 259193323Sedtemplate<class CodeEmitter> 260193323Sedvoid Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { 261193323Sed // Remember where this reference was and where it is to so we can 262193323Sed // deal with it later. 263193323Sed MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 264193323Sed X86::reloc_pcrel_word, MBB)); 265193323Sed MCE.emitWordLE(0); 266193323Sed} 267193323Sed 268193323Sed/// emitGlobalAddress - Emit the specified address to the code stream assuming 269193323Sed/// this is part of a "take the address of a global" instruction. 270193323Sed/// 271193323Sedtemplate<class CodeEmitter> 272207618Srdivackyvoid Emitter<CodeEmitter>::emitGlobalAddress(const GlobalValue *GV, 273207618Srdivacky unsigned Reloc, 274193323Sed intptr_t Disp /* = 0 */, 275193323Sed intptr_t PCAdj /* = 0 */, 276193323Sed bool Indirect /* = false */) { 277198090Srdivacky intptr_t RelocCST = Disp; 278193323Sed if (Reloc == X86::reloc_picrel_word) 279193323Sed RelocCST = PICBaseOffset; 280193323Sed else if (Reloc == X86::reloc_pcrel_word) 281193323Sed RelocCST = PCAdj; 282193323Sed MachineRelocation MR = Indirect 283193323Sed ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 284207618Srdivacky const_cast<GlobalValue *>(GV), 285207618Srdivacky RelocCST, false) 286193323Sed : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 287207618Srdivacky const_cast<GlobalValue *>(GV), RelocCST, false); 288193323Sed MCE.addRelocation(MR); 289193323Sed // The relocated value will be added to the displacement 290193323Sed if (Reloc == X86::reloc_absolute_dword) 291193323Sed MCE.emitDWordLE(Disp); 292193323Sed else 293193323Sed MCE.emitWordLE((int32_t)Disp); 294193323Sed} 295193323Sed 296193323Sed/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 297193323Sed/// be emitted to the current location in the function, and allow it to be PC 298193323Sed/// relative. 299193323Sedtemplate<class CodeEmitter> 300193323Sedvoid Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES, 301193323Sed unsigned Reloc) { 302193323Sed intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0; 303203954Srdivacky 304203954Srdivacky // X86 never needs stubs because instruction selection will always pick 305203954Srdivacky // an instruction sequence that is large enough to hold any address 306203954Srdivacky // to a symbol. 307203954Srdivacky // (see X86ISelLowering.cpp, near 2039: X86TargetLowering::LowerCall) 308203954Srdivacky bool NeedStub = false; 309193323Sed MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 310203954Srdivacky Reloc, ES, RelocCST, 311203954Srdivacky 0, NeedStub)); 312193323Sed if (Reloc == X86::reloc_absolute_dword) 313193323Sed MCE.emitDWordLE(0); 314193323Sed else 315193323Sed MCE.emitWordLE(0); 316193323Sed} 317193323Sed 318193323Sed/// emitConstPoolAddress - Arrange for the address of an constant pool 319193323Sed/// to be emitted to the current location in the function, and allow it to be PC 320193323Sed/// relative. 321193323Sedtemplate<class CodeEmitter> 322193323Sedvoid Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc, 323193323Sed intptr_t Disp /* = 0 */, 324193323Sed intptr_t PCAdj /* = 0 */) { 325193323Sed intptr_t RelocCST = 0; 326193323Sed if (Reloc == X86::reloc_picrel_word) 327193323Sed RelocCST = PICBaseOffset; 328193323Sed else if (Reloc == X86::reloc_pcrel_word) 329193323Sed RelocCST = PCAdj; 330193323Sed MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 331193323Sed Reloc, CPI, RelocCST)); 332193323Sed // The relocated value will be added to the displacement 333193323Sed if (Reloc == X86::reloc_absolute_dword) 334193323Sed MCE.emitDWordLE(Disp); 335193323Sed else 336193323Sed MCE.emitWordLE((int32_t)Disp); 337193323Sed} 338193323Sed 339193323Sed/// emitJumpTableAddress - Arrange for the address of a jump table to 340193323Sed/// be emitted to the current location in the function, and allow it to be PC 341193323Sed/// relative. 342193323Sedtemplate<class CodeEmitter> 343193323Sedvoid Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc, 344193323Sed intptr_t PCAdj /* = 0 */) { 345193323Sed intptr_t RelocCST = 0; 346193323Sed if (Reloc == X86::reloc_picrel_word) 347193323Sed RelocCST = PICBaseOffset; 348193323Sed else if (Reloc == X86::reloc_pcrel_word) 349193323Sed RelocCST = PCAdj; 350193323Sed MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 351193323Sed Reloc, JTI, RelocCST)); 352193323Sed // The relocated value will be added to the displacement 353193323Sed if (Reloc == X86::reloc_absolute_dword) 354193323Sed MCE.emitDWordLE(0); 355193323Sed else 356193323Sed MCE.emitWordLE(0); 357193323Sed} 358193323Sed 359193323Sedinline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, 360193323Sed unsigned RM) { 361193323Sed assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 362193323Sed return RM | (RegOpcode << 3) | (Mod << 6); 363193323Sed} 364193323Sed 365193323Sedtemplate<class CodeEmitter> 366193323Sedvoid Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg, 367193323Sed unsigned RegOpcodeFld){ 368226633Sdim MCE.emitByte(ModRMByte(3, RegOpcodeFld, X86_MC::getX86RegNum(ModRMReg))); 369193323Sed} 370193323Sed 371193323Sedtemplate<class CodeEmitter> 372193323Sedvoid Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) { 373193323Sed MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0)); 374193323Sed} 375193323Sed 376193323Sedtemplate<class CodeEmitter> 377239462Sdimvoid Emitter<CodeEmitter>::emitSIBByte(unsigned SS, 378193323Sed unsigned Index, 379193323Sed unsigned Base) { 380193323Sed // SIB byte is in the same format as the ModRMByte... 381193323Sed MCE.emitByte(ModRMByte(SS, Index, Base)); 382193323Sed} 383193323Sed 384193323Sedtemplate<class CodeEmitter> 385193323Sedvoid Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) { 386193323Sed // Output the constant in little endian byte order... 387193323Sed for (unsigned i = 0; i != Size; ++i) { 388193323Sed MCE.emitByte(Val & 255); 389193323Sed Val >>= 8; 390193323Sed } 391193323Sed} 392193323Sed 393239462Sdim/// isDisp8 - Return true if this signed displacement fits in a 8-bit 394239462Sdim/// sign-extended field. 395193323Sedstatic bool isDisp8(int Value) { 396193323Sed return Value == (signed char)Value; 397193323Sed} 398193323Sed 399198090Srdivackystatic bool gvNeedsNonLazyPtr(const MachineOperand &GVOp, 400198090Srdivacky const TargetMachine &TM) { 401198090Srdivacky // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer 402193323Sed // mechanism as 32-bit mode. 403239462Sdim if (TM.getSubtarget<X86Subtarget>().is64Bit() && 404198090Srdivacky !TM.getSubtarget<X86Subtarget>().isTargetDarwin()) 405198090Srdivacky return false; 406239462Sdim 407198090Srdivacky // Return true if this is a reference to a stub containing the address of the 408198090Srdivacky // global, not the global itself. 409198090Srdivacky return isGlobalStubReference(GVOp.getTargetFlags()); 410193323Sed} 411193323Sed 412193323Sedtemplate<class CodeEmitter> 413193323Sedvoid Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp, 414198090Srdivacky int DispVal, 415198090Srdivacky intptr_t Adj /* = 0 */, 416198090Srdivacky bool IsPCRel /* = true */) { 417193323Sed // If this is a simple integer displacement that doesn't require a relocation, 418193323Sed // emit it now. 419193323Sed if (!RelocOp) { 420193323Sed emitConstant(DispVal, 4); 421193323Sed return; 422193323Sed } 423198090Srdivacky 424193323Sed // Otherwise, this is something that requires a relocation. Emit it as such 425193323Sed // now. 426198090Srdivacky unsigned RelocType = Is64BitMode ? 427198090Srdivacky (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext) 428198090Srdivacky : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 429193323Sed if (RelocOp->isGlobal()) { 430193323Sed // In 64-bit static small code model, we could potentially emit absolute. 431198090Srdivacky // But it's probably not beneficial. If the MCE supports using RIP directly 432239462Sdim // do it, otherwise fallback to absolute (this is determined by IsPCRel). 433193323Sed // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative 434193323Sed // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute 435198090Srdivacky bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM); 436198090Srdivacky emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(), 437199481Srdivacky Adj, Indirect); 438198090Srdivacky } else if (RelocOp->isSymbol()) { 439198090Srdivacky emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType); 440193323Sed } else if (RelocOp->isCPI()) { 441198090Srdivacky emitConstPoolAddress(RelocOp->getIndex(), RelocType, 442198090Srdivacky RelocOp->getOffset(), Adj); 443193323Sed } else { 444198090Srdivacky assert(RelocOp->isJTI() && "Unexpected machine operand!"); 445198090Srdivacky emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj); 446193323Sed } 447193323Sed} 448193323Sed 449193323Sedtemplate<class CodeEmitter> 450193323Sedvoid Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI, 451198090Srdivacky unsigned Op,unsigned RegOpcodeField, 452198090Srdivacky intptr_t PCAdj) { 453193323Sed const MachineOperand &Op3 = MI.getOperand(Op+3); 454193323Sed int DispVal = 0; 455193323Sed const MachineOperand *DispForReloc = 0; 456239462Sdim 457193323Sed // Figure out what sort of displacement we have to handle here. 458193323Sed if (Op3.isGlobal()) { 459193323Sed DispForReloc = &Op3; 460198090Srdivacky } else if (Op3.isSymbol()) { 461198090Srdivacky DispForReloc = &Op3; 462193323Sed } else if (Op3.isCPI()) { 463198090Srdivacky if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) { 464193323Sed DispForReloc = &Op3; 465193323Sed } else { 466193323Sed DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex()); 467193323Sed DispVal += Op3.getOffset(); 468193323Sed } 469193323Sed } else if (Op3.isJTI()) { 470198090Srdivacky if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) { 471193323Sed DispForReloc = &Op3; 472193323Sed } else { 473193323Sed DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex()); 474193323Sed } 475193323Sed } else { 476193323Sed DispVal = Op3.getImm(); 477193323Sed } 478193323Sed 479193323Sed const MachineOperand &Base = MI.getOperand(Op); 480193323Sed const MachineOperand &Scale = MI.getOperand(Op+1); 481193323Sed const MachineOperand &IndexReg = MI.getOperand(Op+2); 482193323Sed 483193323Sed unsigned BaseReg = Base.getReg(); 484239462Sdim 485207618Srdivacky // Handle %rip relative addressing. 486207618Srdivacky if (BaseReg == X86::RIP || 487207618Srdivacky (Is64BitMode && DispForReloc)) { // [disp32+RIP] in X86-64 mode 488207618Srdivacky assert(IndexReg.getReg() == 0 && Is64BitMode && 489207618Srdivacky "Invalid rip-relative address"); 490207618Srdivacky MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); 491207618Srdivacky emitDisplacementField(DispForReloc, DispVal, PCAdj, true); 492207618Srdivacky return; 493207618Srdivacky } 494193323Sed 495198090Srdivacky // Indicate that the displacement will use an pcrel or absolute reference 496198090Srdivacky // by default. MCEs able to resolve addresses on-the-fly use pcrel by default 497198090Srdivacky // while others, unless explicit asked to use RIP, use absolute references. 498198090Srdivacky bool IsPCRel = MCE.earlyResolveAddresses() ? true : false; 499198090Srdivacky 500193323Sed // Is a SIB byte needed? 501239462Sdim // If no BaseReg, issue a RIP relative instruction only if the MCE can 502198090Srdivacky // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 503198090Srdivacky // 2-7) and absolute references. 504203954Srdivacky unsigned BaseRegNo = -1U; 505203954Srdivacky if (BaseReg != 0 && BaseReg != X86::RIP) 506226633Sdim BaseRegNo = X86_MC::getX86RegNum(BaseReg); 507203954Srdivacky 508203954Srdivacky if (// The SIB byte must be used if there is an index register. 509239462Sdim IndexReg.getReg() == 0 && 510203954Srdivacky // The SIB byte must be used if the base is ESP/RSP/R12, all of which 511203954Srdivacky // encode to an R/M value of 4, which indicates that a SIB byte is 512203954Srdivacky // present. 513203954Srdivacky BaseRegNo != N86::ESP && 514203954Srdivacky // If there is no base register and we're in 64-bit mode, we need a SIB 515203954Srdivacky // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 516203954Srdivacky (!Is64BitMode || BaseReg != 0)) { 517203954Srdivacky if (BaseReg == 0 || // [disp32] in X86-32 mode 518203954Srdivacky BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode 519193323Sed MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); 520198090Srdivacky emitDisplacementField(DispForReloc, DispVal, PCAdj, true); 521203954Srdivacky return; 522193323Sed } 523239462Sdim 524203954Srdivacky // If the base is not EBP/ESP and there is no displacement, use simple 525203954Srdivacky // indirect register encoding, this handles addresses like [EAX]. The 526203954Srdivacky // encoding for [EBP] with no displacement means [disp32] so we handle it 527203954Srdivacky // by emitting a displacement of 0 below. 528203954Srdivacky if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { 529203954Srdivacky MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo)); 530203954Srdivacky return; 531193323Sed } 532239462Sdim 533203954Srdivacky // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 534203954Srdivacky if (!DispForReloc && isDisp8(DispVal)) { 535203954Srdivacky MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo)); 536203954Srdivacky emitConstant(DispVal, 1); 537203954Srdivacky return; 538203954Srdivacky } 539239462Sdim 540203954Srdivacky // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 541203954Srdivacky MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo)); 542203954Srdivacky emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel); 543203954Srdivacky return; 544203954Srdivacky } 545239462Sdim 546203954Srdivacky // Otherwise we need a SIB byte, so start by outputting the ModR/M byte first. 547203954Srdivacky assert(IndexReg.getReg() != X86::ESP && 548203954Srdivacky IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 549193323Sed 550203954Srdivacky bool ForceDisp32 = false; 551203954Srdivacky bool ForceDisp8 = false; 552203954Srdivacky if (BaseReg == 0) { 553203954Srdivacky // If there is no base register, we emit the special case SIB byte with 554203954Srdivacky // MOD=0, BASE=4, to JUST get the index, scale, and displacement. 555203954Srdivacky MCE.emitByte(ModRMByte(0, RegOpcodeField, 4)); 556203954Srdivacky ForceDisp32 = true; 557203954Srdivacky } else if (DispForReloc) { 558203954Srdivacky // Emit the normal disp32 encoding. 559203954Srdivacky MCE.emitByte(ModRMByte(2, RegOpcodeField, 4)); 560203954Srdivacky ForceDisp32 = true; 561207618Srdivacky } else if (DispVal == 0 && BaseRegNo != N86::EBP) { 562203954Srdivacky // Emit no displacement ModR/M byte 563203954Srdivacky MCE.emitByte(ModRMByte(0, RegOpcodeField, 4)); 564203954Srdivacky } else if (isDisp8(DispVal)) { 565203954Srdivacky // Emit the disp8 encoding... 566203954Srdivacky MCE.emitByte(ModRMByte(1, RegOpcodeField, 4)); 567203954Srdivacky ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 568203954Srdivacky } else { 569203954Srdivacky // Emit the normal disp32 encoding... 570203954Srdivacky MCE.emitByte(ModRMByte(2, RegOpcodeField, 4)); 571203954Srdivacky } 572193323Sed 573203954Srdivacky // Calculate what the SS field value should be... 574226633Sdim static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; 575203954Srdivacky unsigned SS = SSTable[Scale.getImm()]; 576193323Sed 577203954Srdivacky if (BaseReg == 0) { 578239462Sdim // Handle the SIB byte for the case where there is no base, see Intel 579203954Srdivacky // Manual 2A, table 2-7. The displacement has already been output. 580203954Srdivacky unsigned IndexRegNo; 581203954Srdivacky if (IndexReg.getReg()) 582226633Sdim IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg()); 583203954Srdivacky else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 584203954Srdivacky IndexRegNo = 4; 585203954Srdivacky emitSIBByte(SS, IndexRegNo, 5); 586203954Srdivacky } else { 587226633Sdim unsigned BaseRegNo = X86_MC::getX86RegNum(BaseReg); 588203954Srdivacky unsigned IndexRegNo; 589203954Srdivacky if (IndexReg.getReg()) 590226633Sdim IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg()); 591203954Srdivacky else 592203954Srdivacky IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 593203954Srdivacky emitSIBByte(SS, IndexRegNo, BaseRegNo); 594193323Sed } 595203954Srdivacky 596203954Srdivacky // Do we need to output a displacement? 597203954Srdivacky if (ForceDisp8) { 598203954Srdivacky emitConstant(DispVal, 1); 599203954Srdivacky } else if (DispVal != 0 || ForceDisp32) { 600203954Srdivacky emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel); 601203954Srdivacky } 602193323Sed} 603193323Sed 604228379Sdimstatic const MCInstrDesc *UpdateOp(MachineInstr &MI, const X86InstrInfo *II, 605228379Sdim unsigned Opcode) { 606228379Sdim const MCInstrDesc *Desc = &II->get(Opcode); 607228379Sdim MI.setDesc(*Desc); 608228379Sdim return Desc; 609228379Sdim} 610228379Sdim 611239462Sdim/// Is16BitMemOperand - Return true if the specified instruction has 612239462Sdim/// a 16-bit memory operand. Op specifies the operand # of the memoperand. 613239462Sdimstatic bool Is16BitMemOperand(const MachineInstr &MI, unsigned Op) { 614239462Sdim const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 615239462Sdim const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 616193323Sed 617239462Sdim if ((BaseReg.getReg() != 0 && 618239462Sdim X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 619239462Sdim (IndexReg.getReg() != 0 && 620239462Sdim X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 621239462Sdim return true; 622239462Sdim return false; 623239462Sdim} 624198090Srdivacky 625239462Sdim/// Is32BitMemOperand - Return true if the specified instruction has 626239462Sdim/// a 32-bit memory operand. Op specifies the operand # of the memoperand. 627239462Sdimstatic bool Is32BitMemOperand(const MachineInstr &MI, unsigned Op) { 628239462Sdim const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 629239462Sdim const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 630193323Sed 631239462Sdim if ((BaseReg.getReg() != 0 && 632239462Sdim X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 633239462Sdim (IndexReg.getReg() != 0 && 634239462Sdim X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 635239462Sdim return true; 636239462Sdim return false; 637239462Sdim} 638239462Sdim 639239462Sdim/// Is64BitMemOperand - Return true if the specified instruction has 640239462Sdim/// a 64-bit memory operand. Op specifies the operand # of the memoperand. 641239462Sdim#ifndef NDEBUG 642239462Sdimstatic bool Is64BitMemOperand(const MachineInstr &MI, unsigned Op) { 643239462Sdim const MachineOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); 644239462Sdim const MachineOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); 645239462Sdim 646239462Sdim if ((BaseReg.getReg() != 0 && 647239462Sdim X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 648239462Sdim (IndexReg.getReg() != 0 && 649239462Sdim X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) 650239462Sdim return true; 651239462Sdim return false; 652239462Sdim} 653239462Sdim#endif 654239462Sdim 655239462Sdimtemplate<class CodeEmitter> 656239462Sdimvoid Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags, 657239462Sdim int MemOperand, 658239462Sdim const MachineInstr &MI, 659239462Sdim const MCInstrDesc *Desc) const { 660193323Sed // Emit the lock opcode prefix as needed. 661198090Srdivacky if (Desc->TSFlags & X86II::LOCK) 662198090Srdivacky MCE.emitByte(0xF0); 663193323Sed 664193323Sed // Emit segment override opcode prefix as needed. 665239462Sdim emitSegmentOverridePrefix(TSFlags, MemOperand, MI); 666193323Sed 667193323Sed // Emit the repeat opcode prefix as needed. 668198090Srdivacky if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) 669198090Srdivacky MCE.emitByte(0xF3); 670193323Sed 671239462Sdim // Emit the address size opcode prefix as needed. 672239462Sdim bool need_address_override; 673239462Sdim if (TSFlags & X86II::AdSize) { 674239462Sdim need_address_override = true; 675239462Sdim } else if (MemOperand == -1) { 676239462Sdim need_address_override = false; 677239462Sdim } else if (Is64BitMode) { 678239462Sdim assert(!Is16BitMemOperand(MI, MemOperand)); 679239462Sdim need_address_override = Is32BitMemOperand(MI, MemOperand); 680239462Sdim } else { 681239462Sdim assert(!Is64BitMemOperand(MI, MemOperand)); 682239462Sdim need_address_override = Is16BitMemOperand(MI, MemOperand); 683239462Sdim } 684239462Sdim 685239462Sdim if (need_address_override) 686239462Sdim MCE.emitByte(0x67); 687239462Sdim 688193323Sed // Emit the operand size opcode prefix as needed. 689239462Sdim if (TSFlags & X86II::OpSize) 690198090Srdivacky MCE.emitByte(0x66); 691193323Sed 692193323Sed bool Need0FPrefix = false; 693193323Sed switch (Desc->TSFlags & X86II::Op0Mask) { 694239462Sdim case X86II::TB: // Two-byte opcode prefix 695239462Sdim case X86II::T8: // 0F 38 696239462Sdim case X86II::TA: // 0F 3A 697239462Sdim case X86II::A6: // 0F A6 698239462Sdim case X86II::A7: // 0F A7 699239462Sdim Need0FPrefix = true; 700239462Sdim break; 701239462Sdim case X86II::REP: break; // already handled. 702239462Sdim case X86II::T8XS: // F3 0F 38 703239462Sdim case X86II::XS: // F3 0F 704239462Sdim MCE.emitByte(0xF3); 705239462Sdim Need0FPrefix = true; 706239462Sdim break; 707239462Sdim case X86II::T8XD: // F2 0F 38 708239462Sdim case X86II::TAXD: // F2 0F 3A 709239462Sdim case X86II::XD: // F2 0F 710239462Sdim MCE.emitByte(0xF2); 711239462Sdim Need0FPrefix = true; 712239462Sdim break; 713239462Sdim case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: 714239462Sdim case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: 715239462Sdim MCE.emitByte(0xD8+ 716239462Sdim (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8) 717239462Sdim >> X86II::Op0Shift)); 718239462Sdim break; // Two-byte opcode prefix 719239462Sdim default: llvm_unreachable("Invalid prefix!"); 720239462Sdim case 0: break; // No prefix! 721193323Sed } 722193323Sed 723198090Srdivacky // Handle REX prefix. 724193323Sed if (Is64BitMode) { 725212904Sdim if (unsigned REX = determineREX(MI)) 726193323Sed MCE.emitByte(0x40 | REX); 727193323Sed } 728193323Sed 729193323Sed // 0x0F escape code must be emitted just before the opcode. 730193323Sed if (Need0FPrefix) 731193323Sed MCE.emitByte(0x0F); 732193323Sed 733193323Sed switch (Desc->TSFlags & X86II::Op0Mask) { 734239462Sdim case X86II::T8XD: // F2 0F 38 735239462Sdim case X86II::T8XS: // F3 0F 38 736239462Sdim case X86II::T8: // 0F 38 737239462Sdim MCE.emitByte(0x38); 738239462Sdim break; 739239462Sdim case X86II::TAXD: // F2 0F 38 740239462Sdim case X86II::TA: // 0F 3A 741239462Sdim MCE.emitByte(0x3A); 742239462Sdim break; 743239462Sdim case X86II::A6: // 0F A6 744239462Sdim MCE.emitByte(0xA6); 745239462Sdim break; 746239462Sdim case X86II::A7: // 0F A7 747239462Sdim MCE.emitByte(0xA7); 748239462Sdim break; 749193323Sed } 750239462Sdim} 751193323Sed 752239462Sdim// On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range 753239462Sdim// 0-7 and the difference between the 2 groups is given by the REX prefix. 754239462Sdim// In the VEX prefix, registers are seen sequencially from 0-15 and encoded 755239462Sdim// in 1's complement form, example: 756239462Sdim// 757239462Sdim// ModRM field => XMM9 => 1 758239462Sdim// VEX.VVVV => XMM9 => ~9 759239462Sdim// 760239462Sdim// See table 4-35 of Intel AVX Programming Reference for details. 761239462Sdimstatic unsigned char getVEXRegisterEncoding(const MachineInstr &MI, 762239462Sdim unsigned OpNum) { 763239462Sdim unsigned SrcReg = MI.getOperand(OpNum).getReg(); 764239462Sdim unsigned SrcRegNum = X86_MC::getX86RegNum(MI.getOperand(OpNum).getReg()); 765239462Sdim if (X86II::isX86_64ExtendedReg(SrcReg)) 766239462Sdim SrcRegNum |= 8; 767239462Sdim 768239462Sdim // The registers represented through VEX_VVVV should 769239462Sdim // be encoded in 1's complement form. 770239462Sdim return (~SrcRegNum) & 0xf; 771239462Sdim} 772239462Sdim 773239462Sdim/// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed 774239462Sdimtemplate<class CodeEmitter> 775239462Sdimvoid Emitter<CodeEmitter>::emitSegmentOverridePrefix(uint64_t TSFlags, 776239462Sdim int MemOperand, 777239462Sdim const MachineInstr &MI) const { 778239462Sdim switch (TSFlags & X86II::SegOvrMask) { 779239462Sdim default: llvm_unreachable("Invalid segment!"); 780239462Sdim case 0: 781239462Sdim // No segment override, check for explicit one on memory operand. 782239462Sdim if (MemOperand != -1) { // If the instruction has a memory operand. 783239462Sdim switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { 784239462Sdim default: llvm_unreachable("Unknown segment register!"); 785239462Sdim case 0: break; 786239462Sdim case X86::CS: MCE.emitByte(0x2E); break; 787239462Sdim case X86::SS: MCE.emitByte(0x36); break; 788239462Sdim case X86::DS: MCE.emitByte(0x3E); break; 789239462Sdim case X86::ES: MCE.emitByte(0x26); break; 790239462Sdim case X86::FS: MCE.emitByte(0x64); break; 791239462Sdim case X86::GS: MCE.emitByte(0x65); break; 792239462Sdim } 793239462Sdim } 794239462Sdim break; 795239462Sdim case X86II::FS: 796239462Sdim MCE.emitByte(0x64); 797239462Sdim break; 798239462Sdim case X86II::GS: 799239462Sdim MCE.emitByte(0x65); 800239462Sdim break; 801239462Sdim } 802239462Sdim} 803239462Sdim 804239462Sdimtemplate<class CodeEmitter> 805239462Sdimvoid Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags, 806239462Sdim int MemOperand, 807239462Sdim const MachineInstr &MI, 808239462Sdim const MCInstrDesc *Desc) const { 809239462Sdim bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 810239462Sdim bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 811239462Sdim 812239462Sdim // VEX_R: opcode externsion equivalent to REX.R in 813239462Sdim // 1's complement (inverted) form 814239462Sdim // 815239462Sdim // 1: Same as REX_R=0 (must be 1 in 32-bit mode) 816239462Sdim // 0: Same as REX_R=1 (64 bit mode only) 817239462Sdim // 818239462Sdim unsigned char VEX_R = 0x1; 819239462Sdim 820239462Sdim // VEX_X: equivalent to REX.X, only used when a 821239462Sdim // register is used for index in SIB Byte. 822239462Sdim // 823239462Sdim // 1: Same as REX.X=0 (must be 1 in 32-bit mode) 824239462Sdim // 0: Same as REX.X=1 (64-bit mode only) 825239462Sdim unsigned char VEX_X = 0x1; 826239462Sdim 827239462Sdim // VEX_B: 828239462Sdim // 829239462Sdim // 1: Same as REX_B=0 (ignored in 32-bit mode) 830239462Sdim // 0: Same as REX_B=1 (64 bit mode only) 831239462Sdim // 832239462Sdim unsigned char VEX_B = 0x1; 833239462Sdim 834239462Sdim // VEX_W: opcode specific (use like REX.W, or used for 835239462Sdim // opcode extension, or ignored, depending on the opcode byte) 836239462Sdim unsigned char VEX_W = 0; 837239462Sdim 838239462Sdim // XOP: Use XOP prefix byte 0x8f instead of VEX. 839239462Sdim unsigned char XOP = 0; 840239462Sdim 841239462Sdim // VEX_5M (VEX m-mmmmm field): 842239462Sdim // 843239462Sdim // 0b00000: Reserved for future use 844239462Sdim // 0b00001: implied 0F leading opcode 845239462Sdim // 0b00010: implied 0F 38 leading opcode bytes 846239462Sdim // 0b00011: implied 0F 3A leading opcode bytes 847239462Sdim // 0b00100-0b11111: Reserved for future use 848239462Sdim // 0b01000: XOP map select - 08h instructions with imm byte 849239462Sdim // 0b10001: XOP map select - 09h instructions with no imm byte 850239462Sdim unsigned char VEX_5M = 0x1; 851239462Sdim 852239462Sdim // VEX_4V (VEX vvvv field): a register specifier 853239462Sdim // (in 1's complement form) or 1111 if unused. 854239462Sdim unsigned char VEX_4V = 0xf; 855239462Sdim 856239462Sdim // VEX_L (Vector Length): 857239462Sdim // 858239462Sdim // 0: scalar or 128-bit vector 859239462Sdim // 1: 256-bit vector 860239462Sdim // 861239462Sdim unsigned char VEX_L = 0; 862239462Sdim 863239462Sdim // VEX_PP: opcode extension providing equivalent 864239462Sdim // functionality of a SIMD prefix 865239462Sdim // 866239462Sdim // 0b00: None 867239462Sdim // 0b01: 66 868239462Sdim // 0b10: F3 869239462Sdim // 0b11: F2 870239462Sdim // 871239462Sdim unsigned char VEX_PP = 0; 872239462Sdim 873239462Sdim // Encode the operand size opcode prefix as needed. 874239462Sdim if (TSFlags & X86II::OpSize) 875239462Sdim VEX_PP = 0x01; 876239462Sdim 877239462Sdim if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W) 878239462Sdim VEX_W = 1; 879239462Sdim 880239462Sdim if ((TSFlags >> X86II::VEXShift) & X86II::XOP) 881239462Sdim XOP = 1; 882239462Sdim 883239462Sdim if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L) 884239462Sdim VEX_L = 1; 885239462Sdim 886239462Sdim switch (TSFlags & X86II::Op0Mask) { 887239462Sdim default: llvm_unreachable("Invalid prefix!"); 888239462Sdim case X86II::T8: // 0F 38 889239462Sdim VEX_5M = 0x2; 890239462Sdim break; 891239462Sdim case X86II::TA: // 0F 3A 892239462Sdim VEX_5M = 0x3; 893239462Sdim break; 894239462Sdim case X86II::T8XS: // F3 0F 38 895239462Sdim VEX_PP = 0x2; 896239462Sdim VEX_5M = 0x2; 897239462Sdim break; 898239462Sdim case X86II::T8XD: // F2 0F 38 899239462Sdim VEX_PP = 0x3; 900239462Sdim VEX_5M = 0x2; 901239462Sdim break; 902239462Sdim case X86II::TAXD: // F2 0F 3A 903239462Sdim VEX_PP = 0x3; 904239462Sdim VEX_5M = 0x3; 905239462Sdim break; 906239462Sdim case X86II::XS: // F3 0F 907239462Sdim VEX_PP = 0x2; 908239462Sdim break; 909239462Sdim case X86II::XD: // F2 0F 910239462Sdim VEX_PP = 0x3; 911239462Sdim break; 912239462Sdim case X86II::XOP8: 913239462Sdim VEX_5M = 0x8; 914239462Sdim break; 915239462Sdim case X86II::XOP9: 916239462Sdim VEX_5M = 0x9; 917239462Sdim break; 918239462Sdim case X86II::A6: // Bypass: Not used by VEX 919239462Sdim case X86II::A7: // Bypass: Not used by VEX 920239462Sdim case X86II::TB: // Bypass: Not used by VEX 921239462Sdim case 0: 922239462Sdim break; // No prefix! 923239462Sdim } 924239462Sdim 925239462Sdim 926239462Sdim // Set the vector length to 256-bit if YMM0-YMM15 is used 927239462Sdim for (unsigned i = 0; i != MI.getNumOperands(); ++i) { 928239462Sdim if (!MI.getOperand(i).isReg()) 929239462Sdim continue; 930239462Sdim if (MI.getOperand(i).isImplicit()) 931239462Sdim continue; 932239462Sdim unsigned SrcReg = MI.getOperand(i).getReg(); 933239462Sdim if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15) 934239462Sdim VEX_L = 1; 935239462Sdim } 936239462Sdim 937239462Sdim // Classify VEX_B, VEX_4V, VEX_R, VEX_X 938239462Sdim unsigned NumOps = Desc->getNumOperands(); 939239462Sdim unsigned CurOp = 0; 940239462Sdim if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) == 0) 941239462Sdim ++CurOp; 942239462Sdim else if (NumOps > 3 && Desc->getOperandConstraint(2, MCOI::TIED_TO) == 0) { 943239462Sdim assert(Desc->getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1); 944239462Sdim // Special case for GATHER with 2 TIED_TO operands 945239462Sdim // Skip the first 2 operands: dst, mask_wb 946239462Sdim CurOp += 2; 947239462Sdim } 948239462Sdim 949239462Sdim switch (TSFlags & X86II::FormMask) { 950239462Sdim case X86II::MRMInitReg: 951239462Sdim // Duplicate register. 952239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 953239462Sdim VEX_R = 0x0; 954239462Sdim 955239462Sdim if (HasVEX_4V) 956239462Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp); 957239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 958239462Sdim VEX_B = 0x0; 959239462Sdim if (HasVEX_4VOp3) 960239462Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp); 961239462Sdim break; 962239462Sdim case X86II::MRMDestMem: { 963239462Sdim // MRMDestMem instructions forms: 964239462Sdim // MemAddr, src1(ModR/M) 965239462Sdim // MemAddr, src1(VEX_4V), src2(ModR/M) 966239462Sdim // MemAddr, src1(ModR/M), imm8 967239462Sdim // 968239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrBaseReg).getReg())) 969239462Sdim VEX_B = 0x0; 970239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(X86::AddrIndexReg).getReg())) 971239462Sdim VEX_X = 0x0; 972239462Sdim 973239462Sdim CurOp = X86::AddrNumOperands; 974239462Sdim if (HasVEX_4V) 975239462Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 976239462Sdim 977239462Sdim const MachineOperand &MO = MI.getOperand(CurOp); 978239462Sdim if (MO.isReg() && X86II::isX86_64ExtendedReg(MO.getReg())) 979239462Sdim VEX_R = 0x0; 980239462Sdim break; 981239462Sdim } 982239462Sdim case X86II::MRMSrcMem: 983239462Sdim // MRMSrcMem instructions forms: 984239462Sdim // src1(ModR/M), MemAddr 985239462Sdim // src1(ModR/M), src2(VEX_4V), MemAddr 986239462Sdim // src1(ModR/M), MemAddr, imm8 987239462Sdim // src1(ModR/M), MemAddr, src2(VEX_I8IMM) 988239462Sdim // 989239462Sdim // FMA4: 990239462Sdim // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 991239462Sdim // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), 992239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 993239462Sdim VEX_R = 0x0; 994239462Sdim 995239462Sdim if (HasVEX_4V) 996239462Sdim VEX_4V = getVEXRegisterEncoding(MI, 1); 997239462Sdim 998239462Sdim if (X86II::isX86_64ExtendedReg( 999239462Sdim MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 1000239462Sdim VEX_B = 0x0; 1001239462Sdim if (X86II::isX86_64ExtendedReg( 1002239462Sdim MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 1003239462Sdim VEX_X = 0x0; 1004239462Sdim 1005239462Sdim if (HasVEX_4VOp3) 1006239462Sdim VEX_4V = getVEXRegisterEncoding(MI, X86::AddrNumOperands+1); 1007239462Sdim break; 1008239462Sdim case X86II::MRM0m: case X86II::MRM1m: 1009239462Sdim case X86II::MRM2m: case X86II::MRM3m: 1010239462Sdim case X86II::MRM4m: case X86II::MRM5m: 1011239462Sdim case X86II::MRM6m: case X86II::MRM7m: { 1012239462Sdim // MRM[0-9]m instructions forms: 1013239462Sdim // MemAddr 1014239462Sdim // src1(VEX_4V), MemAddr 1015239462Sdim if (HasVEX_4V) 1016239462Sdim VEX_4V = getVEXRegisterEncoding(MI, 0); 1017239462Sdim 1018239462Sdim if (X86II::isX86_64ExtendedReg( 1019239462Sdim MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) 1020239462Sdim VEX_B = 0x0; 1021239462Sdim if (X86II::isX86_64ExtendedReg( 1022239462Sdim MI.getOperand(MemOperand+X86::AddrIndexReg).getReg())) 1023239462Sdim VEX_X = 0x0; 1024239462Sdim break; 1025239462Sdim } 1026239462Sdim case X86II::MRMSrcReg: 1027239462Sdim // MRMSrcReg instructions forms: 1028239462Sdim // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) 1029239462Sdim // dst(ModR/M), src1(ModR/M) 1030239462Sdim // dst(ModR/M), src1(ModR/M), imm8 1031239462Sdim // 1032239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 1033239462Sdim VEX_R = 0x0; 1034239462Sdim CurOp++; 1035239462Sdim 1036239462Sdim if (HasVEX_4V) 1037239462Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp++); 1038239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) 1039239462Sdim VEX_B = 0x0; 1040239462Sdim CurOp++; 1041239462Sdim if (HasVEX_4VOp3) 1042239462Sdim VEX_4V = getVEXRegisterEncoding(MI, CurOp); 1043239462Sdim break; 1044239462Sdim case X86II::MRMDestReg: 1045239462Sdim // MRMDestReg instructions forms: 1046239462Sdim // dst(ModR/M), src(ModR/M) 1047239462Sdim // dst(ModR/M), src(ModR/M), imm8 1048239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) 1049239462Sdim VEX_B = 0x0; 1050239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg())) 1051239462Sdim VEX_R = 0x0; 1052239462Sdim break; 1053239462Sdim case X86II::MRM0r: case X86II::MRM1r: 1054239462Sdim case X86II::MRM2r: case X86II::MRM3r: 1055239462Sdim case X86II::MRM4r: case X86II::MRM5r: 1056239462Sdim case X86II::MRM6r: case X86II::MRM7r: 1057239462Sdim // MRM0r-MRM7r instructions forms: 1058239462Sdim // dst(VEX_4V), src(ModR/M), imm8 1059239462Sdim VEX_4V = getVEXRegisterEncoding(MI, 0); 1060239462Sdim if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg())) 1061239462Sdim VEX_B = 0x0; 1062239462Sdim break; 1063239462Sdim default: // RawFrm 1064239462Sdim break; 1065239462Sdim } 1066239462Sdim 1067239462Sdim // Emit segment override opcode prefix as needed. 1068239462Sdim emitSegmentOverridePrefix(TSFlags, MemOperand, MI); 1069239462Sdim 1070239462Sdim // VEX opcode prefix can have 2 or 3 bytes 1071239462Sdim // 1072239462Sdim // 3 bytes: 1073239462Sdim // +-----+ +--------------+ +-------------------+ 1074239462Sdim // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | 1075239462Sdim // +-----+ +--------------+ +-------------------+ 1076239462Sdim // 2 bytes: 1077239462Sdim // +-----+ +-------------------+ 1078239462Sdim // | C5h | | R | vvvv | L | pp | 1079239462Sdim // +-----+ +-------------------+ 1080239462Sdim // 1081239462Sdim unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); 1082239462Sdim 1083239462Sdim if (VEX_B && VEX_X && !VEX_W && !XOP && (VEX_5M == 1)) { // 2 byte VEX prefix 1084239462Sdim MCE.emitByte(0xC5); 1085239462Sdim MCE.emitByte(LastByte | (VEX_R << 7)); 1086239462Sdim return; 1087239462Sdim } 1088239462Sdim 1089239462Sdim // 3 byte VEX prefix 1090239462Sdim MCE.emitByte(XOP ? 0x8F : 0xC4); 1091239462Sdim MCE.emitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M); 1092239462Sdim MCE.emitByte(LastByte | (VEX_W << 7)); 1093239462Sdim} 1094239462Sdim 1095239462Sdimtemplate<class CodeEmitter> 1096239462Sdimvoid Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI, 1097239462Sdim const MCInstrDesc *Desc) { 1098239462Sdim DEBUG(dbgs() << MI); 1099239462Sdim 1100239462Sdim // If this is a pseudo instruction, lower it. 1101239462Sdim switch (Desc->getOpcode()) { 1102239462Sdim case X86::ADD16rr_DB: Desc = UpdateOp(MI, II, X86::OR16rr); break; 1103239462Sdim case X86::ADD32rr_DB: Desc = UpdateOp(MI, II, X86::OR32rr); break; 1104239462Sdim case X86::ADD64rr_DB: Desc = UpdateOp(MI, II, X86::OR64rr); break; 1105239462Sdim case X86::ADD16ri_DB: Desc = UpdateOp(MI, II, X86::OR16ri); break; 1106239462Sdim case X86::ADD32ri_DB: Desc = UpdateOp(MI, II, X86::OR32ri); break; 1107239462Sdim case X86::ADD64ri32_DB: Desc = UpdateOp(MI, II, X86::OR64ri32); break; 1108239462Sdim case X86::ADD16ri8_DB: Desc = UpdateOp(MI, II, X86::OR16ri8); break; 1109239462Sdim case X86::ADD32ri8_DB: Desc = UpdateOp(MI, II, X86::OR32ri8); break; 1110239462Sdim case X86::ADD64ri8_DB: Desc = UpdateOp(MI, II, X86::OR64ri8); break; 1111239462Sdim case X86::ACQUIRE_MOV8rm: Desc = UpdateOp(MI, II, X86::MOV8rm); break; 1112239462Sdim case X86::ACQUIRE_MOV16rm: Desc = UpdateOp(MI, II, X86::MOV16rm); break; 1113239462Sdim case X86::ACQUIRE_MOV32rm: Desc = UpdateOp(MI, II, X86::MOV32rm); break; 1114239462Sdim case X86::ACQUIRE_MOV64rm: Desc = UpdateOp(MI, II, X86::MOV64rm); break; 1115239462Sdim case X86::RELEASE_MOV8mr: Desc = UpdateOp(MI, II, X86::MOV8mr); break; 1116239462Sdim case X86::RELEASE_MOV16mr: Desc = UpdateOp(MI, II, X86::MOV16mr); break; 1117239462Sdim case X86::RELEASE_MOV32mr: Desc = UpdateOp(MI, II, X86::MOV32mr); break; 1118239462Sdim case X86::RELEASE_MOV64mr: Desc = UpdateOp(MI, II, X86::MOV64mr); break; 1119239462Sdim } 1120239462Sdim 1121239462Sdim 1122239462Sdim MCE.processDebugLoc(MI.getDebugLoc(), true); 1123239462Sdim 1124239462Sdim unsigned Opcode = Desc->Opcode; 1125239462Sdim 1126193323Sed // If this is a two-address instruction, skip one of the register operands. 1127193323Sed unsigned NumOps = Desc->getNumOperands(); 1128193323Sed unsigned CurOp = 0; 1129239462Sdim if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) == 0) 1130193323Sed ++CurOp; 1131239462Sdim else if (NumOps > 3 && Desc->getOperandConstraint(2, MCOI::TIED_TO) == 0) { 1132239462Sdim assert(Desc->getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1); 1133239462Sdim // Special case for GATHER with 2 TIED_TO operands 1134239462Sdim // Skip the first 2 operands: dst, mask_wb 1135239462Sdim CurOp += 2; 1136239462Sdim } 1137193323Sed 1138239462Sdim uint64_t TSFlags = Desc->TSFlags; 1139239462Sdim 1140239462Sdim // Is this instruction encoded using the AVX VEX prefix? 1141239462Sdim bool HasVEXPrefix = (TSFlags >> X86II::VEXShift) & X86II::VEX; 1142239462Sdim // It uses the VEX.VVVV field? 1143239462Sdim bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; 1144239462Sdim bool HasVEX_4VOp3 = (TSFlags >> X86II::VEXShift) & X86II::VEX_4VOp3; 1145239462Sdim bool HasMemOp4 = (TSFlags >> X86II::VEXShift) & X86II::MemOp4; 1146239462Sdim const unsigned MemOp4_I8IMMOperand = 2; 1147239462Sdim 1148239462Sdim // Determine where the memory operand starts, if present. 1149239462Sdim int MemoryOperand = X86II::getMemoryOperandNo(TSFlags, Opcode); 1150239462Sdim if (MemoryOperand != -1) MemoryOperand += CurOp; 1151239462Sdim 1152239462Sdim if (!HasVEXPrefix) 1153239462Sdim emitOpcodePrefix(TSFlags, MemoryOperand, MI, Desc); 1154239462Sdim else 1155239462Sdim emitVEXOpcodePrefix(TSFlags, MemoryOperand, MI, Desc); 1156239462Sdim 1157203954Srdivacky unsigned char BaseOpcode = X86II::getBaseOpcodeFor(Desc->TSFlags); 1158239462Sdim switch (TSFlags & X86II::FormMask) { 1159198090Srdivacky default: 1160198090Srdivacky llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!"); 1161193323Sed case X86II::Pseudo: 1162193323Sed // Remember the current PC offset, this is the PIC relocation 1163193323Sed // base address. 1164193323Sed switch (Opcode) { 1165239462Sdim default: 1166212904Sdim llvm_unreachable("pseudo instructions should be removed before code" 1167198090Srdivacky " emission"); 1168212904Sdim // Do nothing for Int_MemBarrier - it's just a comment. Add a debug 1169212904Sdim // to make it slightly easier to see. 1170212904Sdim case X86::Int_MemBarrier: 1171212904Sdim DEBUG(dbgs() << "#MEMBARRIER\n"); 1172212904Sdim break; 1173239462Sdim 1174203954Srdivacky case TargetOpcode::INLINEASM: 1175193323Sed // We allow inline assembler nodes with empty bodies - they can 1176193323Sed // implicitly define registers, which is ok for JIT. 1177198090Srdivacky if (MI.getOperand(0).getSymbolName()[0]) 1178207618Srdivacky report_fatal_error("JIT does not support inline asm!"); 1179193323Sed break; 1180212904Sdim case TargetOpcode::PROLOG_LABEL: 1181205218Srdivacky case TargetOpcode::GC_LABEL: 1182203954Srdivacky case TargetOpcode::EH_LABEL: 1183205218Srdivacky MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 1184193323Sed break; 1185239462Sdim 1186203954Srdivacky case TargetOpcode::IMPLICIT_DEF: 1187203954Srdivacky case TargetOpcode::KILL: 1188193323Sed break; 1189193323Sed case X86::MOVPC32r: { 1190193323Sed // This emits the "call" portion of this pseudo instruction. 1191193323Sed MCE.emitByte(BaseOpcode); 1192203954Srdivacky emitConstant(0, X86II::getSizeOfImm(Desc->TSFlags)); 1193193323Sed // Remember PIC base. 1194193323Sed PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset(); 1195193323Sed X86JITInfo *JTI = TM.getJITInfo(); 1196193323Sed JTI->setPICBase(MCE.getCurrentPCValue()); 1197193323Sed break; 1198193323Sed } 1199193323Sed } 1200193323Sed CurOp = NumOps; 1201193323Sed break; 1202198090Srdivacky case X86II::RawFrm: { 1203193323Sed MCE.emitByte(BaseOpcode); 1204193323Sed 1205198090Srdivacky if (CurOp == NumOps) 1206198090Srdivacky break; 1207239462Sdim 1208198090Srdivacky const MachineOperand &MO = MI.getOperand(CurOp++); 1209193323Sed 1210202375Srdivacky DEBUG(dbgs() << "RawFrm CurOp " << CurOp << "\n"); 1211202375Srdivacky DEBUG(dbgs() << "isMBB " << MO.isMBB() << "\n"); 1212202375Srdivacky DEBUG(dbgs() << "isGlobal " << MO.isGlobal() << "\n"); 1213202375Srdivacky DEBUG(dbgs() << "isSymbol " << MO.isSymbol() << "\n"); 1214202375Srdivacky DEBUG(dbgs() << "isImm " << MO.isImm() << "\n"); 1215193323Sed 1216198090Srdivacky if (MO.isMBB()) { 1217198090Srdivacky emitPCRelativeBlockAddress(MO.getMBB()); 1218198090Srdivacky break; 1219193323Sed } 1220239462Sdim 1221198090Srdivacky if (MO.isGlobal()) { 1222198090Srdivacky emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word, 1223199481Srdivacky MO.getOffset(), 0); 1224198090Srdivacky break; 1225198090Srdivacky } 1226239462Sdim 1227198090Srdivacky if (MO.isSymbol()) { 1228198090Srdivacky emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word); 1229198090Srdivacky break; 1230198090Srdivacky } 1231203954Srdivacky 1232203954Srdivacky // FIXME: Only used by hackish MCCodeEmitter, remove when dead. 1233203954Srdivacky if (MO.isJTI()) { 1234203954Srdivacky emitJumpTableAddress(MO.getIndex(), X86::reloc_pcrel_word); 1235203954Srdivacky break; 1236203954Srdivacky } 1237239462Sdim 1238198090Srdivacky assert(MO.isImm() && "Unknown RawFrm operand!"); 1239234353Sdim if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32) { 1240198090Srdivacky // Fix up immediate operand for pc relative calls. 1241198090Srdivacky intptr_t Imm = (intptr_t)MO.getImm(); 1242198090Srdivacky Imm = Imm - MCE.getCurrentPCValue() - 4; 1243203954Srdivacky emitConstant(Imm, X86II::getSizeOfImm(Desc->TSFlags)); 1244198090Srdivacky } else 1245203954Srdivacky emitConstant(MO.getImm(), X86II::getSizeOfImm(Desc->TSFlags)); 1246193323Sed break; 1247198090Srdivacky } 1248239462Sdim 1249198090Srdivacky case X86II::AddRegFrm: { 1250226633Sdim MCE.emitByte(BaseOpcode + 1251226633Sdim X86_MC::getX86RegNum(MI.getOperand(CurOp++).getReg())); 1252239462Sdim 1253198090Srdivacky if (CurOp == NumOps) 1254198090Srdivacky break; 1255239462Sdim 1256198090Srdivacky const MachineOperand &MO1 = MI.getOperand(CurOp++); 1257203954Srdivacky unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 1258198090Srdivacky if (MO1.isImm()) { 1259198090Srdivacky emitConstant(MO1.getImm(), Size); 1260198090Srdivacky break; 1261193323Sed } 1262239462Sdim 1263198090Srdivacky unsigned rt = Is64BitMode ? X86::reloc_pcrel_word 1264198090Srdivacky : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 1265198090Srdivacky if (Opcode == X86::MOV64ri64i32) 1266198090Srdivacky rt = X86::reloc_absolute_word; // FIXME: add X86II flag? 1267198090Srdivacky // This should not occur on Darwin for relocatable objects. 1268198090Srdivacky if (Opcode == X86::MOV64ri) 1269198090Srdivacky rt = X86::reloc_absolute_dword; // FIXME: add X86II flag? 1270198090Srdivacky if (MO1.isGlobal()) { 1271198090Srdivacky bool Indirect = gvNeedsNonLazyPtr(MO1, TM); 1272198090Srdivacky emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, 1273199481Srdivacky Indirect); 1274198090Srdivacky } else if (MO1.isSymbol()) 1275198090Srdivacky emitExternalSymbolAddress(MO1.getSymbolName(), rt); 1276198090Srdivacky else if (MO1.isCPI()) 1277198090Srdivacky emitConstPoolAddress(MO1.getIndex(), rt); 1278198090Srdivacky else if (MO1.isJTI()) 1279198090Srdivacky emitJumpTableAddress(MO1.getIndex(), rt); 1280193323Sed break; 1281198090Srdivacky } 1282193323Sed 1283193323Sed case X86II::MRMDestReg: { 1284193323Sed MCE.emitByte(BaseOpcode); 1285193323Sed emitRegModRMByte(MI.getOperand(CurOp).getReg(), 1286226633Sdim X86_MC::getX86RegNum(MI.getOperand(CurOp+1).getReg())); 1287193323Sed CurOp += 2; 1288193323Sed break; 1289193323Sed } 1290193323Sed case X86II::MRMDestMem: { 1291193323Sed MCE.emitByte(BaseOpcode); 1292239462Sdim 1293239462Sdim unsigned SrcRegNum = CurOp + X86::AddrNumOperands; 1294239462Sdim if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1295239462Sdim SrcRegNum++; 1296193323Sed emitMemModRMByte(MI, CurOp, 1297239462Sdim X86_MC::getX86RegNum(MI.getOperand(SrcRegNum).getReg())); 1298239462Sdim CurOp = SrcRegNum + 1; 1299193323Sed break; 1300193323Sed } 1301193323Sed 1302239462Sdim case X86II::MRMSrcReg: { 1303193323Sed MCE.emitByte(BaseOpcode); 1304239462Sdim 1305239462Sdim unsigned SrcRegNum = CurOp+1; 1306239462Sdim if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1307239462Sdim ++SrcRegNum; 1308239462Sdim 1309239462Sdim if (HasMemOp4) // Skip 2nd src (which is encoded in I8IMM) 1310239462Sdim ++SrcRegNum; 1311239462Sdim 1312239462Sdim emitRegModRMByte(MI.getOperand(SrcRegNum).getReg(), 1313226633Sdim X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg())); 1314239462Sdim // 2 operands skipped with HasMemOp4, compensate accordingly 1315239462Sdim CurOp = HasMemOp4 ? SrcRegNum : SrcRegNum + 1; 1316239462Sdim if (HasVEX_4VOp3) 1317239462Sdim ++CurOp; 1318193323Sed break; 1319239462Sdim } 1320193323Sed case X86II::MRMSrcMem: { 1321210299Sed int AddrOperands = X86::AddrNumOperands; 1322239462Sdim unsigned FirstMemOp = CurOp+1; 1323239462Sdim if (HasVEX_4V) { 1324239462Sdim ++AddrOperands; 1325239462Sdim ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1326239462Sdim } 1327239462Sdim if (HasMemOp4) // Skip second register source (encoded in I8IMM) 1328239462Sdim ++FirstMemOp; 1329193323Sed 1330239462Sdim MCE.emitByte(BaseOpcode); 1331239462Sdim 1332193323Sed intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ? 1333203954Srdivacky X86II::getSizeOfImm(Desc->TSFlags) : 0; 1334239462Sdim emitMemModRMByte(MI, FirstMemOp, 1335226633Sdim X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj); 1336193323Sed CurOp += AddrOperands + 1; 1337239462Sdim if (HasVEX_4VOp3) 1338239462Sdim ++CurOp; 1339193323Sed break; 1340193323Sed } 1341193323Sed 1342193323Sed case X86II::MRM0r: case X86II::MRM1r: 1343193323Sed case X86II::MRM2r: case X86II::MRM3r: 1344193323Sed case X86II::MRM4r: case X86II::MRM5r: 1345193323Sed case X86II::MRM6r: case X86II::MRM7r: { 1346239462Sdim if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1347239462Sdim ++CurOp; 1348193323Sed MCE.emitByte(BaseOpcode); 1349203954Srdivacky emitRegModRMByte(MI.getOperand(CurOp++).getReg(), 1350203954Srdivacky (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r); 1351193323Sed 1352198090Srdivacky if (CurOp == NumOps) 1353198090Srdivacky break; 1354239462Sdim 1355198090Srdivacky const MachineOperand &MO1 = MI.getOperand(CurOp++); 1356203954Srdivacky unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 1357198090Srdivacky if (MO1.isImm()) { 1358198090Srdivacky emitConstant(MO1.getImm(), Size); 1359198090Srdivacky break; 1360193323Sed } 1361239462Sdim 1362198090Srdivacky unsigned rt = Is64BitMode ? X86::reloc_pcrel_word 1363198090Srdivacky : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 1364198090Srdivacky if (Opcode == X86::MOV64ri32) 1365198090Srdivacky rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag? 1366198090Srdivacky if (MO1.isGlobal()) { 1367198090Srdivacky bool Indirect = gvNeedsNonLazyPtr(MO1, TM); 1368198090Srdivacky emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, 1369199481Srdivacky Indirect); 1370198090Srdivacky } else if (MO1.isSymbol()) 1371198090Srdivacky emitExternalSymbolAddress(MO1.getSymbolName(), rt); 1372198090Srdivacky else if (MO1.isCPI()) 1373198090Srdivacky emitConstPoolAddress(MO1.getIndex(), rt); 1374198090Srdivacky else if (MO1.isJTI()) 1375198090Srdivacky emitJumpTableAddress(MO1.getIndex(), rt); 1376193323Sed break; 1377193323Sed } 1378193323Sed 1379193323Sed case X86II::MRM0m: case X86II::MRM1m: 1380193323Sed case X86II::MRM2m: case X86II::MRM3m: 1381193323Sed case X86II::MRM4m: case X86II::MRM5m: 1382193323Sed case X86II::MRM6m: case X86II::MRM7m: { 1383239462Sdim if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1384239462Sdim ++CurOp; 1385210299Sed intptr_t PCAdj = (CurOp + X86::AddrNumOperands != NumOps) ? 1386239462Sdim (MI.getOperand(CurOp+X86::AddrNumOperands).isImm() ? 1387203954Srdivacky X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0; 1388193323Sed 1389193323Sed MCE.emitByte(BaseOpcode); 1390193323Sed emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m, 1391193323Sed PCAdj); 1392210299Sed CurOp += X86::AddrNumOperands; 1393193323Sed 1394198090Srdivacky if (CurOp == NumOps) 1395198090Srdivacky break; 1396239462Sdim 1397198090Srdivacky const MachineOperand &MO = MI.getOperand(CurOp++); 1398203954Srdivacky unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 1399198090Srdivacky if (MO.isImm()) { 1400198090Srdivacky emitConstant(MO.getImm(), Size); 1401198090Srdivacky break; 1402193323Sed } 1403239462Sdim 1404198090Srdivacky unsigned rt = Is64BitMode ? X86::reloc_pcrel_word 1405198090Srdivacky : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 1406198090Srdivacky if (Opcode == X86::MOV64mi32) 1407198090Srdivacky rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag? 1408198090Srdivacky if (MO.isGlobal()) { 1409198090Srdivacky bool Indirect = gvNeedsNonLazyPtr(MO, TM); 1410198090Srdivacky emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0, 1411199481Srdivacky Indirect); 1412198090Srdivacky } else if (MO.isSymbol()) 1413198090Srdivacky emitExternalSymbolAddress(MO.getSymbolName(), rt); 1414198090Srdivacky else if (MO.isCPI()) 1415198090Srdivacky emitConstPoolAddress(MO.getIndex(), rt); 1416198090Srdivacky else if (MO.isJTI()) 1417198090Srdivacky emitJumpTableAddress(MO.getIndex(), rt); 1418193323Sed break; 1419193323Sed } 1420193323Sed 1421193323Sed case X86II::MRMInitReg: 1422193323Sed MCE.emitByte(BaseOpcode); 1423193323Sed // Duplicate register, used by things like MOV8r0 (aka xor reg,reg). 1424193323Sed emitRegModRMByte(MI.getOperand(CurOp).getReg(), 1425226633Sdim X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg())); 1426193323Sed ++CurOp; 1427193323Sed break; 1428239462Sdim 1429203954Srdivacky case X86II::MRM_C1: 1430203954Srdivacky MCE.emitByte(BaseOpcode); 1431203954Srdivacky MCE.emitByte(0xC1); 1432203954Srdivacky break; 1433203954Srdivacky case X86II::MRM_C8: 1434203954Srdivacky MCE.emitByte(BaseOpcode); 1435203954Srdivacky MCE.emitByte(0xC8); 1436203954Srdivacky break; 1437203954Srdivacky case X86II::MRM_C9: 1438203954Srdivacky MCE.emitByte(BaseOpcode); 1439203954Srdivacky MCE.emitByte(0xC9); 1440203954Srdivacky break; 1441203954Srdivacky case X86II::MRM_E8: 1442203954Srdivacky MCE.emitByte(BaseOpcode); 1443203954Srdivacky MCE.emitByte(0xE8); 1444203954Srdivacky break; 1445203954Srdivacky case X86II::MRM_F0: 1446203954Srdivacky MCE.emitByte(BaseOpcode); 1447203954Srdivacky MCE.emitByte(0xF0); 1448203954Srdivacky break; 1449193323Sed } 1450193323Sed 1451239462Sdim while (CurOp != NumOps && NumOps - CurOp <= 2) { 1452239462Sdim // The last source register of a 4 operand instruction in AVX is encoded 1453239462Sdim // in bits[7:4] of a immediate byte. 1454239462Sdim if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) { 1455239462Sdim const MachineOperand &MO = MI.getOperand(HasMemOp4 ? MemOp4_I8IMMOperand 1456239462Sdim : CurOp); 1457239462Sdim ++CurOp; 1458239462Sdim unsigned RegNum = X86_MC::getX86RegNum(MO.getReg()) << 4; 1459239462Sdim if (X86II::isX86_64ExtendedReg(MO.getReg())) 1460239462Sdim RegNum |= 1 << 7; 1461239462Sdim // If there is an additional 5th operand it must be an immediate, which 1462239462Sdim // is encoded in bits[3:0] 1463239462Sdim if (CurOp != NumOps) { 1464239462Sdim const MachineOperand &MIMM = MI.getOperand(CurOp++); 1465239462Sdim if (MIMM.isImm()) { 1466239462Sdim unsigned Val = MIMM.getImm(); 1467239462Sdim assert(Val < 16 && "Immediate operand value out of range"); 1468239462Sdim RegNum |= Val; 1469239462Sdim } 1470239462Sdim } 1471239462Sdim emitConstant(RegNum, 1); 1472239462Sdim } else { 1473239462Sdim emitConstant(MI.getOperand(CurOp++).getImm(), 1474239462Sdim X86II::getSizeOfImm(Desc->TSFlags)); 1475239462Sdim } 1476239462Sdim } 1477239462Sdim 1478234353Sdim if (!MI.isVariadic() && CurOp != NumOps) { 1479198090Srdivacky#ifndef NDEBUG 1480202375Srdivacky dbgs() << "Cannot encode all operands of: " << MI << "\n"; 1481198090Srdivacky#endif 1482198090Srdivacky llvm_unreachable(0); 1483193323Sed } 1484198090Srdivacky 1485198090Srdivacky MCE.processDebugLoc(MI.getDebugLoc(), false); 1486193323Sed} 1487