X86CodeEmitter.cpp revision 228379
1219820Sjeff//===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===// 2219820Sjeff// 3219820Sjeff// The LLVM Compiler Infrastructure 4219820Sjeff// 5219820Sjeff// This file is distributed under the University of Illinois Open Source 6219820Sjeff// License. See LICENSE.TXT for details. 7219820Sjeff// 8219820Sjeff//===----------------------------------------------------------------------===// 9219820Sjeff// 10219820Sjeff// This file contains the pass that transforms the X86 machine instructions into 11219820Sjeff// relocatable machine code. 12219820Sjeff// 13219820Sjeff//===----------------------------------------------------------------------===// 14219820Sjeff 15219820Sjeff#define DEBUG_TYPE "x86-emitter" 16219820Sjeff#include "X86InstrInfo.h" 17219820Sjeff#include "X86JITInfo.h" 18219820Sjeff#include "X86Subtarget.h" 19219820Sjeff#include "X86TargetMachine.h" 20219820Sjeff#include "X86Relocations.h" 21219820Sjeff#include "X86.h" 22219820Sjeff#include "llvm/LLVMContext.h" 23219820Sjeff#include "llvm/PassManager.h" 24219820Sjeff#include "llvm/CodeGen/JITCodeEmitter.h" 25219820Sjeff#include "llvm/CodeGen/MachineFunctionPass.h" 26219820Sjeff#include "llvm/CodeGen/MachineInstr.h" 27219820Sjeff#include "llvm/CodeGen/MachineModuleInfo.h" 28219820Sjeff#include "llvm/CodeGen/Passes.h" 29219820Sjeff#include "llvm/Function.h" 30219820Sjeff#include "llvm/ADT/Statistic.h" 31219820Sjeff#include "llvm/MC/MCCodeEmitter.h" 32219820Sjeff#include "llvm/MC/MCExpr.h" 33219820Sjeff#include "llvm/MC/MCInst.h" 34219820Sjeff#include "llvm/Support/Debug.h" 35219820Sjeff#include "llvm/Support/ErrorHandling.h" 36219820Sjeff#include "llvm/Support/raw_ostream.h" 37219820Sjeff#include "llvm/Target/TargetOptions.h" 38219820Sjeffusing namespace llvm; 39219820Sjeff 40219820SjeffSTATISTIC(NumEmitted, "Number of machine instructions emitted"); 41219820Sjeff 42219820Sjeffnamespace { 43219820Sjeff template<class CodeEmitter> 44219820Sjeff class Emitter : public MachineFunctionPass { 45219820Sjeff const X86InstrInfo *II; 46219820Sjeff const TargetData *TD; 47219820Sjeff X86TargetMachine &TM; 48219820Sjeff CodeEmitter &MCE; 49219820Sjeff MachineModuleInfo *MMI; 50219820Sjeff intptr_t PICBaseOffset; 51219820Sjeff bool Is64BitMode; 52219820Sjeff bool IsPIC; 53219820Sjeff public: 54219820Sjeff static char ID; 55219820Sjeff explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce) 56219820Sjeff : MachineFunctionPass(ID), II(0), TD(0), TM(tm), 57219820Sjeff MCE(mce), PICBaseOffset(0), Is64BitMode(false), 58219820Sjeff IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 59219820Sjeff Emitter(X86TargetMachine &tm, CodeEmitter &mce, 60219820Sjeff const X86InstrInfo &ii, const TargetData &td, bool is64) 61219820Sjeff : MachineFunctionPass(ID), II(&ii), TD(&td), TM(tm), 62219820Sjeff MCE(mce), PICBaseOffset(0), Is64BitMode(is64), 63219820Sjeff IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 64219820Sjeff 65219820Sjeff bool runOnMachineFunction(MachineFunction &MF); 66219820Sjeff 67219820Sjeff virtual const char *getPassName() const { 68219820Sjeff return "X86 Machine Code Emitter"; 69219820Sjeff } 70219820Sjeff 71219820Sjeff void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc); 72219820Sjeff 73219820Sjeff void getAnalysisUsage(AnalysisUsage &AU) const { 74219820Sjeff AU.setPreservesAll(); 75219820Sjeff AU.addRequired<MachineModuleInfo>(); 76219820Sjeff MachineFunctionPass::getAnalysisUsage(AU); 77219820Sjeff } 78219820Sjeff 79219820Sjeff private: 80219820Sjeff void emitPCRelativeBlockAddress(MachineBasicBlock *MBB); 81219820Sjeff void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 82219820Sjeff intptr_t Disp = 0, intptr_t PCAdj = 0, 83219820Sjeff bool Indirect = false); 84219820Sjeff void emitExternalSymbolAddress(const char *ES, unsigned Reloc); 85219820Sjeff void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0, 86219820Sjeff intptr_t PCAdj = 0); 87219820Sjeff void emitJumpTableAddress(unsigned JTI, unsigned Reloc, 88219820Sjeff intptr_t PCAdj = 0); 89219820Sjeff 90219820Sjeff void emitDisplacementField(const MachineOperand *RelocOp, int DispVal, 91219820Sjeff intptr_t Adj = 0, bool IsPCRel = true); 92219820Sjeff 93219820Sjeff void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField); 94219820Sjeff void emitRegModRMByte(unsigned RegOpcodeField); 95219820Sjeff void emitSIBByte(unsigned SS, unsigned Index, unsigned Base); 96219820Sjeff void emitConstant(uint64_t Val, unsigned Size); 97219820Sjeff 98219820Sjeff void emitMemModRMByte(const MachineInstr &MI, 99219820Sjeff unsigned Op, unsigned RegOpcodeField, 100219820Sjeff intptr_t PCAdj = 0); 101219820Sjeff }; 102219820Sjeff 103219820Sjefftemplate<class CodeEmitter> 104219820Sjeff char Emitter<CodeEmitter>::ID = 0; 105219820Sjeff} // end anonymous namespace. 106219820Sjeff 107219820Sjeff/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code 108219820Sjeff/// to the specified templated MachineCodeEmitter object. 109219820SjeffFunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM, 110219820Sjeff JITCodeEmitter &JCE) { 111219820Sjeff return new Emitter<JITCodeEmitter>(TM, JCE); 112219820Sjeff} 113219820Sjeff 114219820Sjefftemplate<class CodeEmitter> 115219820Sjeffbool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) { 116219820Sjeff MMI = &getAnalysis<MachineModuleInfo>(); 117219820Sjeff MCE.setModuleInfo(MMI); 118219820Sjeff 119219820Sjeff II = TM.getInstrInfo(); 120219820Sjeff TD = TM.getTargetData(); 121219820Sjeff Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit(); 122219820Sjeff IsPIC = TM.getRelocationModel() == Reloc::PIC_; 123219820Sjeff 124219820Sjeff do { 125219820Sjeff DEBUG(dbgs() << "JITTing function '" 126219820Sjeff << MF.getFunction()->getName() << "'\n"); 127219820Sjeff MCE.startFunction(MF); 128219820Sjeff for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 129219820Sjeff MBB != E; ++MBB) { 130219820Sjeff MCE.StartMachineBasicBlock(MBB); 131219820Sjeff for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 132219820Sjeff I != E; ++I) { 133219820Sjeff const MCInstrDesc &Desc = I->getDesc(); 134219820Sjeff emitInstruction(*I, &Desc); 135219820Sjeff // MOVPC32r is basically a call plus a pop instruction. 136219820Sjeff if (Desc.getOpcode() == X86::MOVPC32r) 137219820Sjeff emitInstruction(*I, &II->get(X86::POP32r)); 138219820Sjeff ++NumEmitted; // Keep track of the # of mi's emitted 139219820Sjeff } 140219820Sjeff } 141219820Sjeff } while (MCE.finishFunction(MF)); 142219820Sjeff 143219820Sjeff return false; 144219820Sjeff} 145219820Sjeff 146219820Sjeff/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64 147219820Sjeff/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 148219820Sjeff/// size, and 3) use of X86-64 extended registers. 149219820Sjeffstatic unsigned determineREX(const MachineInstr &MI) { 150219820Sjeff unsigned REX = 0; 151219820Sjeff const MCInstrDesc &Desc = MI.getDesc(); 152219820Sjeff 153219820Sjeff // Pseudo instructions do not need REX prefix byte. 154219820Sjeff if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) 155219820Sjeff return 0; 156219820Sjeff if (Desc.TSFlags & X86II::REX_W) 157219820Sjeff REX |= 1 << 3; 158219820Sjeff 159219820Sjeff unsigned NumOps = Desc.getNumOperands(); 160219820Sjeff if (NumOps) { 161219820Sjeff bool isTwoAddr = NumOps > 1 && 162219820Sjeff Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; 163219820Sjeff 164219820Sjeff // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 165219820Sjeff unsigned i = isTwoAddr ? 1 : 0; 166219820Sjeff for (unsigned e = NumOps; i != e; ++i) { 167219820Sjeff const MachineOperand& MO = MI.getOperand(i); 168219820Sjeff if (MO.isReg()) { 169219820Sjeff unsigned Reg = MO.getReg(); 170219820Sjeff if (X86II::isX86_64NonExtLowByteReg(Reg)) 171219820Sjeff REX |= 0x40; 172219820Sjeff } 173219820Sjeff } 174219820Sjeff 175219820Sjeff switch (Desc.TSFlags & X86II::FormMask) { 176219820Sjeff case X86II::MRMInitReg: 177219820Sjeff if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 178219820Sjeff REX |= (1 << 0) | (1 << 2); 179219820Sjeff break; 180219820Sjeff case X86II::MRMSrcReg: { 181219820Sjeff if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 182219820Sjeff REX |= 1 << 2; 183219820Sjeff i = isTwoAddr ? 2 : 1; 184219820Sjeff for (unsigned e = NumOps; i != e; ++i) { 185219820Sjeff const MachineOperand& MO = MI.getOperand(i); 186219820Sjeff if (X86InstrInfo::isX86_64ExtendedReg(MO)) 187219820Sjeff REX |= 1 << 0; 188219820Sjeff } 189219820Sjeff break; 190219820Sjeff } 191219820Sjeff case X86II::MRMSrcMem: { 192219820Sjeff if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 193219820Sjeff REX |= 1 << 2; 194219820Sjeff unsigned Bit = 0; 195219820Sjeff i = isTwoAddr ? 2 : 1; 196219820Sjeff for (; i != NumOps; ++i) { 197219820Sjeff const MachineOperand& MO = MI.getOperand(i); 198219820Sjeff if (MO.isReg()) { 199219820Sjeff if (X86InstrInfo::isX86_64ExtendedReg(MO)) 200219820Sjeff REX |= 1 << Bit; 201219820Sjeff Bit++; 202219820Sjeff } 203219820Sjeff } 204219820Sjeff break; 205219820Sjeff } 206219820Sjeff case X86II::MRM0m: case X86II::MRM1m: 207219820Sjeff case X86II::MRM2m: case X86II::MRM3m: 208219820Sjeff case X86II::MRM4m: case X86II::MRM5m: 209219820Sjeff case X86II::MRM6m: case X86II::MRM7m: 210219820Sjeff case X86II::MRMDestMem: { 211219820Sjeff unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); 212219820Sjeff i = isTwoAddr ? 1 : 0; 213219820Sjeff if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e))) 214219820Sjeff REX |= 1 << 2; 215219820Sjeff unsigned Bit = 0; 216219820Sjeff for (; i != e; ++i) { 217219820Sjeff const MachineOperand& MO = MI.getOperand(i); 218219820Sjeff if (MO.isReg()) { 219219820Sjeff if (X86InstrInfo::isX86_64ExtendedReg(MO)) 220219820Sjeff REX |= 1 << Bit; 221219820Sjeff Bit++; 222219820Sjeff } 223219820Sjeff } 224219820Sjeff break; 225219820Sjeff } 226219820Sjeff default: { 227219820Sjeff if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 228219820Sjeff REX |= 1 << 0; 229219820Sjeff i = isTwoAddr ? 2 : 1; 230219820Sjeff for (unsigned e = NumOps; i != e; ++i) { 231219820Sjeff const MachineOperand& MO = MI.getOperand(i); 232219820Sjeff if (X86InstrInfo::isX86_64ExtendedReg(MO)) 233219820Sjeff REX |= 1 << 2; 234219820Sjeff } 235219820Sjeff break; 236219820Sjeff } 237219820Sjeff } 238219820Sjeff } 239219820Sjeff return REX; 240219820Sjeff} 241219820Sjeff 242219820Sjeff 243219820Sjeff/// emitPCRelativeBlockAddress - This method keeps track of the information 244219820Sjeff/// necessary to resolve the address of this block later and emits a dummy 245219820Sjeff/// value. 246219820Sjeff/// 247219820Sjefftemplate<class CodeEmitter> 248219820Sjeffvoid Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { 249219820Sjeff // Remember where this reference was and where it is to so we can 250219820Sjeff // deal with it later. 251219820Sjeff MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 252219820Sjeff X86::reloc_pcrel_word, MBB)); 253219820Sjeff MCE.emitWordLE(0); 254219820Sjeff} 255219820Sjeff 256219820Sjeff/// emitGlobalAddress - Emit the specified address to the code stream assuming 257219820Sjeff/// this is part of a "take the address of a global" instruction. 258219820Sjeff/// 259219820Sjefftemplate<class CodeEmitter> 260219820Sjeffvoid Emitter<CodeEmitter>::emitGlobalAddress(const GlobalValue *GV, 261219820Sjeff unsigned Reloc, 262219820Sjeff intptr_t Disp /* = 0 */, 263219820Sjeff intptr_t PCAdj /* = 0 */, 264219820Sjeff bool Indirect /* = false */) { 265219820Sjeff intptr_t RelocCST = Disp; 266219820Sjeff if (Reloc == X86::reloc_picrel_word) 267219820Sjeff RelocCST = PICBaseOffset; 268219820Sjeff else if (Reloc == X86::reloc_pcrel_word) 269219820Sjeff RelocCST = PCAdj; 270219820Sjeff MachineRelocation MR = Indirect 271219820Sjeff ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 272219820Sjeff const_cast<GlobalValue *>(GV), 273219820Sjeff RelocCST, false) 274219820Sjeff : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 275219820Sjeff const_cast<GlobalValue *>(GV), RelocCST, false); 276219820Sjeff MCE.addRelocation(MR); 277219820Sjeff // The relocated value will be added to the displacement 278219820Sjeff if (Reloc == X86::reloc_absolute_dword) 279219820Sjeff MCE.emitDWordLE(Disp); 280219820Sjeff else 281219820Sjeff MCE.emitWordLE((int32_t)Disp); 282219820Sjeff} 283219820Sjeff 284219820Sjeff/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 285219820Sjeff/// be emitted to the current location in the function, and allow it to be PC 286219820Sjeff/// relative. 287219820Sjefftemplate<class CodeEmitter> 288219820Sjeffvoid Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES, 289219820Sjeff unsigned Reloc) { 290219820Sjeff intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0; 291219820Sjeff 292219820Sjeff // X86 never needs stubs because instruction selection will always pick 293219820Sjeff // an instruction sequence that is large enough to hold any address 294219820Sjeff // to a symbol. 295219820Sjeff // (see X86ISelLowering.cpp, near 2039: X86TargetLowering::LowerCall) 296219820Sjeff bool NeedStub = false; 297219820Sjeff MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 298219820Sjeff Reloc, ES, RelocCST, 299219820Sjeff 0, NeedStub)); 300219820Sjeff if (Reloc == X86::reloc_absolute_dword) 301219820Sjeff MCE.emitDWordLE(0); 302219820Sjeff else 303219820Sjeff MCE.emitWordLE(0); 304219820Sjeff} 305219820Sjeff 306219820Sjeff/// emitConstPoolAddress - Arrange for the address of an constant pool 307219820Sjeff/// to be emitted to the current location in the function, and allow it to be PC 308219820Sjeff/// relative. 309219820Sjefftemplate<class CodeEmitter> 310219820Sjeffvoid Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc, 311219820Sjeff intptr_t Disp /* = 0 */, 312219820Sjeff intptr_t PCAdj /* = 0 */) { 313219820Sjeff intptr_t RelocCST = 0; 314219820Sjeff if (Reloc == X86::reloc_picrel_word) 315219820Sjeff RelocCST = PICBaseOffset; 316219820Sjeff else if (Reloc == X86::reloc_pcrel_word) 317219820Sjeff RelocCST = PCAdj; 318219820Sjeff MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 319219820Sjeff Reloc, CPI, RelocCST)); 320219820Sjeff // The relocated value will be added to the displacement 321219820Sjeff if (Reloc == X86::reloc_absolute_dword) 322219820Sjeff MCE.emitDWordLE(Disp); 323219820Sjeff else 324219820Sjeff MCE.emitWordLE((int32_t)Disp); 325219820Sjeff} 326219820Sjeff 327219820Sjeff/// emitJumpTableAddress - Arrange for the address of a jump table to 328219820Sjeff/// be emitted to the current location in the function, and allow it to be PC 329219820Sjeff/// relative. 330219820Sjefftemplate<class CodeEmitter> 331219820Sjeffvoid Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc, 332219820Sjeff intptr_t PCAdj /* = 0 */) { 333219820Sjeff intptr_t RelocCST = 0; 334219820Sjeff if (Reloc == X86::reloc_picrel_word) 335219820Sjeff RelocCST = PICBaseOffset; 336219820Sjeff else if (Reloc == X86::reloc_pcrel_word) 337219820Sjeff RelocCST = PCAdj; 338219820Sjeff MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 339219820Sjeff Reloc, JTI, RelocCST)); 340219820Sjeff // The relocated value will be added to the displacement 341219820Sjeff if (Reloc == X86::reloc_absolute_dword) 342219820Sjeff MCE.emitDWordLE(0); 343219820Sjeff else 344219820Sjeff MCE.emitWordLE(0); 345219820Sjeff} 346219820Sjeff 347219820Sjeffinline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, 348219820Sjeff unsigned RM) { 349219820Sjeff assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 350219820Sjeff return RM | (RegOpcode << 3) | (Mod << 6); 351219820Sjeff} 352219820Sjeff 353219820Sjefftemplate<class CodeEmitter> 354219820Sjeffvoid Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg, 355219820Sjeff unsigned RegOpcodeFld){ 356219820Sjeff MCE.emitByte(ModRMByte(3, RegOpcodeFld, X86_MC::getX86RegNum(ModRMReg))); 357219820Sjeff} 358219820Sjeff 359219820Sjefftemplate<class CodeEmitter> 360219820Sjeffvoid Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) { 361219820Sjeff MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0)); 362219820Sjeff} 363219820Sjeff 364219820Sjefftemplate<class CodeEmitter> 365219820Sjeffvoid Emitter<CodeEmitter>::emitSIBByte(unsigned SS, 366219820Sjeff unsigned Index, 367219820Sjeff unsigned Base) { 368219820Sjeff // SIB byte is in the same format as the ModRMByte... 369219820Sjeff MCE.emitByte(ModRMByte(SS, Index, Base)); 370219820Sjeff} 371219820Sjeff 372219820Sjefftemplate<class CodeEmitter> 373219820Sjeffvoid Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) { 374219820Sjeff // Output the constant in little endian byte order... 375219820Sjeff for (unsigned i = 0; i != Size; ++i) { 376219820Sjeff MCE.emitByte(Val & 255); 377219820Sjeff Val >>= 8; 378219820Sjeff } 379219820Sjeff} 380219820Sjeff 381219820Sjeff/// isDisp8 - Return true if this signed displacement fits in a 8-bit 382219820Sjeff/// sign-extended field. 383219820Sjeffstatic bool isDisp8(int Value) { 384219820Sjeff return Value == (signed char)Value; 385219820Sjeff} 386219820Sjeff 387219820Sjeffstatic bool gvNeedsNonLazyPtr(const MachineOperand &GVOp, 388219820Sjeff const TargetMachine &TM) { 389219820Sjeff // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer 390219820Sjeff // mechanism as 32-bit mode. 391219820Sjeff if (TM.getSubtarget<X86Subtarget>().is64Bit() && 392219820Sjeff !TM.getSubtarget<X86Subtarget>().isTargetDarwin()) 393 return false; 394 395 // Return true if this is a reference to a stub containing the address of the 396 // global, not the global itself. 397 return isGlobalStubReference(GVOp.getTargetFlags()); 398} 399 400template<class CodeEmitter> 401void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp, 402 int DispVal, 403 intptr_t Adj /* = 0 */, 404 bool IsPCRel /* = true */) { 405 // If this is a simple integer displacement that doesn't require a relocation, 406 // emit it now. 407 if (!RelocOp) { 408 emitConstant(DispVal, 4); 409 return; 410 } 411 412 // Otherwise, this is something that requires a relocation. Emit it as such 413 // now. 414 unsigned RelocType = Is64BitMode ? 415 (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext) 416 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 417 if (RelocOp->isGlobal()) { 418 // In 64-bit static small code model, we could potentially emit absolute. 419 // But it's probably not beneficial. If the MCE supports using RIP directly 420 // do it, otherwise fallback to absolute (this is determined by IsPCRel). 421 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative 422 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute 423 bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM); 424 emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(), 425 Adj, Indirect); 426 } else if (RelocOp->isSymbol()) { 427 emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType); 428 } else if (RelocOp->isCPI()) { 429 emitConstPoolAddress(RelocOp->getIndex(), RelocType, 430 RelocOp->getOffset(), Adj); 431 } else { 432 assert(RelocOp->isJTI() && "Unexpected machine operand!"); 433 emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj); 434 } 435} 436 437template<class CodeEmitter> 438void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI, 439 unsigned Op,unsigned RegOpcodeField, 440 intptr_t PCAdj) { 441 const MachineOperand &Op3 = MI.getOperand(Op+3); 442 int DispVal = 0; 443 const MachineOperand *DispForReloc = 0; 444 445 // Figure out what sort of displacement we have to handle here. 446 if (Op3.isGlobal()) { 447 DispForReloc = &Op3; 448 } else if (Op3.isSymbol()) { 449 DispForReloc = &Op3; 450 } else if (Op3.isCPI()) { 451 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) { 452 DispForReloc = &Op3; 453 } else { 454 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex()); 455 DispVal += Op3.getOffset(); 456 } 457 } else if (Op3.isJTI()) { 458 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) { 459 DispForReloc = &Op3; 460 } else { 461 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex()); 462 } 463 } else { 464 DispVal = Op3.getImm(); 465 } 466 467 const MachineOperand &Base = MI.getOperand(Op); 468 const MachineOperand &Scale = MI.getOperand(Op+1); 469 const MachineOperand &IndexReg = MI.getOperand(Op+2); 470 471 unsigned BaseReg = Base.getReg(); 472 473 // Handle %rip relative addressing. 474 if (BaseReg == X86::RIP || 475 (Is64BitMode && DispForReloc)) { // [disp32+RIP] in X86-64 mode 476 assert(IndexReg.getReg() == 0 && Is64BitMode && 477 "Invalid rip-relative address"); 478 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); 479 emitDisplacementField(DispForReloc, DispVal, PCAdj, true); 480 return; 481 } 482 483 // Indicate that the displacement will use an pcrel or absolute reference 484 // by default. MCEs able to resolve addresses on-the-fly use pcrel by default 485 // while others, unless explicit asked to use RIP, use absolute references. 486 bool IsPCRel = MCE.earlyResolveAddresses() ? true : false; 487 488 // Is a SIB byte needed? 489 // If no BaseReg, issue a RIP relative instruction only if the MCE can 490 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 491 // 2-7) and absolute references. 492 unsigned BaseRegNo = -1U; 493 if (BaseReg != 0 && BaseReg != X86::RIP) 494 BaseRegNo = X86_MC::getX86RegNum(BaseReg); 495 496 if (// The SIB byte must be used if there is an index register. 497 IndexReg.getReg() == 0 && 498 // The SIB byte must be used if the base is ESP/RSP/R12, all of which 499 // encode to an R/M value of 4, which indicates that a SIB byte is 500 // present. 501 BaseRegNo != N86::ESP && 502 // If there is no base register and we're in 64-bit mode, we need a SIB 503 // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 504 (!Is64BitMode || BaseReg != 0)) { 505 if (BaseReg == 0 || // [disp32] in X86-32 mode 506 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode 507 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); 508 emitDisplacementField(DispForReloc, DispVal, PCAdj, true); 509 return; 510 } 511 512 // If the base is not EBP/ESP and there is no displacement, use simple 513 // indirect register encoding, this handles addresses like [EAX]. The 514 // encoding for [EBP] with no displacement means [disp32] so we handle it 515 // by emitting a displacement of 0 below. 516 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { 517 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo)); 518 return; 519 } 520 521 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 522 if (!DispForReloc && isDisp8(DispVal)) { 523 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo)); 524 emitConstant(DispVal, 1); 525 return; 526 } 527 528 // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 529 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo)); 530 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel); 531 return; 532 } 533 534 // Otherwise we need a SIB byte, so start by outputting the ModR/M byte first. 535 assert(IndexReg.getReg() != X86::ESP && 536 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 537 538 bool ForceDisp32 = false; 539 bool ForceDisp8 = false; 540 if (BaseReg == 0) { 541 // If there is no base register, we emit the special case SIB byte with 542 // MOD=0, BASE=4, to JUST get the index, scale, and displacement. 543 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4)); 544 ForceDisp32 = true; 545 } else if (DispForReloc) { 546 // Emit the normal disp32 encoding. 547 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4)); 548 ForceDisp32 = true; 549 } else if (DispVal == 0 && BaseRegNo != N86::EBP) { 550 // Emit no displacement ModR/M byte 551 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4)); 552 } else if (isDisp8(DispVal)) { 553 // Emit the disp8 encoding... 554 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4)); 555 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 556 } else { 557 // Emit the normal disp32 encoding... 558 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4)); 559 } 560 561 // Calculate what the SS field value should be... 562 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; 563 unsigned SS = SSTable[Scale.getImm()]; 564 565 if (BaseReg == 0) { 566 // Handle the SIB byte for the case where there is no base, see Intel 567 // Manual 2A, table 2-7. The displacement has already been output. 568 unsigned IndexRegNo; 569 if (IndexReg.getReg()) 570 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg()); 571 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 572 IndexRegNo = 4; 573 emitSIBByte(SS, IndexRegNo, 5); 574 } else { 575 unsigned BaseRegNo = X86_MC::getX86RegNum(BaseReg); 576 unsigned IndexRegNo; 577 if (IndexReg.getReg()) 578 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg()); 579 else 580 IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 581 emitSIBByte(SS, IndexRegNo, BaseRegNo); 582 } 583 584 // Do we need to output a displacement? 585 if (ForceDisp8) { 586 emitConstant(DispVal, 1); 587 } else if (DispVal != 0 || ForceDisp32) { 588 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel); 589 } 590} 591 592static const MCInstrDesc *UpdateOp(MachineInstr &MI, const X86InstrInfo *II, 593 unsigned Opcode) { 594 const MCInstrDesc *Desc = &II->get(Opcode); 595 MI.setDesc(*Desc); 596 return Desc; 597} 598 599template<class CodeEmitter> 600void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI, 601 const MCInstrDesc *Desc) { 602 DEBUG(dbgs() << MI); 603 604 // If this is a pseudo instruction, lower it. 605 switch (Desc->getOpcode()) { 606 case X86::ADD16rr_DB: Desc = UpdateOp(MI, II, X86::OR16rr); break; 607 case X86::ADD32rr_DB: Desc = UpdateOp(MI, II, X86::OR32rr); break; 608 case X86::ADD64rr_DB: Desc = UpdateOp(MI, II, X86::OR64rr); break; 609 case X86::ADD16ri_DB: Desc = UpdateOp(MI, II, X86::OR16ri); break; 610 case X86::ADD32ri_DB: Desc = UpdateOp(MI, II, X86::OR32ri); break; 611 case X86::ADD64ri32_DB: Desc = UpdateOp(MI, II, X86::OR64ri32); break; 612 case X86::ADD16ri8_DB: Desc = UpdateOp(MI, II, X86::OR16ri8); break; 613 case X86::ADD32ri8_DB: Desc = UpdateOp(MI, II, X86::OR32ri8); break; 614 case X86::ADD64ri8_DB: Desc = UpdateOp(MI, II, X86::OR64ri8); break; 615 case X86::ACQUIRE_MOV8rm: Desc = UpdateOp(MI, II, X86::MOV8rm); break; 616 case X86::ACQUIRE_MOV16rm: Desc = UpdateOp(MI, II, X86::MOV16rm); break; 617 case X86::ACQUIRE_MOV32rm: Desc = UpdateOp(MI, II, X86::MOV32rm); break; 618 case X86::ACQUIRE_MOV64rm: Desc = UpdateOp(MI, II, X86::MOV64rm); break; 619 case X86::RELEASE_MOV8mr: Desc = UpdateOp(MI, II, X86::MOV8mr); break; 620 case X86::RELEASE_MOV16mr: Desc = UpdateOp(MI, II, X86::MOV16mr); break; 621 case X86::RELEASE_MOV32mr: Desc = UpdateOp(MI, II, X86::MOV32mr); break; 622 case X86::RELEASE_MOV64mr: Desc = UpdateOp(MI, II, X86::MOV64mr); break; 623 } 624 625 626 MCE.processDebugLoc(MI.getDebugLoc(), true); 627 628 unsigned Opcode = Desc->Opcode; 629 630 // Emit the lock opcode prefix as needed. 631 if (Desc->TSFlags & X86II::LOCK) 632 MCE.emitByte(0xF0); 633 634 // Emit segment override opcode prefix as needed. 635 switch (Desc->TSFlags & X86II::SegOvrMask) { 636 case X86II::FS: 637 MCE.emitByte(0x64); 638 break; 639 case X86II::GS: 640 MCE.emitByte(0x65); 641 break; 642 default: llvm_unreachable("Invalid segment!"); 643 case 0: break; // No segment override! 644 } 645 646 // Emit the repeat opcode prefix as needed. 647 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) 648 MCE.emitByte(0xF3); 649 650 // Emit the operand size opcode prefix as needed. 651 if (Desc->TSFlags & X86II::OpSize) 652 MCE.emitByte(0x66); 653 654 // Emit the address size opcode prefix as needed. 655 if (Desc->TSFlags & X86II::AdSize) 656 MCE.emitByte(0x67); 657 658 bool Need0FPrefix = false; 659 switch (Desc->TSFlags & X86II::Op0Mask) { 660 case X86II::TB: // Two-byte opcode prefix 661 case X86II::T8: // 0F 38 662 case X86II::TA: // 0F 3A 663 case X86II::A6: // 0F A6 664 case X86II::A7: // 0F A7 665 Need0FPrefix = true; 666 break; 667 case X86II::TF: // F2 0F 38 668 MCE.emitByte(0xF2); 669 Need0FPrefix = true; 670 break; 671 case X86II::REP: break; // already handled. 672 case X86II::XS: // F3 0F 673 MCE.emitByte(0xF3); 674 Need0FPrefix = true; 675 break; 676 case X86II::XD: // F2 0F 677 MCE.emitByte(0xF2); 678 Need0FPrefix = true; 679 break; 680 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: 681 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: 682 MCE.emitByte(0xD8+ 683 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8) 684 >> X86II::Op0Shift)); 685 break; // Two-byte opcode prefix 686 default: llvm_unreachable("Invalid prefix!"); 687 case 0: break; // No prefix! 688 } 689 690 // Handle REX prefix. 691 if (Is64BitMode) { 692 if (unsigned REX = determineREX(MI)) 693 MCE.emitByte(0x40 | REX); 694 } 695 696 // 0x0F escape code must be emitted just before the opcode. 697 if (Need0FPrefix) 698 MCE.emitByte(0x0F); 699 700 switch (Desc->TSFlags & X86II::Op0Mask) { 701 case X86II::TF: // F2 0F 38 702 case X86II::T8: // 0F 38 703 MCE.emitByte(0x38); 704 break; 705 case X86II::TA: // 0F 3A 706 MCE.emitByte(0x3A); 707 break; 708 case X86II::A6: // 0F A6 709 MCE.emitByte(0xA6); 710 break; 711 case X86II::A7: // 0F A7 712 MCE.emitByte(0xA7); 713 break; 714 } 715 716 // If this is a two-address instruction, skip one of the register operands. 717 unsigned NumOps = Desc->getNumOperands(); 718 unsigned CurOp = 0; 719 if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) != -1) 720 ++CurOp; 721 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1,MCOI::TIED_TO)== 0) 722 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 723 --NumOps; 724 725 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(Desc->TSFlags); 726 switch (Desc->TSFlags & X86II::FormMask) { 727 default: 728 llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!"); 729 case X86II::Pseudo: 730 // Remember the current PC offset, this is the PIC relocation 731 // base address. 732 switch (Opcode) { 733 default: 734 llvm_unreachable("pseudo instructions should be removed before code" 735 " emission"); 736 break; 737 // Do nothing for Int_MemBarrier - it's just a comment. Add a debug 738 // to make it slightly easier to see. 739 case X86::Int_MemBarrier: 740 DEBUG(dbgs() << "#MEMBARRIER\n"); 741 break; 742 743 case TargetOpcode::INLINEASM: 744 // We allow inline assembler nodes with empty bodies - they can 745 // implicitly define registers, which is ok for JIT. 746 if (MI.getOperand(0).getSymbolName()[0]) 747 report_fatal_error("JIT does not support inline asm!"); 748 break; 749 case TargetOpcode::PROLOG_LABEL: 750 case TargetOpcode::GC_LABEL: 751 case TargetOpcode::EH_LABEL: 752 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 753 break; 754 755 case TargetOpcode::IMPLICIT_DEF: 756 case TargetOpcode::KILL: 757 break; 758 case X86::MOVPC32r: { 759 // This emits the "call" portion of this pseudo instruction. 760 MCE.emitByte(BaseOpcode); 761 emitConstant(0, X86II::getSizeOfImm(Desc->TSFlags)); 762 // Remember PIC base. 763 PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset(); 764 X86JITInfo *JTI = TM.getJITInfo(); 765 JTI->setPICBase(MCE.getCurrentPCValue()); 766 break; 767 } 768 } 769 CurOp = NumOps; 770 break; 771 case X86II::RawFrm: { 772 MCE.emitByte(BaseOpcode); 773 774 if (CurOp == NumOps) 775 break; 776 777 const MachineOperand &MO = MI.getOperand(CurOp++); 778 779 DEBUG(dbgs() << "RawFrm CurOp " << CurOp << "\n"); 780 DEBUG(dbgs() << "isMBB " << MO.isMBB() << "\n"); 781 DEBUG(dbgs() << "isGlobal " << MO.isGlobal() << "\n"); 782 DEBUG(dbgs() << "isSymbol " << MO.isSymbol() << "\n"); 783 DEBUG(dbgs() << "isImm " << MO.isImm() << "\n"); 784 785 if (MO.isMBB()) { 786 emitPCRelativeBlockAddress(MO.getMBB()); 787 break; 788 } 789 790 if (MO.isGlobal()) { 791 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word, 792 MO.getOffset(), 0); 793 break; 794 } 795 796 if (MO.isSymbol()) { 797 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word); 798 break; 799 } 800 801 // FIXME: Only used by hackish MCCodeEmitter, remove when dead. 802 if (MO.isJTI()) { 803 emitJumpTableAddress(MO.getIndex(), X86::reloc_pcrel_word); 804 break; 805 } 806 807 assert(MO.isImm() && "Unknown RawFrm operand!"); 808 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32 || 809 Opcode == X86::WINCALL64pcrel32) { 810 // Fix up immediate operand for pc relative calls. 811 intptr_t Imm = (intptr_t)MO.getImm(); 812 Imm = Imm - MCE.getCurrentPCValue() - 4; 813 emitConstant(Imm, X86II::getSizeOfImm(Desc->TSFlags)); 814 } else 815 emitConstant(MO.getImm(), X86II::getSizeOfImm(Desc->TSFlags)); 816 break; 817 } 818 819 case X86II::AddRegFrm: { 820 MCE.emitByte(BaseOpcode + 821 X86_MC::getX86RegNum(MI.getOperand(CurOp++).getReg())); 822 823 if (CurOp == NumOps) 824 break; 825 826 const MachineOperand &MO1 = MI.getOperand(CurOp++); 827 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 828 if (MO1.isImm()) { 829 emitConstant(MO1.getImm(), Size); 830 break; 831 } 832 833 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word 834 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 835 if (Opcode == X86::MOV64ri64i32) 836 rt = X86::reloc_absolute_word; // FIXME: add X86II flag? 837 // This should not occur on Darwin for relocatable objects. 838 if (Opcode == X86::MOV64ri) 839 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag? 840 if (MO1.isGlobal()) { 841 bool Indirect = gvNeedsNonLazyPtr(MO1, TM); 842 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, 843 Indirect); 844 } else if (MO1.isSymbol()) 845 emitExternalSymbolAddress(MO1.getSymbolName(), rt); 846 else if (MO1.isCPI()) 847 emitConstPoolAddress(MO1.getIndex(), rt); 848 else if (MO1.isJTI()) 849 emitJumpTableAddress(MO1.getIndex(), rt); 850 break; 851 } 852 853 case X86II::MRMDestReg: { 854 MCE.emitByte(BaseOpcode); 855 emitRegModRMByte(MI.getOperand(CurOp).getReg(), 856 X86_MC::getX86RegNum(MI.getOperand(CurOp+1).getReg())); 857 CurOp += 2; 858 if (CurOp != NumOps) 859 emitConstant(MI.getOperand(CurOp++).getImm(), 860 X86II::getSizeOfImm(Desc->TSFlags)); 861 break; 862 } 863 case X86II::MRMDestMem: { 864 MCE.emitByte(BaseOpcode); 865 emitMemModRMByte(MI, CurOp, 866 X86_MC::getX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands) 867 .getReg())); 868 CurOp += X86::AddrNumOperands + 1; 869 if (CurOp != NumOps) 870 emitConstant(MI.getOperand(CurOp++).getImm(), 871 X86II::getSizeOfImm(Desc->TSFlags)); 872 break; 873 } 874 875 case X86II::MRMSrcReg: 876 MCE.emitByte(BaseOpcode); 877 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(), 878 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg())); 879 CurOp += 2; 880 if (CurOp != NumOps) 881 emitConstant(MI.getOperand(CurOp++).getImm(), 882 X86II::getSizeOfImm(Desc->TSFlags)); 883 break; 884 885 case X86II::MRMSrcMem: { 886 int AddrOperands = X86::AddrNumOperands; 887 888 intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ? 889 X86II::getSizeOfImm(Desc->TSFlags) : 0; 890 891 MCE.emitByte(BaseOpcode); 892 emitMemModRMByte(MI, CurOp+1, 893 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj); 894 CurOp += AddrOperands + 1; 895 if (CurOp != NumOps) 896 emitConstant(MI.getOperand(CurOp++).getImm(), 897 X86II::getSizeOfImm(Desc->TSFlags)); 898 break; 899 } 900 901 case X86II::MRM0r: case X86II::MRM1r: 902 case X86II::MRM2r: case X86II::MRM3r: 903 case X86II::MRM4r: case X86II::MRM5r: 904 case X86II::MRM6r: case X86II::MRM7r: { 905 MCE.emitByte(BaseOpcode); 906 emitRegModRMByte(MI.getOperand(CurOp++).getReg(), 907 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r); 908 909 if (CurOp == NumOps) 910 break; 911 912 const MachineOperand &MO1 = MI.getOperand(CurOp++); 913 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 914 if (MO1.isImm()) { 915 emitConstant(MO1.getImm(), Size); 916 break; 917 } 918 919 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word 920 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 921 if (Opcode == X86::MOV64ri32) 922 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag? 923 if (MO1.isGlobal()) { 924 bool Indirect = gvNeedsNonLazyPtr(MO1, TM); 925 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, 926 Indirect); 927 } else if (MO1.isSymbol()) 928 emitExternalSymbolAddress(MO1.getSymbolName(), rt); 929 else if (MO1.isCPI()) 930 emitConstPoolAddress(MO1.getIndex(), rt); 931 else if (MO1.isJTI()) 932 emitJumpTableAddress(MO1.getIndex(), rt); 933 break; 934 } 935 936 case X86II::MRM0m: case X86II::MRM1m: 937 case X86II::MRM2m: case X86II::MRM3m: 938 case X86II::MRM4m: case X86II::MRM5m: 939 case X86II::MRM6m: case X86II::MRM7m: { 940 intptr_t PCAdj = (CurOp + X86::AddrNumOperands != NumOps) ? 941 (MI.getOperand(CurOp+X86::AddrNumOperands).isImm() ? 942 X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0; 943 944 MCE.emitByte(BaseOpcode); 945 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m, 946 PCAdj); 947 CurOp += X86::AddrNumOperands; 948 949 if (CurOp == NumOps) 950 break; 951 952 const MachineOperand &MO = MI.getOperand(CurOp++); 953 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 954 if (MO.isImm()) { 955 emitConstant(MO.getImm(), Size); 956 break; 957 } 958 959 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word 960 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 961 if (Opcode == X86::MOV64mi32) 962 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag? 963 if (MO.isGlobal()) { 964 bool Indirect = gvNeedsNonLazyPtr(MO, TM); 965 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0, 966 Indirect); 967 } else if (MO.isSymbol()) 968 emitExternalSymbolAddress(MO.getSymbolName(), rt); 969 else if (MO.isCPI()) 970 emitConstPoolAddress(MO.getIndex(), rt); 971 else if (MO.isJTI()) 972 emitJumpTableAddress(MO.getIndex(), rt); 973 break; 974 } 975 976 case X86II::MRMInitReg: 977 MCE.emitByte(BaseOpcode); 978 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg). 979 emitRegModRMByte(MI.getOperand(CurOp).getReg(), 980 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg())); 981 ++CurOp; 982 break; 983 984 case X86II::MRM_C1: 985 MCE.emitByte(BaseOpcode); 986 MCE.emitByte(0xC1); 987 break; 988 case X86II::MRM_C8: 989 MCE.emitByte(BaseOpcode); 990 MCE.emitByte(0xC8); 991 break; 992 case X86II::MRM_C9: 993 MCE.emitByte(BaseOpcode); 994 MCE.emitByte(0xC9); 995 break; 996 case X86II::MRM_E8: 997 MCE.emitByte(BaseOpcode); 998 MCE.emitByte(0xE8); 999 break; 1000 case X86II::MRM_F0: 1001 MCE.emitByte(BaseOpcode); 1002 MCE.emitByte(0xF0); 1003 break; 1004 } 1005 1006 if (!Desc->isVariadic() && CurOp != NumOps) { 1007#ifndef NDEBUG 1008 dbgs() << "Cannot encode all operands of: " << MI << "\n"; 1009#endif 1010 llvm_unreachable(0); 1011 } 1012 1013 MCE.processDebugLoc(MI.getDebugLoc(), false); 1014} 1015