X86.td revision 226633 
1//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This is a target description file for the Intel i386 architecture, referred
11// to here as the "X86" architecture.
12//
13//===----------------------------------------------------------------------===//
14
15// Get the target-independent interfaces which we are implementing...
16//
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// X86 Subtarget state.
21//
22
23def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
24                                  "64-bit mode (x86_64)">;
25
26def ModeNaCl  : SubtargetFeature<"nacl-mode", "InNaClMode", "true",
27                                 "Native Client mode">;
28
29//===----------------------------------------------------------------------===//
30// X86 Subtarget features.
31//===----------------------------------------------------------------------===//
32
33def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
34                                      "Enable conditional move instructions">;
35
36def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
37                                       "Support POPCNT instruction">;
38
39
40def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
41                                      "Enable MMX instructions">;
42def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
43                                      "Enable SSE instructions",
44                                      // SSE codegen depends on cmovs, and all
45                                      // SSE1+ processors support them.
46                                      [FeatureMMX, FeatureCMOV]>;
47def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
48                                      "Enable SSE2 instructions",
49                                      [FeatureSSE1]>;
50def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
51                                      "Enable SSE3 instructions",
52                                      [FeatureSSE2]>;
53def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
54                                      "Enable SSSE3 instructions",
55                                      [FeatureSSE3]>;
56def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
57                                      "Enable SSE 4.1 instructions",
58                                      [FeatureSSSE3]>;
59def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
60                                      "Enable SSE 4.2 instructions",
61                                      [FeatureSSE41, FeaturePOPCNT]>;
62def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
63                                      "Enable 3DNow! instructions",
64                                      [FeatureMMX]>;
65def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
66                                      "Enable 3DNow! Athlon instructions",
67                                      [Feature3DNow]>;
68// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
69// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
70// without disabling 64-bit mode.
71def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
72                                      "Support 64-bit instructions",
73                                      [FeatureCMOV]>;
74def FeatureCMPXCHG16B : SubtargetFeature<"cmpxchg16b", "HasCmpxchg16b", "true",
75                                      "64-bit with cmpxchg16b",
76                                      [Feature64Bit]>;
77def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
78                                       "Bit testing of memory is slow">;
79def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
80                                        "IsUAMemFast", "true",
81                                        "Fast unaligned memory access">;
82def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
83                                      "Support SSE 4a instructions",
84                                      [FeaturePOPCNT]>;
85
86def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",
87                                      "Enable AVX instructions">;
88def FeatureCLMUL   : SubtargetFeature<"clmul", "HasCLMUL", "true",
89                               "Enable carry-less multiplication instructions">;
90def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
91                                     "Enable three-operand fused multiple-add">;
92def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
93                                      "Enable four-operand fused multiple-add">;
94def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
95                                          "HasVectorUAMem", "true",
96                 "Allow unaligned memory operands on vector/SIMD instructions">;
97def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
98                                      "Enable AES instructions">;
99def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
100                                      "Support MOVBE instruction">;
101def FeatureRDRAND  : SubtargetFeature<"rdrand", "HasRDRAND", "true",
102                                      "Support RDRAND instruction">;
103def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
104                       "Support 16-bit floating point conversion instructions">;
105def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
106                                      "Support LZCNT instruction">;
107def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
108                                      "Support BMI instructions">;
109
110//===----------------------------------------------------------------------===//
111// X86 processors supported.
112//===----------------------------------------------------------------------===//
113
114class Proc<string Name, list<SubtargetFeature> Features>
115 : Processor<Name, NoItineraries, Features>;
116
117def : Proc<"generic",         []>;
118def : Proc<"i386",            []>;
119def : Proc<"i486",            []>;
120def : Proc<"i586",            []>;
121def : Proc<"pentium",         []>;
122def : Proc<"pentium-mmx",     [FeatureMMX]>;
123def : Proc<"i686",            []>;
124def : Proc<"pentiumpro",      [FeatureCMOV]>;
125def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
126def : Proc<"pentium3",        [FeatureSSE1]>;
127def : Proc<"pentium3m",       [FeatureSSE1, FeatureSlowBTMem]>;
128def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
129def : Proc<"pentium4",        [FeatureSSE2]>;
130def : Proc<"pentium4m",       [FeatureSSE2, FeatureSlowBTMem]>;
131def : Proc<"x86-64",          [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
132def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
133def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
134def : Proc<"nocona",          [FeatureSSE3, FeatureCMPXCHG16B,
135                               FeatureSlowBTMem]>;
136def : Proc<"core2",           [FeatureSSSE3, FeatureCMPXCHG16B,
137                               FeatureSlowBTMem]>;
138def : Proc<"penryn",          [FeatureSSE41, FeatureCMPXCHG16B,
139                               FeatureSlowBTMem]>;
140def : Proc<"atom",            [FeatureSSE3, FeatureCMPXCHG16B, FeatureMOVBE,
141                               FeatureSlowBTMem]>;
142// "Arrandale" along with corei3 and corei5
143def : Proc<"corei7",          [FeatureSSE42, FeatureCMPXCHG16B,
144                               FeatureSlowBTMem, FeatureFastUAMem, FeatureAES]>;
145def : Proc<"nehalem",         [FeatureSSE42,  FeatureCMPXCHG16B,
146                               FeatureSlowBTMem, FeatureFastUAMem]>;
147// Westmere is a similar machine to nehalem with some additional features.
148// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
149def : Proc<"westmere",        [FeatureSSE42, FeatureCMPXCHG16B,
150                               FeatureSlowBTMem, FeatureFastUAMem, FeatureAES,
151                               FeatureCLMUL]>;
152// Sandy Bridge
153// SSE is not listed here since llvm treats AVX as a reimplementation of SSE,
154// rather than a superset.
155// FIXME: Disabling AVX for now since it's not ready.
156def : Proc<"corei7-avx",      [FeatureSSE42, FeatureCMPXCHG16B,
157                               FeatureAES, FeatureCLMUL]>;
158// Ivy Bridge
159def : Proc<"core-avx-i",      [FeatureSSE42, FeatureCMPXCHG16B,
160                               FeatureAES, FeatureCLMUL,
161                               FeatureRDRAND, FeatureF16C]>;
162
163// Haswell
164def : Proc<"core-avx2",       [FeatureSSE42, FeatureCMPXCHG16B, FeatureAES,
165                               FeatureCLMUL, FeatureRDRAND, FeatureF16C,
166                               FeatureFMA3, FeatureMOVBE, FeatureLZCNT,
167                               FeatureBMI]>;
168
169def : Proc<"k6",              [FeatureMMX]>;
170def : Proc<"k6-2",            [Feature3DNow]>;
171def : Proc<"k6-3",            [Feature3DNow]>;
172def : Proc<"athlon",          [Feature3DNowA, FeatureSlowBTMem]>;
173def : Proc<"athlon-tbird",    [Feature3DNowA, FeatureSlowBTMem]>;
174def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
175def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
176def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
177def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
178                               FeatureSlowBTMem]>;
179def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
180                               FeatureSlowBTMem]>;
181def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
182                               FeatureSlowBTMem]>;
183def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
184                               FeatureSlowBTMem]>;
185def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
186                               FeatureSlowBTMem]>;
187def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
188                               FeatureSlowBTMem]>;
189def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
190                               FeatureSlowBTMem]>;
191def : Proc<"amdfam10",        [FeatureSSE3,   FeatureSSE4A,
192                               Feature3DNowA, FeatureCMPXCHG16B,
193                               FeatureSlowBTMem]>;
194def : Proc<"barcelona",       [FeatureSSE3,   FeatureSSE4A,
195                               Feature3DNowA, FeatureCMPXCHG16B,
196                               FeatureSlowBTMem]>;
197def : Proc<"istanbul",        [Feature3DNowA, FeatureCMPXCHG16B,
198                               FeatureSSE4A, Feature3DNowA]>;
199def : Proc<"shanghai",        [Feature3DNowA, FeatureCMPXCHG16B, FeatureSSE4A,
200                               Feature3DNowA]>;
201
202def : Proc<"winchip-c6",      [FeatureMMX]>;
203def : Proc<"winchip2",        [Feature3DNow]>;
204def : Proc<"c3",              [Feature3DNow]>;
205def : Proc<"c3-2",            [FeatureSSE1]>;
206
207//===----------------------------------------------------------------------===//
208// Register File Description
209//===----------------------------------------------------------------------===//
210
211include "X86RegisterInfo.td"
212
213//===----------------------------------------------------------------------===//
214// Instruction Descriptions
215//===----------------------------------------------------------------------===//
216
217include "X86InstrInfo.td"
218
219def X86InstrInfo : InstrInfo;
220
221//===----------------------------------------------------------------------===//
222// Calling Conventions
223//===----------------------------------------------------------------------===//
224
225include "X86CallingConv.td"
226
227
228//===----------------------------------------------------------------------===//
229// Assembly Parser
230//===----------------------------------------------------------------------===//
231
232// Currently the X86 assembly parser only supports ATT syntax.
233def ATTAsmParser : AsmParser {
234  string AsmParserClassName = "ATTAsmParser";
235  int Variant = 0;
236
237  // Discard comments in assembly strings.
238  string CommentDelimiter = "#";
239
240  // Recognize hard coded registers.
241  string RegisterPrefix = "%";
242}
243
244//===----------------------------------------------------------------------===//
245// Assembly Printers
246//===----------------------------------------------------------------------===//
247
248// The X86 target supports two different syntaxes for emitting machine code.
249// This is controlled by the -x86-asm-syntax={att|intel}
250def ATTAsmWriter : AsmWriter {
251  string AsmWriterClassName  = "ATTInstPrinter";
252  int Variant = 0;
253  bit isMCAsmWriter = 1;
254}
255def IntelAsmWriter : AsmWriter {
256  string AsmWriterClassName  = "IntelInstPrinter";
257  int Variant = 1;
258  bit isMCAsmWriter = 1;
259}
260
261def X86 : Target {
262  // Information about the instructions...
263  let InstructionSet = X86InstrInfo;
264
265  let AssemblyParsers = [ATTAsmParser];
266
267  let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
268}
269