X86.td revision 223017
122514Sdarrenr//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===// 222514Sdarrenr// 322514Sdarrenr// The LLVM Compiler Infrastructure 422514Sdarrenr// 522514Sdarrenr// This file is distributed under the University of Illinois Open Source 622514Sdarrenr// License. See LICENSE.TXT for details. 722514Sdarrenr// 822514Sdarrenr//===----------------------------------------------------------------------===// 922514Sdarrenr// 1022514Sdarrenr// This is a target description file for the Intel i386 architecture, referred to 1122514Sdarrenr// here as the "X86" architecture. 1222514Sdarrenr// 1322514Sdarrenr//===----------------------------------------------------------------------===// 1422514Sdarrenr 1522514Sdarrenr// Get the target-independent interfaces which we are implementing... 1622514Sdarrenr// 1722514Sdarrenrinclude "llvm/Target/Target.td" 1822514Sdarrenr 1922514Sdarrenr//===----------------------------------------------------------------------===// 2022514Sdarrenr// X86 Subtarget features. 2122514Sdarrenr//===----------------------------------------------------------------------===// 2222514Sdarrenr 2322514Sdarrenrdef FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", 2422514Sdarrenr "Enable conditional move instructions">; 2522514Sdarrenr 2622514Sdarrenrdef FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", 2722514Sdarrenr "Support POPCNT instruction">; 2822514Sdarrenr 2922514Sdarrenr 3022514Sdarrenrdef FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", 3122514Sdarrenr "Enable MMX instructions">; 3222514Sdarrenrdef FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", 3322514Sdarrenr "Enable SSE instructions", 3422514Sdarrenr // SSE codegen depends on cmovs, and all 3522514Sdarrenr // SSE1+ processors support them. 3622514Sdarrenr [FeatureMMX, FeatureCMOV]>; 3722514Sdarrenrdef FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", 3822514Sdarrenr "Enable SSE2 instructions", 3922514Sdarrenr [FeatureSSE1]>; 4022514Sdarrenrdef FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", 4122514Sdarrenr "Enable SSE3 instructions", 4222514Sdarrenr [FeatureSSE2]>; 4322514Sdarrenrdef FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", 4422514Sdarrenr "Enable SSSE3 instructions", 4522514Sdarrenr [FeatureSSE3]>; 4622514Sdarrenrdef FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41", 4722514Sdarrenr "Enable SSE 4.1 instructions", 4822514Sdarrenr [FeatureSSSE3]>; 4922514Sdarrenrdef FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42", 5022514Sdarrenr "Enable SSE 4.2 instructions", 5122514Sdarrenr [FeatureSSE41, FeaturePOPCNT]>; 5222514Sdarrenrdef Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", 5322514Sdarrenr "Enable 3DNow! instructions", 5422514Sdarrenr [FeatureMMX]>; 5522514Sdarrenrdef Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", 5622514Sdarrenr "Enable 3DNow! Athlon instructions", 5722514Sdarrenr [Feature3DNow]>; 5824583Sdarrenr// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied 5922514Sdarrenr// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) 6024583Sdarrenr// without disabling 64-bit mode. 6122514Sdarrenrdef Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", 6222514Sdarrenr "Support 64-bit instructions", 6322514Sdarrenr [FeatureCMOV]>; 6422514Sdarrenrdef FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true", 6522514Sdarrenr "Bit testing of memory is slow">; 6622514Sdarrenrdef FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem", 6722514Sdarrenr "IsUAMemFast", "true", 6822514Sdarrenr "Fast unaligned memory access">; 6922514Sdarrenrdef FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", 7022514Sdarrenr "Support SSE 4a instructions", 7122514Sdarrenr [FeaturePOPCNT]>; 7222514Sdarrenr 7322514Sdarrenrdef FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true", 7422514Sdarrenr "Enable AVX instructions">; 7522514Sdarrenrdef FeatureCLMUL : SubtargetFeature<"clmul", "HasCLMUL", "true", 7622514Sdarrenr "Enable carry-less multiplication instructions">; 7722514Sdarrenrdef FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true", 7822514Sdarrenr "Enable three-operand fused multiple-add">; 7922514Sdarrenrdef FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", 8022514Sdarrenr "Enable four-operand fused multiple-add">; 8122514Sdarrenrdef FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", 8222514Sdarrenr "HasVectorUAMem", "true", 8322514Sdarrenr "Allow unaligned memory operands on vector/SIMD instructions">; 8422514Sdarrenrdef FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 8522514Sdarrenr "Enable AES instructions">; 8622514Sdarrenr 8722514Sdarrenr//===----------------------------------------------------------------------===// 8822514Sdarrenr// X86 processors supported. 8922514Sdarrenr//===----------------------------------------------------------------------===// 9022514Sdarrenr 9122514Sdarrenrclass Proc<string Name, list<SubtargetFeature> Features> 9222514Sdarrenr : Processor<Name, NoItineraries, Features>; 9322514Sdarrenr 9422514Sdarrenrdef : Proc<"generic", []>; 9522514Sdarrenrdef : Proc<"i386", []>; 9622514Sdarrenrdef : Proc<"i486", []>; 9722514Sdarrenrdef : Proc<"i586", []>; 9822514Sdarrenrdef : Proc<"pentium", []>; 9922514Sdarrenrdef : Proc<"pentium-mmx", [FeatureMMX]>; 10022514Sdarrenrdef : Proc<"i686", []>; 10122514Sdarrenrdef : Proc<"pentiumpro", [FeatureCMOV]>; 10222514Sdarrenrdef : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>; 10322514Sdarrenrdef : Proc<"pentium3", [FeatureSSE1]>; 10422514Sdarrenrdef : Proc<"pentium3m", [FeatureSSE1, FeatureSlowBTMem]>; 10522514Sdarrenrdef : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>; 10622514Sdarrenrdef : Proc<"pentium4", [FeatureSSE2]>; 10722514Sdarrenrdef : Proc<"pentium4m", [FeatureSSE2, FeatureSlowBTMem]>; 10822514Sdarrenrdef : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>; 10922514Sdarrenrdef : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>; 11022514Sdarrenrdef : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>; 11122514Sdarrenrdef : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; 11222514Sdarrenrdef : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>; 11322514Sdarrenrdef : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>; 11422514Sdarrenrdef : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; 11522514Sdarrenr// "Arrandale" along with corei3 and corei5 11622514Sdarrenrdef : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem, 11722514Sdarrenr FeatureFastUAMem, FeatureAES]>; 11822514Sdarrenrdef : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem, 11922514Sdarrenr FeatureFastUAMem]>; 12022514Sdarrenr// Westmere is a similar machine to nehalem with some additional features. 12122514Sdarrenr// Westmere is the corei3/i5/i7 path from nehalem to sandybridge 12222514Sdarrenrdef : Proc<"westmere", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem, 12322514Sdarrenr FeatureFastUAMem, FeatureAES, FeatureCLMUL]>; 12422514Sdarrenr// SSE is not listed here since llvm treats AVX as a reimplementation of SSE, 12522514Sdarrenr// rather than a superset. 12622514Sdarrenr// FIXME: Disabling AVX for now since it's not ready. 12722514Sdarrenrdef : Proc<"corei7-avx", [FeatureSSE42, Feature64Bit, 12822514Sdarrenr FeatureAES, FeatureCLMUL]>; 12922514Sdarrenr 13022514Sdarrenrdef : Proc<"k6", [FeatureMMX]>; 13122514Sdarrenrdef : Proc<"k6-2", [Feature3DNow]>; 13222514Sdarrenrdef : Proc<"k6-3", [Feature3DNow]>; 13322514Sdarrenrdef : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>; 13422514Sdarrenrdef : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>; 13522514Sdarrenrdef : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 13622514Sdarrenrdef : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 13722514Sdarrenrdef : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 13822514Sdarrenrdef : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit, 13922514Sdarrenr FeatureSlowBTMem]>; 14022514Sdarrenrdef : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit, 14122514Sdarrenr FeatureSlowBTMem]>; 14222514Sdarrenrdef : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit, 14322514Sdarrenr FeatureSlowBTMem]>; 14422514Sdarrenrdef : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit, 14522514Sdarrenr FeatureSlowBTMem]>; 14622514Sdarrenrdef : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, 14722514Sdarrenr FeatureSlowBTMem]>; 14822514Sdarrenrdef : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, 14922514Sdarrenr FeatureSlowBTMem]>; 15022514Sdarrenrdef : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, 15122514Sdarrenr FeatureSlowBTMem]>; 15222514Sdarrenrdef : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A, 15322514Sdarrenr Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; 15422514Sdarrenrdef : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A, 15522514Sdarrenr Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; 15622514Sdarrenrdef : Proc<"istanbul", [Feature3DNowA, Feature64Bit, FeatureSSE4A, 15722514Sdarrenr Feature3DNowA]>; 15822514Sdarrenrdef : Proc<"shanghai", [Feature3DNowA, Feature64Bit, FeatureSSE4A, 15922514Sdarrenr Feature3DNowA]>; 16022514Sdarrenr 16122514Sdarrenrdef : Proc<"winchip-c6", [FeatureMMX]>; 16222514Sdarrenrdef : Proc<"winchip2", [Feature3DNow]>; 16322514Sdarrenrdef : Proc<"c3", [Feature3DNow]>; 16422514Sdarrenrdef : Proc<"c3-2", [FeatureSSE1]>; 16522514Sdarrenr 16622514Sdarrenr//===----------------------------------------------------------------------===// 16722514Sdarrenr// Register File Description 16822514Sdarrenr//===----------------------------------------------------------------------===// 16922514Sdarrenr 17022514Sdarrenrinclude "X86RegisterInfo.td" 17122514Sdarrenr 17222514Sdarrenr//===----------------------------------------------------------------------===// 17324583Sdarrenr// Instruction Descriptions 17424583Sdarrenr//===----------------------------------------------------------------------===// 17522514Sdarrenr 17622514Sdarrenrinclude "X86InstrInfo.td" 17722514Sdarrenr 17822514Sdarrenrdef X86InstrInfo : InstrInfo; 17922514Sdarrenr 18022514Sdarrenr//===----------------------------------------------------------------------===// 18122514Sdarrenr// Calling Conventions 18222514Sdarrenr//===----------------------------------------------------------------------===// 18322514Sdarrenr 18422514Sdarrenrinclude "X86CallingConv.td" 18524583Sdarrenr 18624583Sdarrenr 18722514Sdarrenr//===----------------------------------------------------------------------===// 18822514Sdarrenr// Assembly Parser 18922514Sdarrenr//===----------------------------------------------------------------------===// 19022514Sdarrenr 19122514Sdarrenr// Currently the X86 assembly parser only supports ATT syntax. 19222514Sdarrenrdef ATTAsmParser : AsmParser { 19322514Sdarrenr string AsmParserClassName = "ATTAsmParser"; 19422514Sdarrenr int Variant = 0; 19522514Sdarrenr 19622514Sdarrenr // Discard comments in assembly strings. 19722514Sdarrenr string CommentDelimiter = "#"; 19822514Sdarrenr 19922514Sdarrenr // Recognize hard coded registers. 20022514Sdarrenr string RegisterPrefix = "%"; 20122514Sdarrenr} 20222514Sdarrenr 20322514Sdarrenr//===----------------------------------------------------------------------===// 20424583Sdarrenr// Assembly Printers 20524583Sdarrenr//===----------------------------------------------------------------------===// 20622514Sdarrenr 20722514Sdarrenr// The X86 target supports two different syntaxes for emitting machine code. 20822514Sdarrenr// This is controlled by the -x86-asm-syntax={att|intel} 20922514Sdarrenrdef ATTAsmWriter : AsmWriter { 21022514Sdarrenr string AsmWriterClassName = "ATTInstPrinter"; 21122514Sdarrenr int Variant = 0; 21222514Sdarrenr bit isMCAsmWriter = 1; 21322514Sdarrenr} 21422514Sdarrenrdef IntelAsmWriter : AsmWriter { 21522514Sdarrenr string AsmWriterClassName = "IntelInstPrinter"; 21624583Sdarrenr int Variant = 1; 21724583Sdarrenr bit isMCAsmWriter = 1; 21822514Sdarrenr} 21922514Sdarrenr 22022514Sdarrenrdef X86 : Target { 22122514Sdarrenr // Information about the instructions... 22222514Sdarrenr let InstructionSet = X86InstrInfo; 22322514Sdarrenr 22422514Sdarrenr let AssemblyParsers = [ATTAsmParser]; 22522514Sdarrenr 22622514Sdarrenr let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; 22722514Sdarrenr} 22822514Sdarrenr