X86.td revision 206274 
1//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10// This is a target description file for the Intel i386 architecture, refered to
11// here as the "X86" architecture.
12//
13//===----------------------------------------------------------------------===//
14
15// Get the target-independent interfaces which we are implementing...
16//
17include "llvm/Target/Target.td"
18
19//===----------------------------------------------------------------------===//
20// X86 Subtarget features.
21//===----------------------------------------------------------------------===//
22
23def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
24                                      "Enable conditional move instructions">;
25
26
27def FeatureMMX     : SubtargetFeature<"mmx","X86SSELevel", "MMX",
28                                      "Enable MMX instructions">;
29def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
30                                      "Enable SSE instructions",
31                                      // SSE codegen depends on cmovs, and all
32                                      // SSE1+ processors support them. 
33                                      [FeatureMMX, FeatureCMOV]>;
34def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
35                                      "Enable SSE2 instructions",
36                                      [FeatureSSE1]>;
37def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
38                                      "Enable SSE3 instructions",
39                                      [FeatureSSE2]>;
40def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
41                                      "Enable SSSE3 instructions",
42                                      [FeatureSSE3]>;
43def FeatureSSE41   : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
44                                      "Enable SSE 4.1 instructions",
45                                      [FeatureSSSE3]>;
46def FeatureSSE42   : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
47                                      "Enable SSE 4.2 instructions",
48                                      [FeatureSSE41]>;
49def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
50                                      "Enable 3DNow! instructions">;
51def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
52                                      "Enable 3DNow! Athlon instructions",
53                                      [Feature3DNow]>;
54// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
55// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
56// without disabling 64-bit mode.
57def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
58                                      "Support 64-bit instructions",
59                                      [FeatureCMOV]>;
60def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
61                                       "Bit testing of memory is slow">;
62def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
63                                        "IsUAMemFast", "true",
64                                        "Fast unaligned memory access">;
65def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
66                                      "Support SSE 4a instructions">;
67
68def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",
69                                      "Enable AVX instructions">;
70def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
71                                     "Enable three-operand fused multiple-add">;
72def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
73                                      "Enable four-operand fused multiple-add">;
74def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
75                                          "HasVectorUAMem", "true",
76                 "Allow unaligned memory operands on vector/SIMD instructions">;
77def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
78                                      "Enable AES instructions">;
79
80//===----------------------------------------------------------------------===//
81// X86 processors supported.
82//===----------------------------------------------------------------------===//
83
84class Proc<string Name, list<SubtargetFeature> Features>
85 : Processor<Name, NoItineraries, Features>;
86
87def : Proc<"generic",         []>;
88def : Proc<"i386",            []>;
89def : Proc<"i486",            []>;
90def : Proc<"i586",            []>;
91def : Proc<"pentium",         []>;
92def : Proc<"pentium-mmx",     [FeatureMMX]>;
93def : Proc<"i686",            []>;
94def : Proc<"pentiumpro",      [FeatureCMOV]>;
95def : Proc<"pentium2",        [FeatureMMX, FeatureCMOV]>;
96def : Proc<"pentium3",        [FeatureSSE1]>;
97def : Proc<"pentium-m",       [FeatureSSE2, FeatureSlowBTMem]>;
98def : Proc<"pentium4",        [FeatureSSE2]>;
99def : Proc<"x86-64",          [FeatureSSE2,   Feature64Bit, FeatureSlowBTMem]>;
100def : Proc<"yonah",           [FeatureSSE3, FeatureSlowBTMem]>;
101def : Proc<"prescott",        [FeatureSSE3, FeatureSlowBTMem]>;
102def : Proc<"nocona",          [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
103def : Proc<"core2",           [FeatureSSSE3,  Feature64Bit, FeatureSlowBTMem]>;
104def : Proc<"penryn",          [FeatureSSE41,  Feature64Bit, FeatureSlowBTMem]>;
105def : Proc<"atom",            [FeatureSSE3,   Feature64Bit, FeatureSlowBTMem]>;
106// "Arrandale" along with corei3 and corei5
107def : Proc<"corei7",          [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem,
108                               FeatureFastUAMem, FeatureAES]>;
109def : Proc<"nehalem",         [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem,
110                               FeatureFastUAMem]>;
111// Westmere is a similar machine to nehalem with some additional features.
112// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
113def : Proc<"westmere",         [FeatureSSE42,  Feature64Bit, FeatureSlowBTMem,
114                                FeatureFastUAMem, FeatureAES]>;
115// Sandy Bridge does not have FMA
116// FIXME: Wikipedia says it does... it should have AES as well.
117def : Proc<"sandybridge",     [FeatureSSE42,  FeatureAVX,   Feature64Bit]>;
118
119def : Proc<"k6",              [FeatureMMX]>;
120def : Proc<"k6-2",            [FeatureMMX,    Feature3DNow]>;
121def : Proc<"k6-3",            [FeatureMMX,    Feature3DNow]>;
122def : Proc<"athlon",          [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
123def : Proc<"athlon-tbird",    [FeatureMMX,    Feature3DNowA, FeatureSlowBTMem]>;
124def : Proc<"athlon-4",        [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
125def : Proc<"athlon-xp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
126def : Proc<"athlon-mp",       [FeatureSSE1,   Feature3DNowA, FeatureSlowBTMem]>;
127def : Proc<"k8",              [FeatureSSE2,   Feature3DNowA, Feature64Bit,
128                               FeatureSlowBTMem]>;
129def : Proc<"opteron",         [FeatureSSE2,   Feature3DNowA, Feature64Bit,
130                               FeatureSlowBTMem]>;
131def : Proc<"athlon64",        [FeatureSSE2,   Feature3DNowA, Feature64Bit,
132                               FeatureSlowBTMem]>;
133def : Proc<"athlon-fx",       [FeatureSSE2,   Feature3DNowA, Feature64Bit,
134                               FeatureSlowBTMem]>;
135def : Proc<"k8-sse3",         [FeatureSSE3,   Feature3DNowA, Feature64Bit,
136                               FeatureSlowBTMem]>;
137def : Proc<"opteron-sse3",    [FeatureSSE3,   Feature3DNowA, Feature64Bit,
138                               FeatureSlowBTMem]>;
139def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, Feature64Bit,
140                               FeatureSlowBTMem]>;
141def : Proc<"amdfam10",        [FeatureSSE3,   FeatureSSE4A,
142                               Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
143def : Proc<"barcelona",       [FeatureSSE3,   FeatureSSE4A,
144                               Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
145def : Proc<"istanbul",        [Feature3DNowA, Feature64Bit, FeatureSSE4A,
146                               Feature3DNowA]>;
147def : Proc<"shanghai",        [Feature3DNowA, Feature64Bit, FeatureSSE4A,
148                               Feature3DNowA]>;
149
150def : Proc<"winchip-c6",      [FeatureMMX]>;
151def : Proc<"winchip2",        [FeatureMMX, Feature3DNow]>;
152def : Proc<"c3",              [FeatureMMX, Feature3DNow]>;
153def : Proc<"c3-2",            [FeatureSSE1]>;
154
155//===----------------------------------------------------------------------===//
156// Register File Description
157//===----------------------------------------------------------------------===//
158
159include "X86RegisterInfo.td"
160
161//===----------------------------------------------------------------------===//
162// Instruction Descriptions
163//===----------------------------------------------------------------------===//
164
165include "X86InstrInfo.td"
166
167def X86InstrInfo : InstrInfo;
168
169//===----------------------------------------------------------------------===//
170// Calling Conventions
171//===----------------------------------------------------------------------===//
172
173include "X86CallingConv.td"
174
175
176//===----------------------------------------------------------------------===//
177// Assembly Printers
178//===----------------------------------------------------------------------===//
179
180// Currently the X86 assembly parser only supports ATT syntax.
181def ATTAsmParser : AsmParser {
182  string AsmParserClassName  = "ATTAsmParser";
183  string AsmParserInstCleanup  = "InstructionCleanup";
184  int Variant = 0;
185
186  // Discard comments in assembly strings.
187  string CommentDelimiter = "#";
188
189  // Recognize hard coded registers.
190  string RegisterPrefix = "%";
191}
192
193// The X86 target supports two different syntaxes for emitting machine code.
194// This is controlled by the -x86-asm-syntax={att|intel}
195def ATTAsmWriter : AsmWriter {
196  string AsmWriterClassName  = "ATTInstPrinter";
197  int Variant = 0;
198}
199def IntelAsmWriter : AsmWriter {
200  string AsmWriterClassName  = "IntelInstPrinter";
201  int Variant = 1;
202}
203
204def X86 : Target {
205  // Information about the instructions...
206  let InstructionSet = X86InstrInfo;
207
208  let AssemblyParsers = [ATTAsmParser];
209
210  let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
211}
212