X86.td revision 205218
11558Srgrimes//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===// 21558Srgrimes// 31558Srgrimes// The LLVM Compiler Infrastructure 41558Srgrimes// 51558Srgrimes// This file is distributed under the University of Illinois Open Source 61558Srgrimes// License. See LICENSE.TXT for details. 71558Srgrimes// 81558Srgrimes//===----------------------------------------------------------------------===// 91558Srgrimes// 101558Srgrimes// This is a target description file for the Intel i386 architecture, refered to 111558Srgrimes// here as the "X86" architecture. 121558Srgrimes// 131558Srgrimes//===----------------------------------------------------------------------===// 141558Srgrimes 151558Srgrimes// Get the target-independent interfaces which we are implementing... 161558Srgrimes// 171558Srgrimesinclude "llvm/Target/Target.td" 181558Srgrimes 191558Srgrimes//===----------------------------------------------------------------------===// 201558Srgrimes// X86 Subtarget features. 211558Srgrimes//===----------------------------------------------------------------------===// 221558Srgrimes 231558Srgrimesdef FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", 241558Srgrimes "Enable conditional move instructions">; 251558Srgrimes 261558Srgrimes 271558Srgrimesdef FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", 281558Srgrimes "Enable MMX instructions">; 291558Srgrimesdef FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", 301558Srgrimes "Enable SSE instructions", 311558Srgrimes // SSE codegen depends on cmovs, and all 321558Srgrimes // SSE1+ processors support them. 331558Srgrimes [FeatureMMX, FeatureCMOV]>; 341558Srgrimesdef FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", 3536998Scharnier "Enable SSE2 instructions", 361558Srgrimes [FeatureSSE1]>; 371558Srgrimesdef FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", 381558Srgrimes "Enable SSE3 instructions", 391558Srgrimes [FeatureSSE2]>; 401558Srgrimesdef FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", 4136998Scharnier "Enable SSSE3 instructions", 4223673Speter [FeatureSSE3]>; 4336998Scharnierdef FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41", 4436998Scharnier "Enable SSE 4.1 instructions", 4550476Speter [FeatureSSSE3]>; 461558Srgrimesdef FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42", 471558Srgrimes "Enable SSE 4.2 instructions", 481558Srgrimes [FeatureSSE41]>; 491558Srgrimesdef Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", 501558Srgrimes "Enable 3DNow! instructions">; 511558Srgrimesdef Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", 521558Srgrimes "Enable 3DNow! Athlon instructions", 5323673Speter [Feature3DNow]>; 541558Srgrimes// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied 551558Srgrimes// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) 561558Srgrimes// without disabling 64-bit mode. 571558Srgrimesdef Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", 5823673Speter "Support 64-bit instructions", 591558Srgrimes [FeatureCMOV]>; 601558Srgrimesdef FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true", 611558Srgrimes "Bit testing of memory is slow">; 621558Srgrimesdef FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", 631558Srgrimes "Support SSE 4a instructions">; 641558Srgrimes 651558Srgrimesdef FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true", 661558Srgrimes "Enable AVX instructions">; 671558Srgrimesdef FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true", 681558Srgrimes "Enable three-operand fused multiple-add">; 691558Srgrimesdef FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", 701558Srgrimes "Enable four-operand fused multiple-add">; 711558Srgrimesdef FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", 721558Srgrimes "HasVectorUAMem", "true", 731558Srgrimes "Allow unaligned memory operands on vector/SIMD instructions">; 741558Srgrimes 751558Srgrimes//===----------------------------------------------------------------------===// 761558Srgrimes// X86 processors supported. 771558Srgrimes//===----------------------------------------------------------------------===// 781558Srgrimes 791558Srgrimesclass Proc<string Name, list<SubtargetFeature> Features> 801558Srgrimes : Processor<Name, NoItineraries, Features>; 811558Srgrimes 821558Srgrimesdef : Proc<"generic", []>; 831558Srgrimesdef : Proc<"i386", []>; 841558Srgrimesdef : Proc<"i486", []>; 851558Srgrimesdef : Proc<"i586", []>; 861558Srgrimesdef : Proc<"pentium", []>; 8723673Speterdef : Proc<"pentium-mmx", [FeatureMMX]>; 881558Srgrimesdef : Proc<"i686", []>; 891558Srgrimesdef : Proc<"pentiumpro", [FeatureCMOV]>; 901558Srgrimesdef : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>; 911558Srgrimesdef : Proc<"pentium3", [FeatureSSE1]>; 921558Srgrimesdef : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>; 931558Srgrimesdef : Proc<"pentium4", [FeatureSSE2]>; 941558Srgrimesdef : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>; 951558Srgrimesdef : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>; 961558Srgrimesdef : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>; 971558Srgrimesdef : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; 981558Srgrimesdef : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>; 991558Srgrimesdef : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>; 1001558Srgrimesdef : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; 1011558Srgrimesdef : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>; 1021558Srgrimesdef : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>; 1031558Srgrimes// Sandy Bridge does not have FMA 1041558Srgrimesdef : Proc<"sandybridge", [FeatureSSE42, FeatureAVX, Feature64Bit]>; 1051558Srgrimes 1061558Srgrimesdef : Proc<"k6", [FeatureMMX]>; 1071558Srgrimesdef : Proc<"k6-2", [FeatureMMX, Feature3DNow]>; 1081558Srgrimesdef : Proc<"k6-3", [FeatureMMX, Feature3DNow]>; 1091558Srgrimesdef : Proc<"athlon", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>; 1101558Srgrimesdef : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>; 11135341Srnordierdef : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 1121558Srgrimesdef : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 1131558Srgrimesdef : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 1141558Srgrimesdef : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit, 1151558Srgrimes FeatureSlowBTMem]>; 1161558Srgrimesdef : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit, 1171558Srgrimes FeatureSlowBTMem]>; 11835341Srnordierdef : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit, 1191558Srgrimes FeatureSlowBTMem]>; 1201558Srgrimesdef : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit, 12135341Srnordier FeatureSlowBTMem]>; 12235341Srnordierdef : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, 12335341Srnordier FeatureSlowBTMem]>; 12435341Srnordierdef : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, 12535341Srnordier FeatureSlowBTMem]>; 12635341Srnordierdef : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, 12723673Speter FeatureSlowBTMem]>; 12823673Speterdef : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A, 12923673Speter Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; 13023673Speterdef : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A, 13123673Speter Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; 13223673Speterdef : Proc<"istanbul", [Feature3DNowA, Feature64Bit, FeatureSSE4A, 1331558Srgrimes Feature3DNowA]>; 1341558Srgrimesdef : Proc<"shanghai", [Feature3DNowA, Feature64Bit, FeatureSSE4A, 1351558Srgrimes Feature3DNowA]>; 1361558Srgrimes 1371558Srgrimesdef : Proc<"winchip-c6", [FeatureMMX]>; 13848271Sphkdef : Proc<"winchip2", [FeatureMMX, Feature3DNow]>; 1391558Srgrimesdef : Proc<"c3", [FeatureMMX, Feature3DNow]>; 1401558Srgrimesdef : Proc<"c3-2", [FeatureSSE1]>; 1411558Srgrimes 1421558Srgrimes//===----------------------------------------------------------------------===// 1431558Srgrimes// Register File Description 1441558Srgrimes//===----------------------------------------------------------------------===// 1451558Srgrimes 1461558Srgrimesinclude "X86RegisterInfo.td" 1471558Srgrimes 1481558Srgrimes//===----------------------------------------------------------------------===// 1491558Srgrimes// Instruction Descriptions 1501558Srgrimes//===----------------------------------------------------------------------===// 1511558Srgrimes 1521558Srgrimesinclude "X86InstrInfo.td" 1531558Srgrimes 1541558Srgrimesdef X86InstrInfo : InstrInfo { 1551558Srgrimes 1561558Srgrimes // Define how we want to layout our TargetSpecific information field... This 1571558Srgrimes // should be kept up-to-date with the fields in the X86InstrInfo.h file. 15824346Speter let TSFlagsFields = ["FormBits", 15924346Speter "hasOpSizePrefix", 1601558Srgrimes "hasAdSizePrefix", 1611558Srgrimes "Prefix", 1621558Srgrimes "hasREX_WPrefix", 1631558Srgrimes "ImmTypeBits", 1641558Srgrimes "FPFormBits", 16527081Sbde "hasLockPrefix", 16627081Sbde "SegOvrBits", 1671558Srgrimes "Opcode"]; 1681558Srgrimes let TSFlagsShifts = [0, 1691558Srgrimes 6, 1701558Srgrimes 7, 1711558Srgrimes 8, 1721558Srgrimes 12, 1732154Sdg 13, 1742154Sdg 16, 17548875Smpp 19, 17648875Smpp 20, 17748875Smpp 24]; 17848875Smpp} 17948875Smpp 18048875Smpp//===----------------------------------------------------------------------===// 18148875Smpp// Calling Conventions 18248875Smpp//===----------------------------------------------------------------------===// 18348875Smpp 18448875Smppinclude "X86CallingConv.td" 18548875Smpp 1861558Srgrimes 1871558Srgrimes//===----------------------------------------------------------------------===// 1881558Srgrimes// Assembly Printers 1891558Srgrimes//===----------------------------------------------------------------------===// 1903270Sdg 1911558Srgrimes// Currently the X86 assembly parser only supports ATT syntax. 1921558Srgrimesdef ATTAsmParser : AsmParser { 1931558Srgrimes string AsmParserClassName = "ATTAsmParser"; 1941558Srgrimes int Variant = 0; 1951558Srgrimes 1961558Srgrimes // Discard comments in assembly strings. 1971558Srgrimes string CommentDelimiter = "#"; 1981558Srgrimes 1991558Srgrimes // Recognize hard coded registers. 2001558Srgrimes string RegisterPrefix = "%"; 2011558Srgrimes} 2021558Srgrimes 2031558Srgrimes// The X86 target supports two different syntaxes for emitting machine code. 2041558Srgrimes// This is controlled by the -x86-asm-syntax={att|intel} 2051558Srgrimesdef ATTAsmWriter : AsmWriter { 2061558Srgrimes string AsmWriterClassName = "ATTInstPrinter"; 2071558Srgrimes int Variant = 0; 2081558Srgrimes} 2091558Srgrimesdef IntelAsmWriter : AsmWriter { 2101558Srgrimes string AsmWriterClassName = "IntelInstPrinter"; 2111558Srgrimes int Variant = 1; 2121558Srgrimes} 21316603Speter 21416603Speterdef X86 : Target { 2151558Srgrimes // Information about the instructions... 2161558Srgrimes let InstructionSet = X86InstrInfo; 2171558Srgrimes 2181558Srgrimes let AssemblyParsers = [ATTAsmParser]; 2191558Srgrimes 2201558Srgrimes let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; 2211558Srgrimes} 2221558Srgrimes