X86.td revision 202375
1193323Sed//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This is a target description file for the Intel i386 architecture, refered to 11193323Sed// here as the "X86" architecture. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed// Get the target-independent interfaces which we are implementing... 16193323Sed// 17193323Sedinclude "llvm/Target/Target.td" 18193323Sed 19193323Sed//===----------------------------------------------------------------------===// 20193323Sed// X86 Subtarget features. 21193323Sed//===----------------------------------------------------------------------===// 22198090Srdivacky 23198090Srdivackydef FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", 24198090Srdivacky "Enable conditional move instructions">; 25198090Srdivacky 26202375Srdivacky 27193323Seddef FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", 28193323Sed "Enable MMX instructions">; 29193323Seddef FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", 30193323Sed "Enable SSE instructions", 31198090Srdivacky // SSE codegen depends on cmovs, and all 32198090Srdivacky // SSE1+ processors support them. 33198090Srdivacky [FeatureMMX, FeatureCMOV]>; 34193323Seddef FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", 35193323Sed "Enable SSE2 instructions", 36193323Sed [FeatureSSE1]>; 37193323Seddef FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", 38193323Sed "Enable SSE3 instructions", 39193323Sed [FeatureSSE2]>; 40193323Seddef FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", 41193323Sed "Enable SSSE3 instructions", 42193323Sed [FeatureSSE3]>; 43193323Seddef FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41", 44193323Sed "Enable SSE 4.1 instructions", 45193323Sed [FeatureSSSE3]>; 46193323Seddef FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42", 47193323Sed "Enable SSE 4.2 instructions", 48193323Sed [FeatureSSE41]>; 49193323Seddef Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", 50193323Sed "Enable 3DNow! instructions">; 51193323Seddef Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", 52193323Sed "Enable 3DNow! Athlon instructions", 53193323Sed [Feature3DNow]>; 54193323Sed// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied 55193323Sed// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) 56193323Sed// without disabling 64-bit mode. 57193323Seddef Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", 58193323Sed "Support 64-bit instructions">; 59193323Seddef FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true", 60193323Sed "Bit testing of memory is slow">; 61193323Seddef FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", 62193323Sed "Support SSE 4a instructions">; 63193323Sed 64195098Seddef FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true", 65195098Sed "Enable AVX instructions">; 66195098Seddef FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true", 67201360Srdivacky "Enable three-operand fused multiple-add">; 68195098Seddef FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", 69195098Sed "Enable four-operand fused multiple-add">; 70202375Srdivackydef FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem", 71202375Srdivacky "HasVectorUAMem", "true", 72202375Srdivacky "Allow unaligned memory operands on vector/SIMD instructions">; 73195098Sed 74193323Sed//===----------------------------------------------------------------------===// 75193323Sed// X86 processors supported. 76193323Sed//===----------------------------------------------------------------------===// 77193323Sed 78193323Sedclass Proc<string Name, list<SubtargetFeature> Features> 79193323Sed : Processor<Name, NoItineraries, Features>; 80193323Sed 81193323Seddef : Proc<"generic", []>; 82193323Seddef : Proc<"i386", []>; 83193323Seddef : Proc<"i486", []>; 84193323Seddef : Proc<"i586", []>; 85193323Seddef : Proc<"pentium", []>; 86193323Seddef : Proc<"pentium-mmx", [FeatureMMX]>; 87193323Seddef : Proc<"i686", []>; 88198090Srdivackydef : Proc<"pentiumpro", [FeatureCMOV]>; 89198090Srdivackydef : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>; 90193323Seddef : Proc<"pentium3", [FeatureSSE1]>; 91193323Seddef : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>; 92193323Seddef : Proc<"pentium4", [FeatureSSE2]>; 93193323Seddef : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>; 94193323Seddef : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>; 95193323Seddef : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>; 96193323Seddef : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; 97193323Seddef : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>; 98193323Seddef : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>; 99193323Seddef : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; 100193323Seddef : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>; 101195098Seddef : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>; 102195098Sed// Sandy Bridge does not have FMA 103195098Seddef : Proc<"sandybridge", [FeatureSSE42, FeatureAVX, Feature64Bit]>; 104193323Sed 105193323Seddef : Proc<"k6", [FeatureMMX]>; 106193323Seddef : Proc<"k6-2", [FeatureMMX, Feature3DNow]>; 107193323Seddef : Proc<"k6-3", [FeatureMMX, Feature3DNow]>; 108193323Seddef : Proc<"athlon", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>; 109193323Seddef : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>; 110193323Seddef : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 111193323Seddef : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 112193323Seddef : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>; 113193323Seddef : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit, 114193323Sed FeatureSlowBTMem]>; 115193323Seddef : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit, 116193323Sed FeatureSlowBTMem]>; 117193323Seddef : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit, 118193323Sed FeatureSlowBTMem]>; 119193323Seddef : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit, 120193323Sed FeatureSlowBTMem]>; 121193323Seddef : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, 122193323Sed FeatureSlowBTMem]>; 123193323Seddef : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, 124193323Sed FeatureSlowBTMem]>; 125193323Seddef : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit, 126193323Sed FeatureSlowBTMem]>; 127193323Seddef : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A, 128193323Sed Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; 129193323Seddef : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A, 130193323Sed Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>; 131195340Seddef : Proc<"istanbul", [Feature3DNowA, Feature64Bit, FeatureSSE4A, 132195340Sed Feature3DNowA]>; 133195340Seddef : Proc<"shanghai", [Feature3DNowA, Feature64Bit, FeatureSSE4A, 134195340Sed Feature3DNowA]>; 135193323Sed 136193323Seddef : Proc<"winchip-c6", [FeatureMMX]>; 137193323Seddef : Proc<"winchip2", [FeatureMMX, Feature3DNow]>; 138193323Seddef : Proc<"c3", [FeatureMMX, Feature3DNow]>; 139193323Seddef : Proc<"c3-2", [FeatureSSE1]>; 140193323Sed 141193323Sed//===----------------------------------------------------------------------===// 142193323Sed// Register File Description 143193323Sed//===----------------------------------------------------------------------===// 144193323Sed 145193323Sedinclude "X86RegisterInfo.td" 146193323Sed 147193323Sed//===----------------------------------------------------------------------===// 148193323Sed// Instruction Descriptions 149193323Sed//===----------------------------------------------------------------------===// 150193323Sed 151193323Sedinclude "X86InstrInfo.td" 152193323Sed 153193323Seddef X86InstrInfo : InstrInfo { 154193323Sed 155193323Sed // Define how we want to layout our TargetSpecific information field... This 156193323Sed // should be kept up-to-date with the fields in the X86InstrInfo.h file. 157193323Sed let TSFlagsFields = ["FormBits", 158193323Sed "hasOpSizePrefix", 159193323Sed "hasAdSizePrefix", 160193323Sed "Prefix", 161193323Sed "hasREX_WPrefix", 162193323Sed "ImmTypeBits", 163193323Sed "FPFormBits", 164193323Sed "hasLockPrefix", 165193323Sed "SegOvrBits", 166193323Sed "Opcode"]; 167193323Sed let TSFlagsShifts = [0, 168193323Sed 6, 169193323Sed 7, 170193323Sed 8, 171193323Sed 12, 172193323Sed 13, 173193323Sed 16, 174193323Sed 19, 175193323Sed 20, 176193323Sed 24]; 177193323Sed} 178193323Sed 179193323Sed//===----------------------------------------------------------------------===// 180193323Sed// Calling Conventions 181193323Sed//===----------------------------------------------------------------------===// 182193323Sed 183193323Sedinclude "X86CallingConv.td" 184193323Sed 185193323Sed 186193323Sed//===----------------------------------------------------------------------===// 187193323Sed// Assembly Printers 188193323Sed//===----------------------------------------------------------------------===// 189193323Sed 190198090Srdivacky// Currently the X86 assembly parser only supports ATT syntax. 191198090Srdivackydef ATTAsmParser : AsmParser { 192198090Srdivacky string AsmParserClassName = "ATTAsmParser"; 193198090Srdivacky int Variant = 0; 194198090Srdivacky 195198090Srdivacky // Discard comments in assembly strings. 196198090Srdivacky string CommentDelimiter = "#"; 197198090Srdivacky 198198090Srdivacky // Recognize hard coded registers. 199198090Srdivacky string RegisterPrefix = "%"; 200198090Srdivacky} 201198090Srdivacky 202193323Sed// The X86 target supports two different syntaxes for emitting machine code. 203193323Sed// This is controlled by the -x86-asm-syntax={att|intel} 204193323Seddef ATTAsmWriter : AsmWriter { 205198090Srdivacky string AsmWriterClassName = "ATTInstPrinter"; 206193323Sed int Variant = 0; 207193323Sed} 208193323Seddef IntelAsmWriter : AsmWriter { 209198090Srdivacky string AsmWriterClassName = "IntelInstPrinter"; 210193323Sed int Variant = 1; 211193323Sed} 212193323Sed 213193323Seddef X86 : Target { 214193323Sed // Information about the instructions... 215193323Sed let InstructionSet = X86InstrInfo; 216193323Sed 217198090Srdivacky let AssemblyParsers = [ATTAsmParser]; 218198090Srdivacky 219193323Sed let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; 220193323Sed} 221