X86IntelInstPrinter.cpp revision 221345 
1//===-- X86IntelInstPrinter.cpp - AT&T assembly instruction printing ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file includes code for rendering MCInst instances as AT&T-style
11// assembly.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "asm-printer"
16#include "X86IntelInstPrinter.h"
17#include "X86InstComments.h"
18#include "X86Subtarget.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCAsmInfo.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Support/FormattedStream.h"
24#include "X86GenInstrNames.inc"
25#include <cctype>
26using namespace llvm;
27
28// Include the auto-generated portion of the assembly writer.
29#define GET_INSTRUCTION_NAME
30#include "X86GenAsmWriter1.inc"
31
32void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
33  printInstruction(MI, OS);
34
35  // If verbose assembly is enabled, we can print some informative comments.
36  if (CommentStream)
37    EmitAnyX86InstComments(MI, *CommentStream, getRegisterName);
38}
39StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const {
40  return getInstructionName(Opcode);
41}
42
43void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op,
44                                     raw_ostream &O) {
45  switch (MI->getOperand(Op).getImm()) {
46  default: assert(0 && "Invalid ssecc argument!");
47  case 0: O << "eq"; break;
48  case 1: O << "lt"; break;
49  case 2: O << "le"; break;
50  case 3: O << "unord"; break;
51  case 4: O << "neq"; break;
52  case 5: O << "nlt"; break;
53  case 6: O << "nle"; break;
54  case 7: O << "ord"; break;
55  }
56}
57
58/// print_pcrel_imm - This is used to print an immediate value that ends up
59/// being encoded as a pc-relative value.
60void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo,
61                                          raw_ostream &O) {
62  const MCOperand &Op = MI->getOperand(OpNo);
63  if (Op.isImm())
64    O << Op.getImm();
65  else {
66    assert(Op.isExpr() && "unknown pcrel immediate operand");
67    O << *Op.getExpr();
68  }
69}
70
71static void PrintRegName(raw_ostream &O, StringRef RegName) {
72  for (unsigned i = 0, e = RegName.size(); i != e; ++i)
73    O << (char)toupper(RegName[i]);
74}
75
76void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
77                                       raw_ostream &O) {
78  const MCOperand &Op = MI->getOperand(OpNo);
79  if (Op.isReg()) {
80    PrintRegName(O, getRegisterName(Op.getReg()));
81  } else if (Op.isImm()) {
82    O << Op.getImm();
83  } else {
84    assert(Op.isExpr() && "unknown operand kind in printOperand");
85    O << *Op.getExpr();
86  }
87}
88
89void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
90                                            raw_ostream &O) {
91  const MCOperand &BaseReg  = MI->getOperand(Op);
92  unsigned ScaleVal         = MI->getOperand(Op+1).getImm();
93  const MCOperand &IndexReg = MI->getOperand(Op+2);
94  const MCOperand &DispSpec = MI->getOperand(Op+3);
95  const MCOperand &SegReg   = MI->getOperand(Op+4);
96
97  // If this has a segment register, print it.
98  if (SegReg.getReg()) {
99    printOperand(MI, Op+4, O);
100    O << ':';
101  }
102
103  O << '[';
104
105  bool NeedPlus = false;
106  if (BaseReg.getReg()) {
107    printOperand(MI, Op, O);
108    NeedPlus = true;
109  }
110
111  if (IndexReg.getReg()) {
112    if (NeedPlus) O << " + ";
113    if (ScaleVal != 1)
114      O << ScaleVal << '*';
115    printOperand(MI, Op+2, O);
116    NeedPlus = true;
117  }
118
119
120  if (!DispSpec.isImm()) {
121    if (NeedPlus) O << " + ";
122    assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
123    O << *DispSpec.getExpr();
124  } else {
125    int64_t DispVal = DispSpec.getImm();
126    if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
127      if (NeedPlus) {
128        if (DispVal > 0)
129          O << " + ";
130        else {
131          O << " - ";
132          DispVal = -DispVal;
133        }
134      }
135      O << DispVal;
136    }
137  }
138
139  O << ']';
140}
141