X86ATTInstPrinter.cpp revision 218885
1//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file includes code for rendering MCInst instances as AT&T-style 11// assembly. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "asm-printer" 16#include "X86ATTInstPrinter.h" 17#include "X86InstComments.h" 18#include "llvm/MC/MCInst.h" 19#include "llvm/MC/MCAsmInfo.h" 20#include "llvm/MC/MCExpr.h" 21#include "llvm/Support/ErrorHandling.h" 22#include "llvm/Support/Format.h" 23#include "llvm/Support/FormattedStream.h" 24#include "X86GenInstrNames.inc" 25using namespace llvm; 26 27// Include the auto-generated portion of the assembly writer. 28#define GET_INSTRUCTION_NAME 29#include "X86GenAsmWriter.inc" 30 31void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { 32 printInstruction(MI, OS); 33 34 // If verbose assembly is enabled, we can print some informative comments. 35 if (CommentStream) 36 EmitAnyX86InstComments(MI, *CommentStream, getRegisterName); 37} 38StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const { 39 return getInstructionName(Opcode); 40} 41 42 43void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op, 44 raw_ostream &O) { 45 switch (MI->getOperand(Op).getImm()) { 46 default: assert(0 && "Invalid ssecc argument!"); 47 case 0: O << "eq"; break; 48 case 1: O << "lt"; break; 49 case 2: O << "le"; break; 50 case 3: O << "unord"; break; 51 case 4: O << "neq"; break; 52 case 5: O << "nlt"; break; 53 case 6: O << "nle"; break; 54 case 7: O << "ord"; break; 55 } 56} 57 58/// print_pcrel_imm - This is used to print an immediate value that ends up 59/// being encoded as a pc-relative value (e.g. for jumps and calls). These 60/// print slightly differently than normal immediates. For example, a $ is not 61/// emitted. 62void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo, 63 raw_ostream &O) { 64 const MCOperand &Op = MI->getOperand(OpNo); 65 if (Op.isImm()) 66 // Print this as a signed 32-bit value. 67 O << (int)Op.getImm(); 68 else { 69 assert(Op.isExpr() && "unknown pcrel immediate operand"); 70 O << *Op.getExpr(); 71 } 72} 73 74void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 75 raw_ostream &O) { 76 const MCOperand &Op = MI->getOperand(OpNo); 77 if (Op.isReg()) { 78 O << '%' << getRegisterName(Op.getReg()); 79 } else if (Op.isImm()) { 80 O << '$' << Op.getImm(); 81 82 if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256)) 83 *CommentStream << format("imm = 0x%llX\n", (long long)Op.getImm()); 84 85 } else { 86 assert(Op.isExpr() && "unknown operand kind in printOperand"); 87 O << '$' << *Op.getExpr(); 88 } 89} 90 91void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op, 92 raw_ostream &O) { 93 const MCOperand &BaseReg = MI->getOperand(Op); 94 const MCOperand &IndexReg = MI->getOperand(Op+2); 95 const MCOperand &DispSpec = MI->getOperand(Op+3); 96 const MCOperand &SegReg = MI->getOperand(Op+4); 97 98 // If this has a segment register, print it. 99 if (SegReg.getReg()) { 100 printOperand(MI, Op+4, O); 101 O << ':'; 102 } 103 104 if (DispSpec.isImm()) { 105 int64_t DispVal = DispSpec.getImm(); 106 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) 107 O << DispVal; 108 } else { 109 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?"); 110 O << *DispSpec.getExpr(); 111 } 112 113 if (IndexReg.getReg() || BaseReg.getReg()) { 114 O << '('; 115 if (BaseReg.getReg()) 116 printOperand(MI, Op, O); 117 118 if (IndexReg.getReg()) { 119 O << ','; 120 printOperand(MI, Op+2, O); 121 unsigned ScaleVal = MI->getOperand(Op+1).getImm(); 122 if (ScaleVal != 1) 123 O << ',' << ScaleVal; 124 } 125 O << ')'; 126 } 127} 128