X86ATTInstPrinter.cpp revision 221345
1218885Sdim//===-- X86ATTInstPrinter.cpp - AT&T assembly instruction printing --------===// 2218885Sdim// 3218885Sdim// The LLVM Compiler Infrastructure 4218885Sdim// 5218885Sdim// This file is distributed under the University of Illinois Open Source 6218885Sdim// License. See LICENSE.TXT for details. 7218885Sdim// 8218885Sdim//===----------------------------------------------------------------------===// 9218885Sdim// 10218885Sdim// This file includes code for rendering MCInst instances as AT&T-style 11218885Sdim// assembly. 12218885Sdim// 13218885Sdim//===----------------------------------------------------------------------===// 14218885Sdim 15218885Sdim#define DEBUG_TYPE "asm-printer" 16218885Sdim#include "X86ATTInstPrinter.h" 17218885Sdim#include "X86InstComments.h" 18221345Sdim#include "X86Subtarget.h" 19218885Sdim#include "llvm/MC/MCInst.h" 20218885Sdim#include "llvm/MC/MCAsmInfo.h" 21218885Sdim#include "llvm/MC/MCExpr.h" 22218885Sdim#include "llvm/Support/ErrorHandling.h" 23218885Sdim#include "llvm/Support/Format.h" 24218885Sdim#include "llvm/Support/FormattedStream.h" 25218885Sdim#include "X86GenInstrNames.inc" 26221345Sdim#include <map> 27218885Sdimusing namespace llvm; 28218885Sdim 29218885Sdim// Include the auto-generated portion of the assembly writer. 30218885Sdim#define GET_INSTRUCTION_NAME 31221345Sdim#define PRINT_ALIAS_INSTR 32221345Sdim#include "X86GenRegisterNames.inc" 33218885Sdim#include "X86GenAsmWriter.inc" 34221345Sdim#undef PRINT_ALIAS_INSTR 35221345Sdim#undef GET_INSTRUCTION_NAME 36218885Sdim 37221345SdimX86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) 38221345Sdim : MCInstPrinter(MAI) { 39221345Sdim // Initialize the set of available features. 40221345Sdim setAvailableFeatures(ComputeAvailableFeatures( 41221345Sdim &TM.getSubtarget<X86Subtarget>())); 42221345Sdim} 43221345Sdim 44218885Sdimvoid X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { 45221345Sdim // Try to print any aliases first. 46221345Sdim if (!printAliasInstr(MI, OS)) 47221345Sdim printInstruction(MI, OS); 48218885Sdim 49218885Sdim // If verbose assembly is enabled, we can print some informative comments. 50218885Sdim if (CommentStream) 51218885Sdim EmitAnyX86InstComments(MI, *CommentStream, getRegisterName); 52218885Sdim} 53221345Sdim 54218885SdimStringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const { 55218885Sdim return getInstructionName(Opcode); 56218885Sdim} 57218885Sdim 58218885Sdimvoid X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op, 59218885Sdim raw_ostream &O) { 60218885Sdim switch (MI->getOperand(Op).getImm()) { 61218885Sdim default: assert(0 && "Invalid ssecc argument!"); 62218885Sdim case 0: O << "eq"; break; 63218885Sdim case 1: O << "lt"; break; 64218885Sdim case 2: O << "le"; break; 65218885Sdim case 3: O << "unord"; break; 66218885Sdim case 4: O << "neq"; break; 67218885Sdim case 5: O << "nlt"; break; 68218885Sdim case 6: O << "nle"; break; 69218885Sdim case 7: O << "ord"; break; 70218885Sdim } 71218885Sdim} 72218885Sdim 73218885Sdim/// print_pcrel_imm - This is used to print an immediate value that ends up 74218885Sdim/// being encoded as a pc-relative value (e.g. for jumps and calls). These 75218885Sdim/// print slightly differently than normal immediates. For example, a $ is not 76218885Sdim/// emitted. 77218885Sdimvoid X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo, 78218885Sdim raw_ostream &O) { 79218885Sdim const MCOperand &Op = MI->getOperand(OpNo); 80218885Sdim if (Op.isImm()) 81218885Sdim // Print this as a signed 32-bit value. 82218885Sdim O << (int)Op.getImm(); 83218885Sdim else { 84218885Sdim assert(Op.isExpr() && "unknown pcrel immediate operand"); 85218885Sdim O << *Op.getExpr(); 86218885Sdim } 87218885Sdim} 88218885Sdim 89218885Sdimvoid X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 90218885Sdim raw_ostream &O) { 91218885Sdim const MCOperand &Op = MI->getOperand(OpNo); 92218885Sdim if (Op.isReg()) { 93218885Sdim O << '%' << getRegisterName(Op.getReg()); 94218885Sdim } else if (Op.isImm()) { 95218885Sdim O << '$' << Op.getImm(); 96218885Sdim 97218885Sdim if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256)) 98218885Sdim *CommentStream << format("imm = 0x%llX\n", (long long)Op.getImm()); 99218885Sdim 100218885Sdim } else { 101218885Sdim assert(Op.isExpr() && "unknown operand kind in printOperand"); 102218885Sdim O << '$' << *Op.getExpr(); 103218885Sdim } 104218885Sdim} 105218885Sdim 106218885Sdimvoid X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op, 107218885Sdim raw_ostream &O) { 108218885Sdim const MCOperand &BaseReg = MI->getOperand(Op); 109218885Sdim const MCOperand &IndexReg = MI->getOperand(Op+2); 110218885Sdim const MCOperand &DispSpec = MI->getOperand(Op+3); 111218885Sdim const MCOperand &SegReg = MI->getOperand(Op+4); 112218885Sdim 113218885Sdim // If this has a segment register, print it. 114218885Sdim if (SegReg.getReg()) { 115218885Sdim printOperand(MI, Op+4, O); 116218885Sdim O << ':'; 117218885Sdim } 118218885Sdim 119218885Sdim if (DispSpec.isImm()) { 120218885Sdim int64_t DispVal = DispSpec.getImm(); 121218885Sdim if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) 122218885Sdim O << DispVal; 123218885Sdim } else { 124218885Sdim assert(DispSpec.isExpr() && "non-immediate displacement for LEA?"); 125218885Sdim O << *DispSpec.getExpr(); 126218885Sdim } 127218885Sdim 128218885Sdim if (IndexReg.getReg() || BaseReg.getReg()) { 129218885Sdim O << '('; 130218885Sdim if (BaseReg.getReg()) 131218885Sdim printOperand(MI, Op, O); 132218885Sdim 133218885Sdim if (IndexReg.getReg()) { 134218885Sdim O << ','; 135218885Sdim printOperand(MI, Op+2, O); 136218885Sdim unsigned ScaleVal = MI->getOperand(Op+1).getImm(); 137218885Sdim if (ScaleVal != 1) 138218885Sdim O << ',' << ScaleVal; 139218885Sdim } 140218885Sdim O << ')'; 141218885Sdim } 142218885Sdim} 143