SparcInstrInfo.cpp revision 224145
1122394Sharti//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===// 2122394Sharti// 3122394Sharti// The LLVM Compiler Infrastructure 4122394Sharti// 5122394Sharti// This file is distributed under the University of Illinois Open Source 6122394Sharti// License. See LICENSE.TXT for details. 7133211Sharti// 8133211Sharti//===----------------------------------------------------------------------===// 9133211Sharti// 10133211Sharti// This file contains the Sparc implementation of the TargetInstrInfo class. 11133211Sharti// 12133211Sharti//===----------------------------------------------------------------------===// 13122394Sharti 14122394Sharti#include "SparcInstrInfo.h" 15122394Sharti#include "Sparc.h" 16133211Sharti#include "SparcMachineFunctionInfo.h" 17133211Sharti#include "SparcSubtarget.h" 18133211Sharti#include "llvm/CodeGen/MachineInstrBuilder.h" 19133211Sharti#include "llvm/CodeGen/MachineRegisterInfo.h" 20133211Sharti#include "llvm/Target/TargetRegistry.h" 21133211Sharti#include "llvm/Support/ErrorHandling.h" 22133211Sharti#include "llvm/ADT/STLExtras.h" 23133211Sharti#include "llvm/ADT/SmallVector.h" 24133211Sharti 25133211Sharti#define GET_INSTRINFO_CTOR 26133211Sharti#include "SparcGenInstrInfo.inc" 27133211Sharti 28122394Shartiusing namespace llvm; 29156066Sharti 30122394ShartiSparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) 31122394Sharti : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), 32122394Sharti RI(ST, *this), Subtarget(ST) { 33122394Sharti} 34122394Sharti 35122394Sharti/// isLoadFromStackSlot - If the specified machine instruction is a direct 36122394Sharti/// load from a stack slot, return the virtual or physical register number of 37122394Sharti/// the destination along with the FrameIndex of the loaded stack slot. If 38122394Sharti/// not, return 0. This predicate must return 0 if the instruction has 39241654Semax/// any side effects other than loading from the stack slot. 40122394Shartiunsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 41122394Sharti int &FrameIndex) const { 42122394Sharti if (MI->getOpcode() == SP::LDri || 43122394Sharti MI->getOpcode() == SP::LDFri || 44122394Sharti MI->getOpcode() == SP::LDDFri) { 45122394Sharti if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && 46122394Sharti MI->getOperand(2).getImm() == 0) { 47122394Sharti FrameIndex = MI->getOperand(1).getIndex(); 48122394Sharti return MI->getOperand(0).getReg(); 49122394Sharti } 50122394Sharti } 51122394Sharti return 0; 52122394Sharti} 53122394Sharti 54122394Sharti/// isStoreToStackSlot - If the specified machine instruction is a direct 55122394Sharti/// store to a stack slot, return the virtual or physical register number of 56122394Sharti/// the source reg along with the FrameIndex of the loaded stack slot. If 57122394Sharti/// not, return 0. This predicate must return 0 if the instruction has 58122394Sharti/// any side effects other than storing to the stack slot. 59122394Shartiunsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 60122394Sharti int &FrameIndex) const { 61122394Sharti if (MI->getOpcode() == SP::STri || 62122394Sharti MI->getOpcode() == SP::STFri || 63122394Sharti MI->getOpcode() == SP::STDFri) { 64122394Sharti if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && 65122394Sharti MI->getOperand(1).getImm() == 0) { 66122394Sharti FrameIndex = MI->getOperand(0).getIndex(); 67122394Sharti return MI->getOperand(2).getReg(); 68122394Sharti } 69122394Sharti } 70122394Sharti return 0; 71155602Sharti} 72155602Sharti 73155602Shartistatic bool IsIntegerCC(unsigned CC) 74155602Sharti{ 75155602Sharti return (CC <= SPCC::ICC_VC); 76155602Sharti} 77155602Sharti 78155602Sharti 79155602Shartistatic SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) 80155602Sharti{ 81155602Sharti switch(CC) { 82155602Sharti default: llvm_unreachable("Unknown condition code"); 83155602Sharti case SPCC::ICC_NE: return SPCC::ICC_E; 84122394Sharti case SPCC::ICC_E: return SPCC::ICC_NE; 85122394Sharti case SPCC::ICC_G: return SPCC::ICC_LE; 86122394Sharti case SPCC::ICC_LE: return SPCC::ICC_G; 87122394Sharti case SPCC::ICC_GE: return SPCC::ICC_L; 88122394Sharti case SPCC::ICC_L: return SPCC::ICC_GE; 89122394Sharti case SPCC::ICC_GU: return SPCC::ICC_LEU; 90122394Sharti case SPCC::ICC_LEU: return SPCC::ICC_GU; 91122394Sharti case SPCC::ICC_CC: return SPCC::ICC_CS; 92122394Sharti case SPCC::ICC_CS: return SPCC::ICC_CC; 93122394Sharti case SPCC::ICC_POS: return SPCC::ICC_NEG; 94122394Sharti case SPCC::ICC_NEG: return SPCC::ICC_POS; 95122394Sharti case SPCC::ICC_VC: return SPCC::ICC_VS; 96122394Sharti case SPCC::ICC_VS: return SPCC::ICC_VC; 97122394Sharti 98122394Sharti case SPCC::FCC_U: return SPCC::FCC_O; 99122394Sharti case SPCC::FCC_O: return SPCC::FCC_U; 100122394Sharti case SPCC::FCC_G: return SPCC::FCC_LE; 101122394Sharti case SPCC::FCC_LE: return SPCC::FCC_G; 102122394Sharti case SPCC::FCC_UG: return SPCC::FCC_ULE; 103122394Sharti case SPCC::FCC_ULE: return SPCC::FCC_UG; 104122394Sharti case SPCC::FCC_L: return SPCC::FCC_GE; 105122394Sharti case SPCC::FCC_GE: return SPCC::FCC_L; 106122394Sharti case SPCC::FCC_UL: return SPCC::FCC_UGE; 107122394Sharti case SPCC::FCC_UGE: return SPCC::FCC_UL; 108122394Sharti case SPCC::FCC_LG: return SPCC::FCC_UE; 109122394Sharti case SPCC::FCC_UE: return SPCC::FCC_LG; 110122394Sharti case SPCC::FCC_NE: return SPCC::FCC_E; 111122394Sharti case SPCC::FCC_E: return SPCC::FCC_NE; 112122394Sharti } 113122394Sharti} 114122394Sharti 115122394Sharti 116122394Shartibool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 117122394Sharti MachineBasicBlock *&TBB, 118122394Sharti MachineBasicBlock *&FBB, 119122394Sharti SmallVectorImpl<MachineOperand> &Cond, 120122394Sharti bool AllowModify) const 121122394Sharti{ 122122394Sharti 123122394Sharti MachineBasicBlock::iterator I = MBB.end(); 124122394Sharti MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 125122394Sharti while (I != MBB.begin()) { 126122394Sharti --I; 127122394Sharti 128122394Sharti if (I->isDebugValue()) 129122394Sharti continue; 130122394Sharti 131122394Sharti //When we see a non-terminator, we are done 132122394Sharti if (!isUnpredicatedTerminator(I)) 133122394Sharti break; 134122394Sharti 135122394Sharti //Terminator is not a branch 136122394Sharti if (!I->getDesc().isBranch()) 137122394Sharti return true; 138122394Sharti 139122394Sharti //Handle Unconditional branches 140122394Sharti if (I->getOpcode() == SP::BA) { 141122394Sharti UnCondBrIter = I; 142122394Sharti 143122394Sharti if (!AllowModify) { 144122394Sharti TBB = I->getOperand(0).getMBB(); 145122394Sharti continue; 146122394Sharti } 147122394Sharti 148122394Sharti while (llvm::next(I) != MBB.end()) 149122394Sharti llvm::next(I)->eraseFromParent(); 150122394Sharti 151122394Sharti Cond.clear(); 152122394Sharti FBB = 0; 153122394Sharti 154122394Sharti if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 155122394Sharti TBB = 0; 156122394Sharti I->eraseFromParent(); 157122394Sharti I = MBB.end(); 158122394Sharti UnCondBrIter = MBB.end(); 159122394Sharti continue; 160122394Sharti } 161122394Sharti 162122394Sharti TBB = I->getOperand(0).getMBB(); 163122394Sharti continue; 164122394Sharti } 165122394Sharti 166122394Sharti unsigned Opcode = I->getOpcode(); 167122394Sharti if (Opcode != SP::BCOND && Opcode != SP::FBCOND) 168122394Sharti return true; //Unknown Opcode 169122394Sharti 170122394Sharti SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm(); 171122394Sharti 172122394Sharti if (Cond.empty()) { 173122394Sharti MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 174122394Sharti if (AllowModify && UnCondBrIter != MBB.end() && 175122394Sharti MBB.isLayoutSuccessor(TargetBB)) { 176122394Sharti 177122394Sharti //Transform the code 178122394Sharti // 179122394Sharti // brCC L1 180122394Sharti // ba L2 181122394Sharti // L1: 182122394Sharti // .. 183122394Sharti // L2: 184122394Sharti // 185122394Sharti // into 186122394Sharti // 187122394Sharti // brnCC L2 188122394Sharti // L1: 189146525Sharti // ... 190122394Sharti // L2: 191122394Sharti // 192146525Sharti BranchCode = GetOppositeBranchCondition(BranchCode); 193122394Sharti MachineBasicBlock::iterator OldInst = I; 194122394Sharti BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode)) 195122394Sharti .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode); 196122394Sharti BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA)) 197122394Sharti .addMBB(TargetBB); 198146525Sharti MBB.addSuccessor(TargetBB); 199122394Sharti OldInst->eraseFromParent(); 200122394Sharti UnCondBrIter->eraseFromParent(); 201122394Sharti 202122394Sharti UnCondBrIter = MBB.end(); 203155602Sharti I = MBB.end(); 204155602Sharti continue; 205155602Sharti } 206155602Sharti FBB = TBB; 207155602Sharti TBB = I->getOperand(0).getMBB(); 208155602Sharti Cond.push_back(MachineOperand::CreateImm(BranchCode)); 209155602Sharti continue; 210155602Sharti } 211155602Sharti //FIXME: Handle subsequent conditional branches 212155602Sharti //For now, we can't handle multiple conditional branches 213155602Sharti return true; 214155602Sharti } 215200063Ssyrinx return false; 216200063Ssyrinx} 217200063Ssyrinx 218200063Ssyrinxunsigned 219200063SsyrinxSparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 220200063Ssyrinx MachineBasicBlock *FBB, 221200063Ssyrinx const SmallVectorImpl<MachineOperand> &Cond, 222200063Ssyrinx DebugLoc DL) const { 223122394Sharti assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 224122394Sharti assert((Cond.size() == 1 || Cond.size() == 0) && 225122394Sharti "Sparc branch conditions should have one component!"); 226122394Sharti 227122394Sharti if (Cond.empty()) { 228122394Sharti assert(!FBB && "Unconditional branch with multiple successors!"); 229122394Sharti BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); 230122394Sharti return 1; 231122394Sharti } 232122394Sharti 233122394Sharti //Conditional branch 234122394Sharti unsigned CC = Cond[0].getImm(); 235122394Sharti 236122394Sharti if (IsIntegerCC(CC)) 237122394Sharti BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); 238122394Sharti else 239122394Sharti BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); 240122394Sharti if (!FBB) 241122394Sharti return 1; 242122394Sharti 243122394Sharti BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); 244122394Sharti return 2; 245122394Sharti} 246122394Sharti 247122394Shartiunsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const 248122394Sharti{ 249122394Sharti MachineBasicBlock::iterator I = MBB.end(); 250122394Sharti unsigned Count = 0; 251122394Sharti while (I != MBB.begin()) { 252122394Sharti --I; 253122394Sharti 254122394Sharti if (I->isDebugValue()) 255122394Sharti continue; 256122394Sharti 257122394Sharti if (I->getOpcode() != SP::BA 258122394Sharti && I->getOpcode() != SP::BCOND 259122394Sharti && I->getOpcode() != SP::FBCOND) 260150920Sharti break; // Not a branch 261150920Sharti 262150920Sharti I->eraseFromParent(); 263150920Sharti I = MBB.end(); 264150920Sharti ++Count; 265150920Sharti } 266150920Sharti return Count; 267150920Sharti} 268122394Sharti 269122394Shartivoid SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 270150920Sharti MachineBasicBlock::iterator I, DebugLoc DL, 271150920Sharti unsigned DestReg, unsigned SrcReg, 272150920Sharti bool KillSrc) const { 273 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) 274 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) 275 .addReg(SrcReg, getKillRegState(KillSrc)); 276 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) 277 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) 278 .addReg(SrcReg, getKillRegState(KillSrc)); 279 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) 280 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg) 281 .addReg(SrcReg, getKillRegState(KillSrc)); 282 else 283 llvm_unreachable("Impossible reg-to-reg copy"); 284} 285 286void SparcInstrInfo:: 287storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 288 unsigned SrcReg, bool isKill, int FI, 289 const TargetRegisterClass *RC, 290 const TargetRegisterInfo *TRI) const { 291 DebugLoc DL; 292 if (I != MBB.end()) DL = I->getDebugLoc(); 293 294 // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 295 if (RC == SP::IntRegsRegisterClass) 296 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) 297 .addReg(SrcReg, getKillRegState(isKill)); 298 else if (RC == SP::FPRegsRegisterClass) 299 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) 300 .addReg(SrcReg, getKillRegState(isKill)); 301 else if (RC == SP::DFPRegsRegisterClass) 302 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) 303 .addReg(SrcReg, getKillRegState(isKill)); 304 else 305 llvm_unreachable("Can't store this register to stack slot"); 306} 307 308void SparcInstrInfo:: 309loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 310 unsigned DestReg, int FI, 311 const TargetRegisterClass *RC, 312 const TargetRegisterInfo *TRI) const { 313 DebugLoc DL; 314 if (I != MBB.end()) DL = I->getDebugLoc(); 315 316 if (RC == SP::IntRegsRegisterClass) 317 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); 318 else if (RC == SP::FPRegsRegisterClass) 319 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); 320 else if (RC == SP::DFPRegsRegisterClass) 321 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); 322 else 323 llvm_unreachable("Can't load this register from stack slot"); 324} 325 326unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const 327{ 328 SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>(); 329 unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg(); 330 if (GlobalBaseReg != 0) 331 return GlobalBaseReg; 332 333 // Insert the set of GlobalBaseReg into the first MBB of the function 334 MachineBasicBlock &FirstMBB = MF->front(); 335 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 336 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 337 338 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 339 340 341 DebugLoc dl; 342 343 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg); 344 SparcFI->setGlobalBaseReg(GlobalBaseReg); 345 return GlobalBaseReg; 346} 347