1234353Sdim//===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the Sparc implementation of the TargetInstrInfo class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#include "SparcInstrInfo.h" 15224145Sdim#include "Sparc.h" 16224145Sdim#include "SparcMachineFunctionInfo.h" 17193323Sed#include "SparcSubtarget.h" 18249423Sdim#include "llvm/ADT/STLExtras.h" 19249423Sdim#include "llvm/ADT/SmallVector.h" 20263508Sdim#include "llvm/CodeGen/MachineFrameInfo.h" 21193323Sed#include "llvm/CodeGen/MachineInstrBuilder.h" 22263508Sdim#include "llvm/CodeGen/MachineMemOperand.h" 23198090Srdivacky#include "llvm/CodeGen/MachineRegisterInfo.h" 24198090Srdivacky#include "llvm/Support/ErrorHandling.h" 25226633Sdim#include "llvm/Support/TargetRegistry.h" 26224145Sdim 27263508Sdim#define GET_INSTRINFO_CTOR_DTOR 28193323Sed#include "SparcGenInstrInfo.inc" 29224145Sdim 30193323Sedusing namespace llvm; 31193323Sed 32263508Sdim 33263508Sdim// Pin the vtable to this file. 34263508Sdimvoid SparcInstrInfo::anchor() {} 35263508Sdim 36193323SedSparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) 37224145Sdim : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), 38263508Sdim RI(ST), Subtarget(ST) { 39193323Sed} 40193323Sed 41193323Sed/// isLoadFromStackSlot - If the specified machine instruction is a direct 42193323Sed/// load from a stack slot, return the virtual or physical register number of 43193323Sed/// the destination along with the FrameIndex of the loaded stack slot. If 44193323Sed/// not, return 0. This predicate must return 0 if the instruction has 45193323Sed/// any side effects other than loading from the stack slot. 46193323Sedunsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 47193323Sed int &FrameIndex) const { 48193323Sed if (MI->getOpcode() == SP::LDri || 49263508Sdim MI->getOpcode() == SP::LDXri || 50193323Sed MI->getOpcode() == SP::LDFri || 51263508Sdim MI->getOpcode() == SP::LDDFri || 52263508Sdim MI->getOpcode() == SP::LDQFri) { 53193323Sed if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && 54193323Sed MI->getOperand(2).getImm() == 0) { 55193323Sed FrameIndex = MI->getOperand(1).getIndex(); 56193323Sed return MI->getOperand(0).getReg(); 57193323Sed } 58193323Sed } 59193323Sed return 0; 60193323Sed} 61193323Sed 62193323Sed/// isStoreToStackSlot - If the specified machine instruction is a direct 63193323Sed/// store to a stack slot, return the virtual or physical register number of 64193323Sed/// the source reg along with the FrameIndex of the loaded stack slot. If 65193323Sed/// not, return 0. This predicate must return 0 if the instruction has 66193323Sed/// any side effects other than storing to the stack slot. 67193323Sedunsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 68193323Sed int &FrameIndex) const { 69193323Sed if (MI->getOpcode() == SP::STri || 70263508Sdim MI->getOpcode() == SP::STXri || 71193323Sed MI->getOpcode() == SP::STFri || 72263508Sdim MI->getOpcode() == SP::STDFri || 73263508Sdim MI->getOpcode() == SP::STQFri) { 74193323Sed if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && 75193323Sed MI->getOperand(1).getImm() == 0) { 76193323Sed FrameIndex = MI->getOperand(0).getIndex(); 77193323Sed return MI->getOperand(2).getReg(); 78193323Sed } 79193323Sed } 80193323Sed return 0; 81193323Sed} 82193323Sed 83218893Sdimstatic bool IsIntegerCC(unsigned CC) 84218893Sdim{ 85218893Sdim return (CC <= SPCC::ICC_VC); 86218893Sdim} 87218893Sdim 88218893Sdim 89218893Sdimstatic SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) 90218893Sdim{ 91218893Sdim switch(CC) { 92218893Sdim case SPCC::ICC_NE: return SPCC::ICC_E; 93218893Sdim case SPCC::ICC_E: return SPCC::ICC_NE; 94218893Sdim case SPCC::ICC_G: return SPCC::ICC_LE; 95218893Sdim case SPCC::ICC_LE: return SPCC::ICC_G; 96218893Sdim case SPCC::ICC_GE: return SPCC::ICC_L; 97218893Sdim case SPCC::ICC_L: return SPCC::ICC_GE; 98218893Sdim case SPCC::ICC_GU: return SPCC::ICC_LEU; 99218893Sdim case SPCC::ICC_LEU: return SPCC::ICC_GU; 100218893Sdim case SPCC::ICC_CC: return SPCC::ICC_CS; 101218893Sdim case SPCC::ICC_CS: return SPCC::ICC_CC; 102218893Sdim case SPCC::ICC_POS: return SPCC::ICC_NEG; 103218893Sdim case SPCC::ICC_NEG: return SPCC::ICC_POS; 104218893Sdim case SPCC::ICC_VC: return SPCC::ICC_VS; 105218893Sdim case SPCC::ICC_VS: return SPCC::ICC_VC; 106218893Sdim 107218893Sdim case SPCC::FCC_U: return SPCC::FCC_O; 108218893Sdim case SPCC::FCC_O: return SPCC::FCC_U; 109263508Sdim case SPCC::FCC_G: return SPCC::FCC_ULE; 110263508Sdim case SPCC::FCC_LE: return SPCC::FCC_UG; 111263508Sdim case SPCC::FCC_UG: return SPCC::FCC_LE; 112263508Sdim case SPCC::FCC_ULE: return SPCC::FCC_G; 113263508Sdim case SPCC::FCC_L: return SPCC::FCC_UGE; 114263508Sdim case SPCC::FCC_GE: return SPCC::FCC_UL; 115263508Sdim case SPCC::FCC_UL: return SPCC::FCC_GE; 116263508Sdim case SPCC::FCC_UGE: return SPCC::FCC_L; 117218893Sdim case SPCC::FCC_LG: return SPCC::FCC_UE; 118218893Sdim case SPCC::FCC_UE: return SPCC::FCC_LG; 119218893Sdim case SPCC::FCC_NE: return SPCC::FCC_E; 120218893Sdim case SPCC::FCC_E: return SPCC::FCC_NE; 121218893Sdim } 122234353Sdim llvm_unreachable("Invalid cond code"); 123218893Sdim} 124218893Sdim 125218893Sdimbool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 126218893Sdim MachineBasicBlock *&TBB, 127218893Sdim MachineBasicBlock *&FBB, 128218893Sdim SmallVectorImpl<MachineOperand> &Cond, 129218893Sdim bool AllowModify) const 130218893Sdim{ 131218893Sdim 132218893Sdim MachineBasicBlock::iterator I = MBB.end(); 133218893Sdim MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 134218893Sdim while (I != MBB.begin()) { 135218893Sdim --I; 136218893Sdim 137218893Sdim if (I->isDebugValue()) 138218893Sdim continue; 139218893Sdim 140263508Sdim // When we see a non-terminator, we are done. 141218893Sdim if (!isUnpredicatedTerminator(I)) 142218893Sdim break; 143218893Sdim 144263508Sdim // Terminator is not a branch. 145234353Sdim if (!I->isBranch()) 146218893Sdim return true; 147218893Sdim 148263508Sdim // Handle Unconditional branches. 149218893Sdim if (I->getOpcode() == SP::BA) { 150218893Sdim UnCondBrIter = I; 151218893Sdim 152218893Sdim if (!AllowModify) { 153218893Sdim TBB = I->getOperand(0).getMBB(); 154218893Sdim continue; 155218893Sdim } 156218893Sdim 157218893Sdim while (llvm::next(I) != MBB.end()) 158218893Sdim llvm::next(I)->eraseFromParent(); 159218893Sdim 160218893Sdim Cond.clear(); 161218893Sdim FBB = 0; 162218893Sdim 163218893Sdim if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 164218893Sdim TBB = 0; 165218893Sdim I->eraseFromParent(); 166218893Sdim I = MBB.end(); 167218893Sdim UnCondBrIter = MBB.end(); 168218893Sdim continue; 169218893Sdim } 170218893Sdim 171218893Sdim TBB = I->getOperand(0).getMBB(); 172218893Sdim continue; 173218893Sdim } 174218893Sdim 175218893Sdim unsigned Opcode = I->getOpcode(); 176218893Sdim if (Opcode != SP::BCOND && Opcode != SP::FBCOND) 177263508Sdim return true; // Unknown Opcode. 178218893Sdim 179218893Sdim SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm(); 180218893Sdim 181218893Sdim if (Cond.empty()) { 182218893Sdim MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 183218893Sdim if (AllowModify && UnCondBrIter != MBB.end() && 184218893Sdim MBB.isLayoutSuccessor(TargetBB)) { 185218893Sdim 186263508Sdim // Transform the code 187218893Sdim // 188218893Sdim // brCC L1 189218893Sdim // ba L2 190218893Sdim // L1: 191218893Sdim // .. 192218893Sdim // L2: 193218893Sdim // 194218893Sdim // into 195218893Sdim // 196218893Sdim // brnCC L2 197218893Sdim // L1: 198218893Sdim // ... 199218893Sdim // L2: 200218893Sdim // 201218893Sdim BranchCode = GetOppositeBranchCondition(BranchCode); 202218893Sdim MachineBasicBlock::iterator OldInst = I; 203218893Sdim BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode)) 204218893Sdim .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode); 205218893Sdim BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA)) 206218893Sdim .addMBB(TargetBB); 207234353Sdim 208218893Sdim OldInst->eraseFromParent(); 209218893Sdim UnCondBrIter->eraseFromParent(); 210218893Sdim 211218893Sdim UnCondBrIter = MBB.end(); 212218893Sdim I = MBB.end(); 213218893Sdim continue; 214218893Sdim } 215218893Sdim FBB = TBB; 216218893Sdim TBB = I->getOperand(0).getMBB(); 217218893Sdim Cond.push_back(MachineOperand::CreateImm(BranchCode)); 218218893Sdim continue; 219218893Sdim } 220263508Sdim // FIXME: Handle subsequent conditional branches. 221263508Sdim // For now, we can't handle multiple conditional branches. 222218893Sdim return true; 223218893Sdim } 224218893Sdim return false; 225218893Sdim} 226218893Sdim 227193323Sedunsigned 228193323SedSparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 229193323Sed MachineBasicBlock *FBB, 230210299Sed const SmallVectorImpl<MachineOperand> &Cond, 231218893Sdim DebugLoc DL) const { 232218893Sdim assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 233218893Sdim assert((Cond.size() == 1 || Cond.size() == 0) && 234218893Sdim "Sparc branch conditions should have one component!"); 235218893Sdim 236218893Sdim if (Cond.empty()) { 237218893Sdim assert(!FBB && "Unconditional branch with multiple successors!"); 238218893Sdim BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); 239218893Sdim return 1; 240218893Sdim } 241218893Sdim 242263508Sdim // Conditional branch 243218893Sdim unsigned CC = Cond[0].getImm(); 244218893Sdim 245218893Sdim if (IsIntegerCC(CC)) 246218893Sdim BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); 247218893Sdim else 248218893Sdim BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); 249218893Sdim if (!FBB) 250218893Sdim return 1; 251218893Sdim 252218893Sdim BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); 253218893Sdim return 2; 254193323Sed} 255193323Sed 256218893Sdimunsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const 257218893Sdim{ 258218893Sdim MachineBasicBlock::iterator I = MBB.end(); 259218893Sdim unsigned Count = 0; 260218893Sdim while (I != MBB.begin()) { 261218893Sdim --I; 262218893Sdim 263218893Sdim if (I->isDebugValue()) 264218893Sdim continue; 265218893Sdim 266218893Sdim if (I->getOpcode() != SP::BA 267218893Sdim && I->getOpcode() != SP::BCOND 268218893Sdim && I->getOpcode() != SP::FBCOND) 269218893Sdim break; // Not a branch 270218893Sdim 271218893Sdim I->eraseFromParent(); 272218893Sdim I = MBB.end(); 273218893Sdim ++Count; 274218893Sdim } 275218893Sdim return Count; 276218893Sdim} 277218893Sdim 278210299Sedvoid SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 279210299Sed MachineBasicBlock::iterator I, DebugLoc DL, 280210299Sed unsigned DestReg, unsigned SrcReg, 281210299Sed bool KillSrc) const { 282263508Sdim unsigned numSubRegs = 0; 283263508Sdim unsigned movOpc = 0; 284263508Sdim const unsigned *subRegIdx = 0; 285263508Sdim 286263508Sdim const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd }; 287263508Sdim const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 }; 288263508Sdim const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd, 289263508Sdim SP::sub_odd64_then_sub_even, 290263508Sdim SP::sub_odd64_then_sub_odd }; 291263508Sdim 292210299Sed if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) 293210299Sed BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) 294210299Sed .addReg(SrcReg, getKillRegState(KillSrc)); 295210299Sed else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) 296210299Sed BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) 297210299Sed .addReg(SrcReg, getKillRegState(KillSrc)); 298263508Sdim else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { 299263508Sdim if (Subtarget.isV9()) { 300263508Sdim BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) 301263508Sdim .addReg(SrcReg, getKillRegState(KillSrc)); 302263508Sdim } else { 303263508Sdim // Use two FMOVS instructions. 304263508Sdim subRegIdx = DFP_FP_SubRegsIdx; 305263508Sdim numSubRegs = 2; 306263508Sdim movOpc = SP::FMOVS; 307263508Sdim } 308263508Sdim } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { 309263508Sdim if (Subtarget.isV9()) { 310263508Sdim if (Subtarget.hasHardQuad()) { 311263508Sdim BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) 312263508Sdim .addReg(SrcReg, getKillRegState(KillSrc)); 313263508Sdim } else { 314263508Sdim // Use two FMOVD instructions. 315263508Sdim subRegIdx = QFP_DFP_SubRegsIdx; 316263508Sdim numSubRegs = 2; 317263508Sdim movOpc = SP::FMOVD; 318263508Sdim } 319263508Sdim } else { 320263508Sdim // Use four FMOVS instructions. 321263508Sdim subRegIdx = QFP_FP_SubRegsIdx; 322263508Sdim numSubRegs = 4; 323263508Sdim movOpc = SP::FMOVS; 324263508Sdim } 325263508Sdim } else 326210299Sed llvm_unreachable("Impossible reg-to-reg copy"); 327263508Sdim 328263508Sdim if (numSubRegs == 0 || subRegIdx == 0 || movOpc == 0) 329263508Sdim return; 330263508Sdim 331263508Sdim const TargetRegisterInfo *TRI = &getRegisterInfo(); 332263508Sdim MachineInstr *MovMI = 0; 333263508Sdim 334263508Sdim for (unsigned i = 0; i != numSubRegs; ++i) { 335263508Sdim unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]); 336263508Sdim unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]); 337263508Sdim assert(Dst && Src && "Bad sub-register"); 338263508Sdim 339263508Sdim MovMI = BuildMI(MBB, I, DL, get(movOpc), Dst).addReg(Src); 340263508Sdim } 341263508Sdim // Add implicit super-register defs and kills to the last MovMI. 342263508Sdim MovMI->addRegisterDefined(DestReg, TRI); 343263508Sdim if (KillSrc) 344263508Sdim MovMI->addRegisterKilled(SrcReg, TRI); 345193323Sed} 346193323Sed 347193323Sedvoid SparcInstrInfo:: 348193323SedstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 349193323Sed unsigned SrcReg, bool isKill, int FI, 350208599Srdivacky const TargetRegisterClass *RC, 351208599Srdivacky const TargetRegisterInfo *TRI) const { 352206124Srdivacky DebugLoc DL; 353193323Sed if (I != MBB.end()) DL = I->getDebugLoc(); 354193323Sed 355263508Sdim MachineFunction *MF = MBB.getParent(); 356263508Sdim const MachineFrameInfo &MFI = *MF->getFrameInfo(); 357263508Sdim MachineMemOperand *MMO = 358263508Sdim MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 359263508Sdim MachineMemOperand::MOStore, 360263508Sdim MFI.getObjectSize(FI), 361263508Sdim MFI.getObjectAlignment(FI)); 362263508Sdim 363193323Sed // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 364263508Sdim if (RC == &SP::I64RegsRegClass) 365263508Sdim BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0) 366263508Sdim .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 367263508Sdim else if (RC == &SP::IntRegsRegClass) 368193323Sed BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) 369263508Sdim .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 370239462Sdim else if (RC == &SP::FPRegsRegClass) 371193323Sed BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) 372263508Sdim .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 373263508Sdim else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) 374193323Sed BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) 375263508Sdim .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 376263508Sdim else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) 377263508Sdim // Use STQFri irrespective of its legality. If STQ is not legal, it will be 378263508Sdim // lowered into two STDs in eliminateFrameIndex. 379263508Sdim BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0) 380263508Sdim .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 381193323Sed else 382198090Srdivacky llvm_unreachable("Can't store this register to stack slot"); 383193323Sed} 384193323Sed 385193323Sedvoid SparcInstrInfo:: 386193323SedloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 387193323Sed unsigned DestReg, int FI, 388208599Srdivacky const TargetRegisterClass *RC, 389208599Srdivacky const TargetRegisterInfo *TRI) const { 390206124Srdivacky DebugLoc DL; 391193323Sed if (I != MBB.end()) DL = I->getDebugLoc(); 392193323Sed 393263508Sdim MachineFunction *MF = MBB.getParent(); 394263508Sdim const MachineFrameInfo &MFI = *MF->getFrameInfo(); 395263508Sdim MachineMemOperand *MMO = 396263508Sdim MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 397263508Sdim MachineMemOperand::MOLoad, 398263508Sdim MFI.getObjectSize(FI), 399263508Sdim MFI.getObjectAlignment(FI)); 400263508Sdim 401263508Sdim if (RC == &SP::I64RegsRegClass) 402263508Sdim BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0) 403263508Sdim .addMemOperand(MMO); 404263508Sdim else if (RC == &SP::IntRegsRegClass) 405263508Sdim BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0) 406263508Sdim .addMemOperand(MMO); 407239462Sdim else if (RC == &SP::FPRegsRegClass) 408263508Sdim BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0) 409263508Sdim .addMemOperand(MMO); 410263508Sdim else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) 411263508Sdim BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0) 412263508Sdim .addMemOperand(MMO); 413263508Sdim else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) 414263508Sdim // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be 415263508Sdim // lowered into two LDDs in eliminateFrameIndex. 416263508Sdim BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0) 417263508Sdim .addMemOperand(MMO); 418193323Sed else 419198090Srdivacky llvm_unreachable("Can't load this register from stack slot"); 420193323Sed} 421193323Sed 422198090Srdivackyunsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const 423198090Srdivacky{ 424198090Srdivacky SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>(); 425198090Srdivacky unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg(); 426198090Srdivacky if (GlobalBaseReg != 0) 427198090Srdivacky return GlobalBaseReg; 428198090Srdivacky 429198090Srdivacky // Insert the set of GlobalBaseReg into the first MBB of the function 430198090Srdivacky MachineBasicBlock &FirstMBB = MF->front(); 431198090Srdivacky MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 432198090Srdivacky MachineRegisterInfo &RegInfo = MF->getRegInfo(); 433198090Srdivacky 434263763Sdim const TargetRegisterClass *PtrRC = 435263763Sdim Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; 436263763Sdim GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC); 437198090Srdivacky 438206124Srdivacky DebugLoc dl; 439198090Srdivacky 440198090Srdivacky BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg); 441198090Srdivacky SparcFI->setGlobalBaseReg(GlobalBaseReg); 442198090Srdivacky return GlobalBaseReg; 443198090Srdivacky} 444